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Core-Microconverter-Slide28

The flash on the ADuC702x series has a 16-bit bus. This means that when running at full speed with the clock divider register set to a divide by one, 2 clock cycles are required to execute one 16-bit instruction. When the clock divider is increased, the spare clock cycles are used to fetch the second 16-bits of the instruction, resulting in single cycle operation from FLASH at frequencies below 20.5MHz.

PTM Published on: 2006-06-30