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LPC1700 Microcontroller Slide 29
The GPDMA block is an AHB Bus master. It has eight DMA channels with a four-word FIFO per channel. The GPDMA supports the following peripherals: SSP, I2S, UART, ADC and DAC. The DMA can also be triggered by a timer match condition. As shown in the image, GPIO registers are accessible by the GPDMA controller to allow DMA data to or from GPIOs, synchronized to any DMA request. Single and burst requests are supported. This table also shows which peripherals support single requests and which peripherals support burst requests.
PTM Published on: 2011-11-02