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LPC1700 Microcontroller Slide 15
An on-chip 512KB Flash is provided with zero wait-state performance as well as a Flash Accelerator. On-chip SRAM, totaling 64KB, is also included which is further broken down into 32KB SRAM (accessible by the CPU and DMA controller on a higher speed bus) and two additional 16KB SRAMs (separate slave ports on the AHB multilayer matrix). The breakup is a key system feature since it allows the 3 AHB masters to spread over 3 separate SRAMs that can be accessed simultaneously. Finally, an on-chip 8KB ROM is included which contains all the APIs for Flash program/erase functions.
PTM Published on: 2011-11-02