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LPC1700 Microcontroller Slide 5
This block diagram represents the LPC1700 broken into two parts. On the top is the Cortex-M3 core, DMA controller, Ethernet, and USB blocks. On the right hand side are the different internal memories: SRAM, flash and ROM. Interfacing the Flash to the rest of the chip is the Flash accelerator module. Connecting all the blocks with the different peripherals is the multi-layer AHB bus matrix. The LPC17xx uses a multi-layer AHB matrix to connect the Cortex-M3 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slaves ports of the matrix to be accessed simultaneously by different bus masters.
PTM Published on: 2011-11-02