Serial Peripheral Interface, or SPI, is a synchronous serial communications interface. The SPI implementation consists of a shift register for the receive and transmit data directions. There are typically additional data registers for both the transmit and receive directions to provide double buffering to reduce the probability of data loss. As the device transmits the data, the receive data stream is latched using the same clock source providing a full duplex operation. Some implementations may use a half duplex configuration where the data is transmitted and received on a single wire. The master node generates the clock for the interface and the slave device accepts the clock. Both devices are required to be configured for the same clock rates and phase. For example, if data was to be transmitted at 100kbps and the data is valid on the rising clock then the master needs to pass the data and have it stable when the clock rises and the slave has to be able to latch the data on the same edge of the clock. This page shows some standard naming conventions used for SPI interface. MOSI is the Master Out Slave In and is the data transmitted from the master device to a slave device. It is configured through the I/O as a push-pull output. The MISO signal is the Master In Slave Out and is the data received by the master. The I/O for these pins should be set as inputs. The SCK is the clock signal and the NSS is the slave select (or chip select) signal to enable the active slave device.