This slide shows a block diagram of the MAX® V’s Logic Element which leverages Intel’s® FPGA logic technology. It enables enhanced register packing due to a combination of LUT and register chains. The register can be used on the LE input as well as the LE output. Register feedback is useful when the user wants to register the input of a block in a block-based design. This saves the user from having to consume an entire LE to implement an input register.