The Si5330 is a low jitter, low skew clock buffer that is ideal for clock distribution. The device supports operation over the 5 to 700 MHz range. Some Si5330 versions support differential clock buffering (e.g. 1:4 LVPECL clock buffer). Some Si5330 versions support single ended clock buffering (e.g. 1:8 CMOS clock buffer), some Si5330 versions support differential to single-ended or single-ended to differential clock buffering. These devices are useful in applications where the design needs to generate multiple output clocks that are at a different clock format than the reference clock. The skew between output clocks is well-controlled and guaranteed to be less than ±100 ps. The delay through the device is 2.5 ns. The device core is powered by an independent supply running at 1.8 V, 2.5 V, or 3.3 V. The four outputs are powered by a single supply separate from the core. The outputs can be run at 1.5 V, 1.8 V, 2.5 V, or 3.3 V.