Traditional clock architectures may require discrete components for clock format translation (examples: singled-ended to differential, differential to single-ended or differential to differential). These components are relatively expensive, so the cost of multiple level translators can significantly impact the total cost of the timing architecture. Often level translators are selected at the end of the design process once the main IC selection has been made. The Si5335 supports a programmable clock signal format and supply voltage on every output clock. This minimizes PCB cost and design complexity. This also makes it easy for designers to use the Si5335 in mixed-supply applications, where one clock may need timing referenced to 1.8 V and a second clock requires a 3.3 V-based supply. Skyworks Solutions offers a termination guideline in the Si533x/5x datasheets that provide the recommended termination for each of the output clock formats supported: CMOS, SSTL, HSTL, LVDS, LVPECL, CML and HCSL.