A complete AD conversion consists of three components: an A/D conversion start delay time (tD), a sampling time (tSPL ) which is the time required for the sample and hold capacitor to charge, and the actual successive approximation time (tSAM ) which is fixed at 25 clock cycles. When using repeat mode, the start delay only occurs for the first conversion in the sweep. The following channel conversion times are equal to the sample time plus the conversion time. Some ADCs can produce errors if they encounter a high source impedance which does not allow the sample capacitor to charge sufficiently. The RX ADC has the ability to modify the length of time the sample capacitor is connected to the input, allowing the capacitor to fully charge even with high source impedances.