This figure shows a block diagram of the 10-Bit A/D converter in the RX MCU. AVcc and AVss are the analog inputs that power the block while Vref high and Vref low are the reference inputs which drive the 10-bit D/A used in the successive approximation process. On the right side of the block diagram the internal data bus connection is shown along with the interrupt signal. The RX ADC allows  asynchronous triggering using the ADTRG pin and also provides a synchronized trigger. The module can also be triggered by software or synchronously from various timer signals including compare match and input capture functions. Please refer to the hardware manual for the specific device to verify which timer signals can be used. The RX ADC has various clocks which can be selected as the source for the AD clock. In the diagram, it can be seen that P-Clock or P-Clock divided by 2,4, or 8 can be selected. Please refer to the hardware manual for the specific device to determine which clock sources can be selected and for details on setting up the clock dividers.