The R8C Family MCU CPU core operates with a versatile set of 89 instructions to generate efficient code and maximize performance. Those instructions perform from very simple to highly complex functions, supporting memory-to-memory, register-to-memory, and register-to-register operations. Twenty of the instructions execute in a single clock cycle and frequently used functions, such as MOVE and JUMP, are only one byte long to help reduce overall code size. The instruction set provides stack frame manipulation instructions for C language development, as well as 4-bit transfer operations. There are also powerful bit manipulation instructions, such as Bit Set and Bit Not. Powerful mathematical instructions such as RMPA and SMOVB turn R8C Family devices into high-performance MCUs with DSP functionality. To optimize the use of the instruction set, the R8C CPU provides eight general addressing modes and six special addressing modes. Finally, to complement the R8C architecture and instruction set, Renesas has developed an advanced compiler toolchain that is tuned to deliver the most efficient code possible. In summary, the register architecture of the R8C CPU core and its efficient instruction set, plus the processing of the efficient, optimized Renesas C compiler, are a combination that produces compact code that runs fast.