Power is the next feature provided with the R8C Family MCUs. As mentioned previously, the optimized CISC architecture at the heart of these MCUs operates at clock speeds up to 20MHz. It has two register banks, labeled “B0” and “B1” in this diagram. They consist of data, address, and specialized registers. This dual-register structure allows the CPU to alternate between the banks for fast interrupt response, a feature that the Renesas C compiler puts to good use. The general purpose registers can be configured in 8-, 16-, or 32-bit widths to take full advantage of the instruction set and boost execution speed. A 20-bit program counter (PC) allows the MCUs to address up to 1MB of linear memory space. Two stack-pointer registers (USP and ISP) provide flexible allocation of RAM resources and enhance execution with real-time operating systems. Also, a fast, 16-bit  x 16-bit hardware multiplier can perform advanced instructions like those typically offered by digital signal processors. In the CPU core, the 20-bit register INTBL stores the starting address of the interrupt vector table, which can be placed in the most appropriate location. The static-base (SB) register provides additional flexibility because it can be used as an alternative to the frame-base (FB) register for relative-addressing operations. The 16-bit flag register (FLG) provides status flags and configures CPU resources such as bank switching. More details on the CPU core are provided in the R8C Family Architecture Overview course. Finally, the R8C's architecture can access any location of the program memory or SRAM in a single clock cycle. This is even more significant for devices over 64KB of memory space, as most other 8-bit MCUs require bank switching to access the extra memory, thus reducing the overall performance.