In many R8C devices, Renesas incorporates a Data Transfer Controller or “DTC”. This hardware subsystem provides functionality similar to a DMA engine typically found in 16- and 32-bit microcontrollers. The main difference is that the DTC has scalable channels as opposed to a fixed number of channels found in a typical DMA. This scalability is accomplished by using virtual channels configured through the built-in SRAM. If only two channels are required, then the user's program will use a proportional amount of RAM to configure and control the operation of the DTC. One other powerful feature of the DTC is that channels can be chained together to trigger a series of operations without any CPU intervention. DTC supports single or repeat transfers with automatic address increment. The latter mode is particularly useful when the DTC needs to transfer a block of data from one location to another. The diagram here illustrates the sequence of events followed by the DTC. The start of the DTC operation can be triggered by software or from any interrupt source. Upon triggering, the DTC uses the configuration/control data stored in the R8C's SRAM which is defined by the user. Step 5 and 6 in this sequence shows the actual data transfer to/from memory. The data source can be ROM, or any location in RAM including the SFRs (Special Function Registers) which can obtain any of the memory-mapped peripheral data. The data transfer destination is RAM, which can be defined as general purpose or peripherals such as I/O. Upon data transaction, the DTC will write back information to the RAM allocated for DTC use. This final piece of data can be used to record/update information such as addressing, or trigger a chained event. By using the DTC, R8C devices can achieve higher overall performance, while it can reduce power consumption by “disabling” the CPU while the DTC performs data transfer operations. For example, using the DTC transfer of multiple A/D conversion results to RAM for further manipulation; such as filtering; can be done at least 60% faster compared to a standard operation.