Slide 1 Slide 2 Slide 3 Slide 4 Slide 5 Slide 6 Slide 7 Slide 8 Slide 9 Slide 10 Slide 11 Slide 12 Slide 13 Slide 14 Slide 15 Slide 16 Slide 17 Slide 18 Slide 19 Slide 20 Slide 21 Slide 22 Slide 23 Slide 24 Slide 25 Slide 26 Slide 27 Slide 28 Slide 29 Slide 30 Slide 31 Slide 32 Slide 33 Slide 34 Slide 35 Slide 36 Slide 37 Slide 38 Slide 39 Slide 40 Slide 41 Slide 42 Slide 43 Product List
power savings
There are several power management options available in the LPC3250. This device can be operated as low as 0.9V. The on-chip PLLs cannot be used at this voltage so the chip will be operating at a lower frequency. This is suitable for very low power standby modes where system operation is required but performance can be compromised. The HIGHCORE pin can also be used as an indicator to switch to a lower voltage. The STOP mode is the operational mode of the LPC3250 when the multi-layer bus matrix is disabled and the CPU clock is stopped. The RTC can be used to time the LPC3250 as well. The RTC oscillator uses a 32 kHz crystal and runs at much lower power than the main crystal oscillator. The RTC 397x PLL multiplies the RTC clock to a frequency which can be further multiplied by the main PLL to generate the > 200 MHz CPU clock. Additionally, the on-chip SRAM is broken up into four blocks of 64KB which can be individually powered down to save power.
PTM Published on: 2011-11-02