The P2 and P1 (not the P1022/13-not shown here) processors are pin compatible offerings, enabling the designer to scale from 533MHz to 1.2GHz. Also, NXP provides a pin muxing tool which enables design using the QUICC Engine derivative solution the P1021/12. Some key differences to note include: the P1 series, including the P1022/13, has a core frequency of up to 1000MHz, while the P2 series goes up to 1.2GHz; the P1 series has half the L2 cache of P2; the P2 adds 64-bit DDR; TDM is not available on P2, but is available on P1 which provides the needed support interface for applications like voice over IP; the P1012 and 1021 offer a Utopia interface with the QUICC Engine for multi-protocol support, like HDLC and ATM for telecom applications along with Profibus and Profinet for industrial applications. The QUICC Engine enables customers to offload these protocols, while competitors’ processors have to have an external FPGA to perform the same function. NXP does in one chip what competitors have to do in two - saves on BOM and board real estate.