So what does this mean? Recall the evolution of Flash and its capabilities in its early days. One example is that in designing for low and ultra low power operation, memory access speeds would be restricted (to say 8 MHz) via the surrounding memory controller/power management circuitry. This reduces the power consumption of the memory IP. Typically, for most applications, system speeds can be 2 – 3x higher than the memory access speeds before memory access becomes a bottleneck. But even this can be alleviated via, for example, a small, integrated SRAM cache in the product. This approach could balance the need for performance and ultra low power memory access operation. The second major limitation is memory density and size. FRAM today is ideally suited for devices needing less than 128/256 KB of embedded memory. While TI has successfully demonstrated manufacturability of up to 4 Mbytes FRAM, the FRAM on MSP430 devices only contains up to 16kB of data on this first series of devices, the MSP430FR57xx family. Plans are in place to improve both the speed and size of FRAM in the coming years.