Place at least one 1µF low ESR capacitor very close to the IC between VDD and GND pins in order to reduce parasitic inductance in fast switching loop. Also reduce the loop formed with the MOSFET being driven to reduce parasitic inductance. Power Dissipation of the IC should be kept under its Maximum Power Dissipation limit. IC power dissipation can be calculated using above equations. Additionally, users will want to reduce the loop formed with the MOSFET being driven to reduce parasitic inductance. Power Dissipation of the IC should be kept under its Maximum Power Dissipation limit. IC power dissipation can be calculated using above equations.