A zero delay buffer is a device that can fanout one clock signal into multiple clock signals with zero delay and very low skew between the outputs. A zero delay buffer is similar to a standard buffer except it employs an integrated PLL with feedback to synchronize the output clock to the input clock with no delay, aligning the rising edges of the clock outputs to the rising edge of the input clock. The input phase detector checks the rising edges of the feedback clock with the reference clock and adjusts the control voltage to the VCO. A phase lag or phase lead can be added to the output clocks, not tied to the feedback pin, but the output clock in the feedback path will always be synchronized to the input clock at VDD/2.