A converter’s performance when employing parallel FETs, can be quantitatively compared by creating a meaningful switching Parallel Impact Figure, or PIF. By definition, the PIF will encompass only switching capability. Omitted are the additional on-resistance and thermal benefits that come from distributing heat loads on the PCB. The dv/dt and di/dt immunity have been shown as key performance contributors for predicting paralleled FET converter performance, and therefore it is logical to include these quantities into the definition of PIF. Furthermore, the definition of PIF enables comparison between the paralleled FET converter performance with that of a single switch equivalent. The PIF provides an indication of the limits within which the converter will function within the switch’s immunity limits when using paralleled devices compared to a single FET equivalent. As a shorthand, this slide shows the equation using dv/dt and di/dt. The actual calculation uses the minimum switching time that causes the device to false trigger either from dv/dt, or from di/dt.