MachXO3™ ultra-low density family of FPGAs

The MachXO3L is Lattice's newest instant-on, non-volatile, small footprint FPGAs that use advanced packaging technology to enable the lowest cost devices. The family features the latest in small packaging, low-power, and aggressive cost combined with fast performance. The MachXO3L family spans from 640 to 6900 LUTs. It is available in lower power E (1.2 V core) version or C (3.3/2.5 V core) versions.

Breakthrough I/O Density at the Lowest Cost per I/O – Programmable bridging and I/O expansion has never been more affordable with up to 540 I/O and priced at 1 cent per I/O.

Maximum I/O, Minimum Size – Smallest BGA packages with 0.4 mm, 0.5 mm, and 0.8 mm ball-spacing options.

Instant Programmable Bridging and I/O Expansion – Maximum flexibility with instant-on access and multi-time programmability.

CSI-2 Image Sensor Interfacing

• Supports CSI-2 high speed differential signaling
• Both Rx and Tx interfaces
• From 1-4 lanes of CSI-2 at up to 800 Mbps
• Can be implemented in a 49 wlcsp (3.2 mm x 3.2 mm)
• RAW, YUV or RGB supported

DSI LCD Display Interfacing

• Supports DSI transmit signaling
• HS (High-Speed) Mode transmit
• LP (Low-Power) Mode transmit and receive
• Can be implemented in a 49 wlcsp (3.2 mm x 3.2 mm)
• Supports DSI formats RGB, YCbCr and User Defined
• Input bus can also be DSI to enable LCD screen replacement

Microprocessor Interface Expansion

• Save cost by adding GPIO to low-cost microcontrollers
• Add additional SPI and I²C interfaces to system control processors
• Perform voltage-level translation with ease
• Simplify system management with PLD implementation of system status registers