A basis for this topic will define the real system latency of an access. Latency is defined as "the time the memory controller issues a read to the time the data is returned to the controller from that request". Looking at this as the latency, the value that is arrived at includes: controller logic, interface logic for the FPGA, I/O structures of the FPGA, full access time of the memory device, and the return I/O, logic, and controller path in the FPGA. What has been learned is that for devices like accelerator engines and QDR SRAMs, the overhead of the logic and I/O of the FPGA is a significant portion of the system latency value for accessing the memory; not the device access time. However, for devices like DRAM and HBM, the access time of the memory is a significant portion of overall memory access, so the FPGA I/O and controller logic provide a smaller portion of the overall access latency, keeping the device latency as the significant contributor. In effect, when the device latency is a small portion of the system access latency, the impact of a few nanoseconds is not a large contributor to the latency impact of reads of the memory. This is the case for accelerator engines vs. today's high-speed SRAMs like QDRs. Since system latency is similar, the other factors such as density and cost can become larger factors in the decision process.