The MxL7704-X factory configurations are optimized for Xilinx® Zynq ® Ultrascale+™ ZU2, ZU3 MPSoCs. Output voltages are preset to: 3.3 V for the LDO, 3.3 V for Analog and I/O rails, 1.8 V for additional I/O, 1.35 V for DDR3L memory, and 0.85V for the core rail. Sequencing is set core first, so the 0.85 V rail powers up first, followed by SEQ_EN, 1.8 V, and the 3.3 V and 1.35 V rails power up last. PGOOD1 is not used and PGOOD2 is assigned to logical AND of all bucks. The switching frequency is set to 1 MHz. The MxL7704 offers a register that allows the user to choose whether a fault on a given channel will only affect that channel or cause an entire restart of the power system. The MxL7704-X is pre-configured with this register set for “chip” fault. This means a fault on any channel will cause the other channels to simultaneously power down based on their power down settings. Once all channels are powered down, a 1 ms delay will gate the restart of the channel or chip and soft off is enabled.