Analog Devices Inc. 的 OP282,482 規格書

UP282/UP482 3 3 3 3 3 :l :l 3333 33:3 3333333 @é E? E I: ANALOG DEVICES CECE EE _|_ .rEErEE: E E E E E I: ..\ Ducumenlfeedbick
Dual/Quad,
Low Power, High Speed
JFET Operational Amplifiers
Data Sheet
OP282/OP482
Rev. I Document Feedback
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FEATURES
High slew rate: 9 V/µs
Wide bandwidth: 4 MHz
Low supply current: 250 µA/amplifier maximum
Low offset voltage: 3 mV maximum
Low bias current: 100 pA maximum
Fast settling time
Common-mode range includes V+
Unity-gain stable
14-ball wafer level chip scale for quad
APPLICATIONS
Active filters
Fast amplifiers
Integrators
Supply current monitoring
GENERAL DESCRIPTION
The OP282/OP482 dual and quad operational amplifiers feature
excellent speed at exceptionally low supply currents. The slew
rate is typically 9 V/µs with a supply current of less than 250 µA
per amplifier. These unity-gain stable amplifiers have a typical
gain bandwidth of 4 MHz.
The JFET input stage of the OP282/OP482 ensures that the bias
current is typically a few picoamps and is less than 500 pA over
the full temperature range. The offset voltage is less than 3 mV
for the dual amplifier and less than 4 mV for the quad amplifier.
With a wide output swing (within 1.5 V of each supply), low
power consumption, and high slew rate, the OP282/OP482 are
ideal for battery-powered systems or power-restricted applica-
tions. An input common-mode range that includes the positive
supply makes the OP282/OP482 an excellent choice for high-
side signal conditioning.
The OP282/OP482 are specified over the extended industrial
temperature range. The OP282 is available in the standard
8-lead, narrow SOIC and MSOP packages. The OP482 is
available in the PDIP and narrow SOIC packages, as well as
a 14-ball WLCSP.
PIN CONNECTIONS
1
2
3
45
6
7
8
OUT A
–IN A
+IN A
V– OP-482
V+
OUT B
–IN B
+IN B
OP282
00301-001
Figure 1. 8-Lead, Narrow-Body SOIC (S-Suffix) [R-8]
00301-002
OUT A
1
–IN A
2
+IN A
3
V–
4
V+
8
OUT B
7
–IN B
6
+IN B
5
OP282
TOP VIEW
(Not to Scale)
Figure 2. 8-Lead MSOP [RM-8]
1
2
3
4
5
6
7
14
13
12
11
10
9
8
OUT A
–IN A
+IN A
V+
+IN B
–IN B
OUT B
OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C
OP482
– + + –
– + + –
00301-003
Figure 3. 14-Lead PDIP (P-Suffix) [N-14]
1
2
3
4
5
6
7
14
13
12
11
10
9
8
OUT A
–IN A
+IN A
V+
+IN B
–IN B
OUT B
OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C
OP482
00301-004
Figure 4. 14-Lead, Narrow-Body SOIC (S-Suffix) [R-14]
TOP VIEW (BALL SIDE DOWN)
Not to Scale
00301-048
BALLA1 CORNER
OUT A
+IN D
V–
+IN C
OUT C
OUT D
–IN A
V+
–IN B
OUT B
–IN D
+IN A
+IN B
–IN C
A
B
C
D
E
F
123
G
H
J
Figure 5. 14-Ball WLCSP [CB-14-2]
OP282/OP482 Data Sheet
Rev. I | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Pin Connections ............................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Absolute Maximum Ratings ............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution...................................................................................4
Typical Performance Characteristics ..............................................5
Applications Information .............................................................. 12
High-Side Signal Conditioning ................................................ 12
Phase Inversion ........................................................................... 12
Active Filters ............................................................................... 12
Programmable State Variable Filter ......................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 16
REVISION HISTORY
9/13—Rev. H to Rev. I
Changes to Figure 5 .......................................................................... 1
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 16
9/10—Rev. G to Rev. H
Added WLCSP .................................................................... Universal
Changes to Features Section............................................................ 1
Changes to General Description Section ...................................... 1
Added Figure 5; Renumbered Sequentially .................................. 1
Changes to Large-Signal Voltage Gain Parameter, Table 1 ......... 3
Changes to Table 2, Thermal Resistance Section, and Table 3 ... 4
Change to Figure 30 ......................................................................... 9
Added Figure 53 .............................................................................. 16
Changes to Ordering Guide .......................................................... 16
7/08—Rev. F to Rev. G
Changes to Phase Inversion Section ............................................ 12
Deleted Figure 45 ............................................................................ 12
Added Figure 45 and Figure 46..................................................... 12
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 16
10/04—Rev. E to Rev. F
Deleted 8-Lead PDIP ......................................................... Universal
Added 8-Lead MSOP ......................................................... Universal
Changes to Format and Layout ......................................... Universal
Changes to Features .......................................................................... 1
Changes to Pin Configurations ....................................................... 1
Changes to General Description .................................................... 1
Changes to Specifications ................................................................ 3
Changes to Absolute Maximum Ratings ....................................... 4
Changes to Table 3 ............................................................................ 4
Added Figure 5 through Figure 20; Renumbered
Successive Figures .............................................................................. 5
Updated Figure 21 and Figure 22 .................................................... 7
Updated Figure 23 and Figure 27 .................................................... 8
Updated Figure 29 ............................................................................. 9
Updated Figure 35 and Figure 36 ................................................. 10
Updated Figure 43 .......................................................................... 11
Changes to Applications Information ......................................... 12
Changes to Figure 44 ...................................................................... 12
Deleted OP282/OP482 Spice Macro Model Section .................... 9
Deleted Figure 4 ................................................................................. 9
Deleted OP282 Spice Marco Model ............................................. 10
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 14
10/02—Rev. D to Rev. E
Edits to 8-Lead Epoxy DIP (P-Suffix) Pin ...................................... 1
Edits to Ordering Guide ................................................................... 3
Edits to Outline Dimensions ......................................................... 11
9/02—Rev. C to Rev. D
Edits to 14-Lead SOIC (S-Suffix) Pin ............................................. 1
Replaced 8-Lead SOIC (S-Suffix) ................................................. 11
4/02—Rev. B to Rev. C
Wafer Test Limits Deleted ................................................................ 2
Edits to Absolute Maximum Ratings .............................................. 3
Dice Characteristics Deleted ............................................................ 3
Edits to Ordering Guide ................................................................... 3
Edits to Figure 1 ................................................................................. 7
Edits to Figure 3 ................................................................................. 8
20-Position Chip Carrier (RC Suffix) Deleted ........................... 11
Data Sheet OP282/OP482
Rev. I | Page 3 of 16
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
At VS = ±15.0 V, TA = 25°C, unless otherwise noted; applies to both A and G grades.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS OP282 0.2 3 mV
OP282, −40°C ≤ TA ≤ +85°C 4.5 mV
OP482
0.2
4
mV
OP482, −40°C ≤ TA ≤ +85°C 6 mV
Input Bias Current IB VCM = 0 V 3 100 pA
VCM = 0 V1 500 pA
Input Offset Current IOS VCM = 0 V 1 50 pA
VCM = 0 V1 250 pA
Input Voltage Range −11 +15 V
Common-Mode Rejection Ratio CMRR −11 V ≤ VCM ≤ +15 V, −40°C ≤ TA ≤ +85°C 70 90 dB
Large-Signal Voltage Gain AVO RL = 10 kΩ, VO = ±13.5 V 20 V/mV
RL = 10 kΩ, −40°C ≤ TA ≤ +85°C 15 V/mV
Offset Voltage Drift ΔVOS/ΔT 10 µV/°C
ΔI
B
/ΔT
8
pA/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 10 kΩ 13.5 13.9 V
Output Voltage Low VOL RL = 10 kΩ −13.9 −13.5 V
Short-Circuit Limit ISC Source 3 10 mA
Sink −12 −8 mA
Open-Loop Output Impedance ZOUT f = 1 MHz 200 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = ±4.5 V to ±18 V, −40°C ≤ TA ≤ +85°C 25 316 µV/V
Supply Current/Amplifier ISY VO = 0 V, −40°C ≤ TA ≤ 85°C 210 250 µA
Supply Voltage Range VS ±4.5 ±18 V
DYNAMIC PERFORMANCE
Slew Rate SR RL = 10 kΩ 7 9 V/µs
Full-Power Bandwidth BWP 1% distortion 125 kHz
t
S
To 0.01%
1.6
µs
Gain Bandwidth Product GBP 4 MHz
Phase Margin ØM 55 Degrees
Voltage Noise en p-p 0.1 Hz to 10 Hz 1.3 µV p-p
Voltage Noise Density en f = 1 kHz 36 nV/√Hz
Current Noise Density in 0.01 pA/√Hz
1 The input bias and offset currents are characterized at TA = TJ = 85°C. Bias and offset currents are guaranteed but not tested at −40°C.
Am ESD (ele‘Qrostili‘ dischirge) sensitive device. Charged dewces and mm“ boards (an duthavge wvmom de‘ecnon Almough ms pvodun fea‘uves palemed or propuelavy pvmemon (mm, damage may occur on devvces subjened m high enevgy ESD Thevefave, pvupev ESD pvemunans should b2 \aken u: avoxd permmame degradanon m \055 o! mnmonamy
OP282/OP482 Data Sheet
Rev. I | Page 4 of 16
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage ±18 V
Input Voltage
±18 V
Differential Input Voltage1 36 V
Output Short-Circuit Duration Indefinite
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering 60 sec)
300°C
1 For supply voltages less than ±18 V, the absolute maximum input voltage is
equal to the supply voltage.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device in
socket for PDIP. θJA is specified for a device soldered in the circuit
board for SOIC_N, MSOP, and WLCSP packages. This was
measured using a standard 4-layer board.
Table 3.
Package Type θJA θJC Unit
8-Lead MSOP [RM] 142 45 °C/W
8-Lead SOIC_N (S-Suffix) [R] 120 45 °C/W
14-Lead PDIP (P-Suffix) [N] 83 39 °C/W
14-Lead SOIC_N (S-Suffix) [R] 112 35 °C/W
14-Ball WLCSP [CB]1, 2 70 16 °C/W
1 Simulated thermal numbers per JESD51-9.
2 Junction-to-board thermal resistance.
ESD CAUTION
Data Sheet OP282/OP482
Rev. I | Page 5 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
FREQUENCY (Hz)
OPEN-LOOP GAIN (dB)
1k
–40
–20
60
80
10k 1M 10M
00301-005
100k
20
40
0
V
S
= ±15V
T
A
= 25°C
PHASE (Degrees)
–45
135
45
90
0
–90
180
Figure 6. OP282 Open-Loop Gain and Phase vs. Frequency
TEMPERATURE (°C)
OPEN-LOOP GAIN (V/mV)
–75
0
5
35
45
–25 100 125
00301-006
25
15
25
10
V
S
= ±15V
R
L
= 10kΩ
20
30
40
75500–50
Figure 7. OP282 Open-Loop Gain vs. Temperature
LOAD CAPACITANCE (pF)
OVERSHOOT (%)
0
0
10
70
80
200 400 500
00301-007
30
50
20
40
60
300100
V
S
= ±15V
R
L
= 2kΩ
V
IN
= 100mV p-p
A
VCL
= 1
T
A
= 25°C
+OS
–OS
Figure 8. OP282 Small-Signal Overshoot vs. Load Capacitance
FREQUENCY (Hz)
CLOSED-LOOP GAIN (dB)
1k
–30
–20
60
70
10k 1M 10M
00301-008
100k
20
40
0
V
S
= ±15V
T
A
= 25°C
–10
50
10
30
A
VCL
= 1
00
A
VCL
= 1
0
A
VCL
= 1
Figure 9. OP282 Closed-Loop Gain vs. Frequency
TEMPERATURE (°C)
SLEW RATE (V/µs)
–75
0
5
30
–25 100 125
00301-009
25
15
25
10
V
S
= ±15V
R
L
= 10kΩ
C
L
= 50pF
20
75500–50
–SR
+SR
Figure 10. OP282 Slew Rate vs. Temperature
TEMPERATURE (°C)
INPUT BIAS CURRENT (pA)
–75
0.1
1000
–25 100 125
00301-010
25
1
100
10
75500–50
V
S
= ±15V
V
CM
= 0V
Figure 11. OP282 Input Bias Current vs. Temperature
OP282/OP482 Data Sheet
Rev. I | Page 6 of 16
FREQUENCY (Hz)
VOLTAGE NOISE DENSITY (nV/√Hz)
10
1
1000
100 10k
00301-011
1k
100
10
V
S
= ±15V
T
A
= 25°C
Figure 12. OP282 Voltage Noise Density vs. Frequency
COMMON-MODE VOLTAGE (V)
INPUT BIAS CURRENT (pA)
–15
0.1
1000
10 15
00301-012
–5
1
100
10
50–10
V
S
= ±15V
T
A
= 25°C
Figure 13. OP282 Input Bias Current vs. Common-Mode Voltage
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
0
450
480
±20
00301-013
±10
455
465
460
±15±5
T
A
= 25°C
470
475
Figure 14. OP282 Supply Current vs. Supply Voltage
SUPPLY VOLTAGE (V)
OUTPUT VOLTAGE SWING (V)
0
–20
20
±20
00301-014
±10
–15
–5
–10
±15±5
T
A
= 25°C
R
L
= 10kΩ
0
15 V
OH
V
OL
5
10
Figure 15. OP282 Output Voltage Swing vs. Supply Voltage
FREQUENCY (Hz)
OUTPUT IMPEDANCE (Ω)
1k
0.1
100
1000
10k 1M100
00301-015
100k
1
10
V
S
= ±15V
T
A
= 25°C
A
VCL
= 100
A
VCL
= 10
A
VCL
= 1
Figure 16. OP282 Closed-Loop Output Impedance vs. Frequency
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
–50
450
480
125
00301-016
25
455
750
460
475
465
470
–25 50 100
Figure 17. OP282 Supply Current vs. Temperature
/ \ sou
Data Sheet OP282/OP482
Rev. I | Page 7 of 16
LOAD RESISTANCE (Ω)
ABSOLUTE OUTPUT VOLTAGE (V)
0
6
16
1k 10k100
00301-017
2
4
V
S
= ±15V
T
A
= 25°C
V
OL
V
OH
12
8
10
14
Figure 18. OP282 Absolute Output Voltage vs. Load Resistance
FREQUENCY (Hz)
PSRR (dB)
1k
–60
40
140
10k 1M100
00301-018
100k
0
20
–40
–20
60
100
120
80
–PSRR
+PSRR
VS = ±15V
TA = 25°C
Figure 19. OP282 PSRR vs. Frequency
TEMPERATURE (°C)
SHORT-CIRCUIT CURRENT (mA)
–50
0
14
125
00301-019
25
4
750
6
12
8
10
–25 50 100
2
SINK
SOURCE
V
S
= ±15V
T
A
= 25°C
Figure 20. OP282 Short-Circuit Current vs. Temperature
FREQUENCY (Hz)
MAXIMUM OUTPUT SWING (V p-p)
100
0
5
25
30
1k 100k 1M
00301-020
10k
15
20
10
V
S
= ±15V
T
A
= 25°C
R
L
= 10kΩ
A
VCL
= 1
Figure 21. OP282 Maximum Output Swing vs. Frequency
FREQUENCY (Hz)
CMRR (dB)
1k
–60
40
140
10k 1M100
00301-021
100k
0
20
–40
–20
60
100
120
80
V
S
= ±15V
T
A
= 25°C
Figure 22. OP282 CMRR vs. Frequency
V
OS
(µV)
UNITS
–2000
0
200
00301-022
–400
80
–1200
120
160
40
400 1200 2000
V
S
= ±15V
T
A
= 25°C
300 × OP282
(600 OP AMPS)
0
Figure 23. OP282 VOS Distribution, SOIC_N Package
OP282/OP482 Data Sheet
Rev. I | Page 8 of 16
TCVOS (µV/°C)
UNITS
0
0
400
00301-023
20
80
16
120
160
40
28 32 3624
200
280
320
360
240
4128
VS = ±15V
300 × OP282
(600 OP AMPS)
Figure 24. OP282 TCVOS Distribution, SOIC_N Package
FREQUENCY (Hz)
1k 10k 100k 1M 100M
10M
80
OPEN-LOOP GAIN (dB)
PHASE (Degrees)
90
135
0
45
180
60
40
20
0
V
S
= ±15V
T
A
= 25°C
00301-024
Figure 25. OP482 Open-Loop Gain and Phase vs. Frequency
12510050 75250–75 –50 –25
TEMPERATURE (
°
C)
OPEN-LOOP GAIN (V/mV)
30
35
25
20
15
10
5
V
S
= ±15V
R
L
= 10k
Ω
00301-025
0
Figure 26. OP482 Open-Loop Gain vs. Temperature
OVERSHOOT (%)
5000300
100 200 400
70
10
0
60
50
40
30
20
LOAD CAPACITANCE (pF)
A
VCL
= 1
NEGATIVE EDGE
V
S
= ±15V
R
L
= 2k
Ω
V
IN
= 100mV p-p
00301-026
A
VCL
= 1
POSITIVE EDGE
Figure 27. OP482 Small-Signal Overshoot vs. Load Capacitance
FREQUENCY (Hz)
1k 10k 100k 1M 100M10M
60
CLOSED-LOOP GAIN (dB)
40
20
10
0
50
30
–10
–20
00301-027
A
VCL
= 10
A
VCL
= 1
A
VCL
= 100
V
S
= ±15V
T
A
= 25°C
Figure 28. OP482 Closed-Loop Gain vs. Frequency
–SR
–75
TEMPERATURE (°C)
–50 –25 025 50 75 100 125
5
10
25
15
20
+SR
SLEW RATE (V/µs)
00301-028
V
S
= ±15V
R
L
= 10kΩ
C
L
= 50pF
0
Figure 29. OP482 Slew Rate vs. Temperature
//m
Data Sheet OP282/OP482
Rev. I | Page 9 of 16
1000
1.0
0.1
100
10
INPUT BIAS CURRENT (pA)
TEMPERATURE (°C)
125
–25
–50 25075 100
00301-029
V
S
= ±15V
V
CM
= 0V
–75 50
Figure 30. OP482 Input Bias Current vs. Temperature
60
55
PHASE MARGIN (Degrees)
–75
TEMPERATURE (°C)
–50 –25 025 50 75 100 125
V
S
= ±15V
R
L
= 10kΩ
GBW
GAIN BANDWIDTH PRODUCT (MHz)
50
45
40
5.0
4.5
4.0
3.5
3.0
00301-030
Ø
M
Figure 31. OP482 Phase Margin and Gain Bandwidth Product vs.
Temperature
FREQUENCY (Hz)
10 100 1k 10k
80
0
20
10
40
30
50
60
70
VOLTAGE NOISE DENSITY (nV/√Hz)
00301-031
V
S
= ±15V
T
A
= 25°C
Figure 32. OP482 Voltage Noise Density vs. Frequency
COMMON-MODE VOLTAGE (V)
15–15 0510
–10 –5
INPUT BIAS CURRENT (pA)
100
1
1000
0.1
10
00301-032
V
S
= ±15V
T
A
= 25°C
Figure 33. OP482 Input Bias Current vs. Common-Mode Voltage
SUPPLY VOLTAGE (V)
±150±20±10±5
RELATIVE SUPPLY CURRENT (I
SY
)
1.10
0.90
1.15
0.85
1.00
1.05
0.95
00301-033
T
A
= 25°C
Figure 34. OP482 Relative Supply Current vs. Supply Voltage
SUPPLY VOLTAGE (V)
±150±10
±5 ±20
–5
OUTPUT VOLTAGE SWING (V)
0
15
5
10
20
–10
–20
–15
00301-034
R
L
= 10kΩ
T
A
= 25°C
Figure 35. OP482 Output Voltage Swing vs. Supply Voltage
OP282/OP482 Data Sheet
Rev. I | Page 10 of 16
IMPEDANCE (
Ω
)
600
0
300
100
200
500
400
1M1k100 100k10k
FREQUENCY (Hz)
A
VCL
= 10
00301-035
V
S
= ±15V
T
A
= 25°C
A
VCL
= 1
A
VCL
= 100
Figure 36. OP482 Closed-Loop Output Impedance vs. Frequency
RELATIVE SUPPLY CURRENT (I
SY
)
TEMPERATURE (
°
C)
1.20
0.80
0.90
0.85
1.00
0.95
1.05
1.10
1.15
–50–75 1251007550250–25
00301-036
VS = ±15V
Figure 37. OP482 Relative Supply Current vs. Temperature
LOAD RESISTANCE (Ω)
10k1k
100
ABSOLUTE OUTPUT VOLTAGE (V)
16
0
2
8
6
10
12
14
4
POSITIVE
SWING
NEGATIVE
SWING
00301-037
V
S
= ±15V
T
A
= 25°C
Figure 38. OP482 Maximum Output Voltage vs. Load Resistance
PSRR (dB)
100
20
40
0
20
80
60
1M1k100 100k10k
FREQUENCY (Hz)
+PSRR
00301-038
V
S
= ±15V
Δ
V = 100mV
T
A
= 25°C
–PSRR
Figure 39. OP482 Power Supply Rejection Ratio (PSRR) vs. Frequency
SHORT-CIRCUIT CURRENT (mA)
20
15
5
10
SINK
SOURCE
TEMPERATURE (
°
C)
75–75 025 50
–50 –25 100 125
00301-039
V
S
= ±15V
0
Figure 40. OP482 Short-Circuit Current vs. Temperature
MAXIMUM OUTPUT SWING (V)
30
0
15
5
10
25
20
100k10k
1k 1M
FREQUENCY (Hz)
00301-040
V
S
= ±15V
T
A
= 25°C
A
VCL
= 1
R
L
= 10kΩ
Figure 41. OP482 Maximum Output Swing vs. Frequency
Data Sheet OP282/OP482
Rev. I | Page 11 of 16
CMRR (dB)
100
–20
40
0
20
80
60
1M1k
100 100k10k
FREQUENCY (Hz)
00301-041
V
S
= ±15V
T
A
= 25°C
V
CM
= 100mV
Figure 42. OP482 Common-Mode Rejection Ratio (CMRR) vs. Frequency
UNITS
0
600
700
300
100
200
400
500
2000
–1600–2000 160012008004000
–400–800–1200
V
OS
(µV)
00301-045
V
S
= ±15V
T
A
= 25°C
300 × OP482
(1200 OP AMPS)
Figure 43. OP482 VOS Distribution, PDIP Package
UNITS
320
0
80
40
160
120
200
240
280
0
00301-043
32282412 20168
4
TCV
OS
(µV/°C)
Figure 44. OP482 TCVOS Distribution, PDIP Package
m w—w
OP282/OP482 Data Sheet
Rev. I | Page 12 of 16
APPLICATIONS INFORMATION
The OP282 and OP482 are dual and quad JFET op amps that
are optimized for high speed at low power. This combination
makes these amplifiers excellent choices for battery-powered or
low power applications that require above average performance.
Applications benefiting from this performance combination
include telecommunications, geophysical exploration, portable
medical equipment, and navigational instrumentation.
HIGH-SIDE SIGNAL CONDITIONING
Many applications require the sensing of signals near the positive
rail. OP282 and OP482 were tested and are guaranteed over a
common-mode range (−11 V ≤ VCM ≤ +15 V) that includes the
positive supply.
One application where such sensing is commonly used is in the
sensing of power supply currents. Therefore, the OP282/OP482
can be used in current sensing applications, such as the partial
circuit shown in Figure 45. In this circuit, the voltage drop across
a low value resistor, such as the 0.1 Ω shown here, is amplified
and compared to 7.5 V. The output can then be used for current
limiting.
15V
100k
Ω
500k
Ω
0.1
Ω
500k
Ω
100k
Ω
R
L
1/2
OP282
00301-046
Figure 45. High-Side Signal Conditioning
PHASE INVERSION
Most JFET input amplifiers invert the phase of the input signal
if either input exceeds the input common-mode range. For the
OP282/OP482, a negative signal in excess of 11 V causes phase
inversion. This is caused by saturation of the input stage, leading
to the forward-biasing of a gate-drain diode. Phase reversal in
the OP282/OP482 can be prevented by using Schottky diodes to
clamp the input terminals to each other and to the supplies. In
the simple buffer circuit shown in Figure 46, D1 protects the op
amp against phase reversal. R1, D2, and D3 limit the input
current when the input exceeds the supply rail. The resistor
should be selected to limit the amount of input current below
the absolute maximum rating.
00301-042
D1
IN5711 V+
OP282/
OP482
V+
V
OUT
V
IN
V–
V–
D2
IN5711
R1
10kΩ
D3
IN5711
Figure 46. Phase Reversal Solution Circuit
00301-044
TIME (200µs/DIV)
VOLTAGE (5V/DIV)
2
V
S
= ±15V
V
IN
V
OUT
Figure 47. No Phase Reversal
ACTIVE FILTERS
The wide bandwidth and high slew rates of the OP282/OP482
make either one an excellent choice for many filter applications.
There are many active filter configurations, but the four most
popular configurations are Butterworth, elliptic, Bessel, and
Chebyshev. Each type has a response that is optimized for a
given characteristic, as shown in Table 4.
Table 4. Active Filter Configurations
Type Selectivity Overshoot Phase Amplitude (Pass Band) Amplitude (Stop Band)
Butterworth
Moderate
Good
Maximum flat
Chebyshev Good Moderate Nonlinear Equal ripple
Elliptic Best Poor Equal ripple Equal ripple
Bessel (Thompson) Poor Best Linear
Data Sheet OP282/OP482
Rev. I | Page 13 of 16
PROGRAMMABLE STATE VARIABLE FILTER
The circuit shown in Figure 48 can be used to accurately
program the Q, the cutoff frequency (fC), and the gain of a two-
pole state variable filter. OP482 devices have been used in this
design because of their high bandwidths, low power, and low
noise. This circuit takes only three packages to build because of
the quad configuration of the op amps and DACs.
The DACs shown are used in the voltage mode; therefore, many
values are dependent on the accuracy of the DAC only and not
on the absolute values of the DAC’s resistive ladders. This
makes this circuit unusually accurate for a programmable filter.
Adjusting DAC 1 changes the signal amplitude across R1; therefore,
the DAC attenuation times R1 determines the amount of signal
current that charges the integrating capacitor, C1.
This cutoff frequency can now be expressed as
=256
2π
1D1
R1C1
fC
where D1 is the digital code for the DAC.
The gain of this circuit is set by adjusting D3. The gain equation is
=256
D3
R5
R4
Gain
DAC 2 is used to set the Q of the circuit. Adjusting this DAC
controls the amount of feedback from the band-pass node to
the input summing node. Note that the digital value of the
DAC is in the numerator; therefore, zero code is not a valid
operating point.
=D2R3
R2
Q256
R5
2k
Ω
1/4
OP482
VIN
1/4
DAC8408
HIGH PASS
C1
1000pF
R4
2k
Ω
R6
2k
Ω
R7
2k
Ω
1/4
OP482 R1
2k
Ω
1/4
OP482
1/4
DAC8408 1/4
OP482 R1
2k
Ω
1/4
OP482
1/4
DAC8408 1/4
OP482
C1
1000pF
LOW
PASS
1/4
OP482
1/4
OP482
1/4
DAC8408
BAND PASS
R2
2k
Ω
R3
2k
Ω
00301-047
Figure 48. Programmable State Variable Filter
OP282/OP482 Data Sheet
Rev. I | Page 14 of 16
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-AA
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
10-07-2009-B
Figure 49. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8 5
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 50. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
S-Suffix (R-8)
Dimensions shown in millimeters and (inches)
,‘HHHHHHH' ‘ o 7 j i HHHHHHHi Ah ‘Ffig 7 Vix ’1 r .u‘
Data Sheet OP282/OP482
Rev. I | Page 15 of 16
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
070606-A
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.070 (1.78)
0.050 (1.27)
0.045 (1.14)
14
17
8
0.100 (2.54)
BSC
0.775 (19.69)
0.750 (19.05)
0.735 (18.67)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.015 (0.38)
GAUGE
PLANE
0.210 (5.33)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 (0.13)
MIN
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
Figure 51. 14-Lead Plastic Dual In-Line Package [PDIP]
P-Suffix (N-14)
Dimension shown in inches and (millimeters)
CONTROLLING DIMENSIONSARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AB
060606-A
14 8
7
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
8.75 (0.3445)
8.55 (0.3366)
1.27 (0.0500)
BSC
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
8°
0°
45°
Figure 52. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
S-Suffix (R-14)
Dimensions shown in millimeters and (inches)
SEGIéOEg www.3nalog.cnm
OP282/OP482 Data Sheet
Rev. I | Page 16 of 16
1.165
1.128
1.090
2.160
2.123
2.085
A
B
C
D
E
F
1
2
3
BOTTOM VIEW
(BALL SIDE UP)
1.60
REF
0.694
REF
0.40
BSC
0.20
BSC
0.347
BSC 0.347
BSC
G
H
J
0.287
0.267
0.247
0.415
0.400
0.385
0.230
0.200
0.170
0.645
0.600
0.555
TOP VIEW
(BALL SIDE DOWN)
END VIEW
BALLA1
IDENTIFIER
09-11-2012-B
SEATING
PLANE
COPLANARITY
0.05
Figure 53. 14-Ball Wafer Level Chip Scale Package [WLCSP]
CB-14-2
Controlling dimensions are millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Branding
OP282ARMZ −40°C to +85°C 8-Lead MSOP RM-8 A0B
OP282ARMZ-REEL −40°C to +85°C 8-Lead MSOP RM-8 A0B
OP282GS
−40°C to +85°C
8-Lead SOIC_N
S-Suffix (R-8)
OP282GS-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
OP282GS-REEL7 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
OP282GSZ −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
OP282GSZ-REEL −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
OP282GSZ-REEL7 −40°C to +85°C 8-Lead SOIC_N S-Suffix (R-8)
OP482ACBZ-RL −40°C to +85°C 14-Ball WLCSP CB-14-2 A2J
OP482ACBZ-R7 −40°C to +85°C 14-Ball WLCSP CB-14-2 A2J
OP482GPZ −40°C to +85°C 14-Lead PDIP P-Suffix (N-14)
OP482GS −40°C to +85°C 14-Lead SOIC_N S-Suffix (R-14)
OP482GS-REEL −40°C to +85°C 14-Lead SOIC_N S-Suffix (R-14)
OP482GS-REEL7 −40°C to +85°C 14-Lead SOIC_N S-Suffix (R-14)
OP482GSZ −40°C to +85°C 14-Lead SOIC_N S-Suffix (R-14)
OP482GSZ-REEL −40°C to +85°C 14-Lead SOIC_N S-Suffix (R-14)
OP482GSZ-REEL7
−40°C to +85°C
14-Lead SOIC_N
S-Suffix (R-14)
1 Z = RoHS Compliant Part.
©1991–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00301-0-9/13(I)