Analog Devices Inc. 的 AD8195 規格書

ANALOG DEVICES AD8195 eddyansiv
HDMI/DVI Buffer with Equalization
Data Sheet
AD8195
Rev. B
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rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008–2012 Analog Devices, Inc. All rights reserved.
FEATURES
1 input, 1 output HDMI/DVI link
Enables HDMI 1.3a-compliant front panel input
4 TMDS channels per link
Supports 250 Mbps to 2.25 Gbps data rates
Supports 25 MHz to 225 MHz pixel clocks
Equalized inputs for operation with long HDMI cables
(20 m at 2.25 Gbps)
Preemphasized outputs
Fully buffered unidirectional inputs/outputs
50 Ω on-chip terminations
Low added jitter
Transmitter disable feature
Reduces power dissipation
Disables input termination
3 auxiliary buffered channels per link
Bidirectional buffered DDC lines (SDA and SCL)
Bidirectional buffered CEC line with integrated pull-up
resistors (27 kΩ)
Independently powered from 5 V of HDMI input
connector
Logic level translation (3.3 V, 5 V)
Input/output capacitance isolation
Standards compatible: HDMI, DVI, HDCP, DDC, CEC
40-lead LFCSP_VQ package (6 mm × 6 mm)
APPLICATIONS
Front panel buffer for advanced television (HDTV) sets
GENERAL DESCRIPTION
The AD8195 is an HDMI/DVI buffer featuring equalized TMDS
inputs and preemphasized TMDS outputs, ideal for systems with
long cable runs. The AD8195 includes bidirectional buffering
for the DDC bus and bidirectional buffering with integrated
pull-up resistors for the CEC bus. The DDC and CEC buffers
are powered independently of the TMDS buffers so that DDC/
CEC functionality can be maintained when the system is powered
off. The AD8195 meets all the requirements for sink tests as
defined in Section 8 of the HDMI Compliance Test 1.3c.
The AD8195 is specified to operate over the −40°C to +85°C
temperature range.
FUNCTIONAL BLOCK DIAGRAM
IP[3:0]
IN[3:0]
VTTI
OP[3:0]
AMUXVCC
AVEE
VTTO
AVCC
ON[3:0]
VREF_IN VREF_OUT
+
–
+
–EQ BUFFER PE
CONTROL
LOGIC
4
4
4
22
4
HIGH SPEED BUFFERED
LOW SPEED BUFFERED
PE_EN
TX_EN
COMP
PARALLEL
BIDIRECTIONAL
AD8195
SCL_IN
SDA_IN SCL_OUT
SDA_OUT
CEC_IN CEC_OUT
07049-001
Figure 1.
TYPICAL APPLICATION
07049-002
MEDIA CENTER
SET-TOP BOX
DVD PLAYER
HDTV SET
4:1 HDMI
SWITCH
AD8195
HDMI
RECEIVER
FRONT PANEL
CONNECTOR
BACK PANEL
CONNECTORS
GAME
CONSOLE
Figure 2. Typical AD8195 Application for HDTV Sets
PRODUCT HIGHLIGHTS
1. Enables a fully HDMI 1.3a-compliant front panel input.
2. Supports data rates of up to 2.25 Gbps, enabling 1080p deep
color (12-bit color) HDMI formats and greater than UXGA
(1600 × 1200) DVI resolutions.
3. Input cable equalizer enables use of long cables; more than
20 meters (24 AWG) at data rates of up to 2.25 Gbps.
4. Auxiliary buffer isolates and buffers the DDC bus and CEC
line for a single chip, fully HDMI 1.3a-compliant solution.
5. Auxiliary buffer is powered independently from the TMDS
link so that DDC/CEC functionality can be maintained
when the system is powered off.
AD8195 Data Sheet
Rev. B | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Typical Application ........................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
TMDS Performance Specifications ............................................ 3
Auxiliary Channel Performance Specifications........................ 4
Power Supply and Control Logic Specifications ...................... 4
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
Maximum Power Dissipation ..................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ..............................6
Typical Performance Characteristics ..............................................8
Theory of Operation ...................................................................... 13
Input Channels ........................................................................... 13
Output Channels ........................................................................ 13
Preemphasis ................................................................................ 14
Auxiliary Lines ............................................................................ 14
Applications Information .............................................................. 15
Front Panel Buffer for Advanced TV ....................................... 15
Cable Lengths and Equalization ............................................... 16
TMDS Output Rise/Fall Times ................................................. 16
PCB Layout Guidelines .............................................................. 16
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
8/12—Rev. A to Rev. B
Changed Data Rate = 3 Gbps to
Data Rate = 2.25 Gbps .................................................. Throughout
Changes to Features Section, General Description Section, and
Product Highlights Section ............................................................. 1
Changes to Table 1 ............................................................................ 3
Changes to specifications statements in Typical Performance
Characteristics Section ..................................................................... 8
Changes to Figure 19 ...................................................................... 11
Changes to Theory of Operation Section and to
Input Channels Section .................................................................. 13
Changes to Output Channels Section .......................................... 13
Changes to Preemphasis Section .................................................. 14
Changes to Cable Lengths and Equalization Section and
PCB Layout Guidelines Section .................................................... 16
Added Unused DDC/CEC Buffers Section ................................. 18
8/11—Rev. 0 to Re v. A
Changed Data Rate = 2.25 Gbps to
Data Rate = 2.25 Gbps .................................................. Throughout
Changes to Features Section, General Description Section, and
Product Highlights Section .............................................................. 1
Changes to Table 1 ............................................................................. 3
Changes to Table 3 ............................................................................. 4
Changes to Figure 5 Caption and Figure 7 Caption ..................... 8
Added Figure 6 and Figure 8; Renumbered Sequentially ............ 8
Moved Figure 9 and Figure 11 ......................................................... 9
Changes to Figure 9 Caption and Figure 11 Caption ................... 9
Added Figure 10 and Figure 12 ....................................................... 9
Moved Figure 14 and Figure 16 .................................................... 10
Changes to Figure 14 Caption and Figure 16 Caption .............. 10
Added Figure 15 and Figure 17 .................................................... 10
Changes to Figure 18, Figure 19, and Figure 21 ......................... 11
Changes to Input Channels Section ............................................. 13
Changes to Output Channels Section .......................................... 13
Changes to Preemphasis Section .................................................. 14
Changes to Cable Lengths and Equalization Section, TMDS
Output Rise/Fall Times Section, and PCB Layout Guidelines
Section .............................................................................................. 16
Changes to Auxiliary Control Signals Section ........................... 18
8/08—Revision 0: Initial Version
Data Sheet AD8195
Rev. B | Page 3 of 20
SPECIFICATIONS
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AMUXVCC = 5 V, VREF_IN = 5 V, VREF_OUT = 5 V, AVEE = 0 V, differential input
swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.
TMDS PERFORMANCE SPECIFICATIONS
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
TMDS DYNAMIC PERFORMANCE
Maximum Data Rate (DR) per Channel NRZ 2.25 Gbps
Bit Error Rate (BER)
10−9
Added Data Jitter DR ≤ 2.25 Gbps, PRBS 27 − 1 31 ps p-p
Added Clock Jitter 1 ps rms
Differential Intrapair Skew At output 1 ps
Differential Interpair Skew At output 30 ps
TMDS EQUALIZATION PERFORMANCE
Receiver1 Boost frequency = 1.5 GHz 12 dB
Transmitter2 Boost frequency = 1.5 GHz 6 dB
TMDS INPUT CHARACTERISTICS
Input Voltage Swing Differential 150 1200 mV
Input Common-Mode Voltage (VICM) AVCC − 800 AVCC mV
TMDS OUTPUT CHARACTERISTICS
High Voltage Level Single-ended, high speed channel AVCC − 200 AVCC + 10 mV
Low Voltage Level Single-ended, high speed channel AVCC − 600 AVCC − 400 mV
Rise/Fall Time (20% to 80%)3
50
90
150
ps
TMDS TERMINATION
Input Termination Resistance Single-ended 50 Ω
Output Termination Resistance
50
Ω
1 Output meets transmitter eye diagram as defined in the DVI Standard Revision 1.0 and HDMI Standard.
2 Cable output meets receiver eye diagram mask as defined in the DVI Standard Revision 1.0 and HDMI Standard.
3 Output rise/fall time measurement excludes external components, such as HDMI connector or external ESD protection diodes. See the Applications Information
section for more information.
AD8195 Data Sheet
Rev. B | Page 4 of 20
AUXILIARY CHANNEL PERFORMANCE SPECIFICATIONS
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
DDC CHANNELS
Input Capacitance, CAUX DC bias = 2.5 V, ac voltage = 3.5 V p-p, f = 100 kHz 10 15 pF
Input Low Voltage, VIL 0.5 V
Input High Voltage, VIH 0.7 × VREF1 VREF1 V
Output Low Voltage, VOL IOL = 5 mA 0.25 0.4 V
Output High Voltage, VOH VREF1 V
Rise Time 10% to 90%, no load 140 ns
Fall Time 90% to 10%, CLOAD = 400 pF 100 200 ns
Leakage Input voltage = 5.0 V 10 μA
CEC CHANNEL
Input Capacitance, CAUX DC bias = 1.65 V, ac voltage = 2.5 V p-p, f = 100 kHz,
2 kΩ pull-up resistor from CEC_OUT to 3.3 V
5 25 pF
Input Low Voltage, VIL 0.8 V
Input High Voltage, VIH 2.0 V
Output Low Voltage, V
OL
0.25
0.6
V
Output High Voltage, VOH 2.5 3.3 V
Rise Time 10% to 90%, CLOAD = 1500 pF, RPULL-UP = 27 kΩ;
or CLOAD = 7200 pF, RPULL-UP = 3 kΩ
50 100 µs
Fall Time 90% to 10%, CLOAD = 1500pF, RPULL-UP = 27 kΩ;
or CLOAD = 7200 pF, RPULL-UP = 3 kΩ
5 10 µs
Pull-Up Resistance 27 kΩ
Leakage Off leakage test conditions2 1.8 µA
1 VREF is the voltage at the reference pin (VREF_IN for SCL_IN and SDA_IN, or VREF_OUT for SCL_OUT and SDA_OUT); nominally 5.0 V.
2 Off leakage test conditions are described in the HDMI Compliance Test Specification 1.3b Section 8, Test ID 8-14: “Remove power (mains) from DUT. Connect CEC line
to 3.63 V via 27 kΩ ± 5% resistor with ammeter in series. Measure CEC line leakage.”
POWER SUPPLY AND CONTROL LOGIC SPECIFICATIONS
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
AVCC Operating range (3.3 V ± 10%) 3 3.3 3.6 V
AMUXVCC Operating range (5 V ± 10%) 4.5 5 5.5 V
VREF_IN, VREF_OUT 3 5.5 V
QUIESCENT CURRENT
AVCC Output disabled 20 40 mA
Output enabled, no preemphasis (0 dB) 32 50 mA
Output enabled, maximum preemphasis (6 dB) 66 80 mA
VTTI
Input termination on
40
54
mA
VTTO Output termination on, no preemphasis 40 50 mA
Output termination on, maximum preemphasis 80 100 mA
VREF_IN 120 200 μA
VREF_OUT 120 200 μA
AMUXVCC 10 20 mA
POWER DISSIPATION
Output disabled 116 254 mW
Output enabled, no preemphasis (0 dB) 180 663 mW
Output enabled, maximum preemphasis (6 dB) 736 1047 mW
PARALLEL CONTROL INTERFACE TX_EN, PE_EN
Input High Voltage, V
IH
2.4
V
Input Low Voltage, VIL 0.8 V
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Data Sheet AD8195
Rev. B | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
AVCC to AVEE 3.7 V
VTTI
AVCC + 0.6 V
VTTO AVCC + 0.6 V
AMUXVCC 5.5 V
VREF_IN 5.5 V
VREF_OUT 5.5 V
Internal Power Dissipation 1.81 W
High Speed Input Voltage
AVCC − 1.4 V < VIN <
AVCC + 0.6 V
High Speed Differential Input Voltage 2.0 V
Parallel Control Input Voltage AVEE − 0.3 V < VIN <
AVCC + 0.6 V
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Junction Temperature 150°C
ESD, Human Body Model
Input Pins Only ±5 kV
All Other Pins ±3 kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Table 5.
Package θJA θJC Unit
40-Lead LFCSP_VQ 36 5.0 °C/W
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD8195
is limited by the associated rise in junction temperature. The
maximum safe junction temperature for plastic encapsulated
devices is determined by the glass transition temperature of the
plastic, approximately 150°C. Temporarily exceeding this limit
may cause a shift in parametric performance due to a change in
the stresses exerted on the die by the package. Exceeding a junction
temperature of 175°C for an extended period can result in device
failure. To ensure proper operation, it is necessary to observe
the maximum power derating as determined by the thermal
resistance coefficients.
ESD CAUTION
AD8195 Data Sheet
Rev. B | Page 6 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. THE AD8195 LFCSP HAS AN EXPOSED PAD ON THE UNDERSIDE OF
THE PACKAGE THAT AIDS IN HEAT DISSIPATION. THE PAD MUST BE
ELECTRICALLY CONNECTED TO THE AVEE SUPPLY PLANE IN ORDER
TO MEET THERMAL SPECIFICATIONS.
AD8195
TOP VIEW
(Not to Scale)
1IN0
2IP0
3IN1
4IP1
5VTTI
6IN2
7IP2
10AVCC
30 AVCC
29 PE_EN
28 TX_EN
27 AVEE
26 AVCC
25 AVCC
24 AVEE
21 COMP
40 SCL_IN
39 SDA_IN
38 CEC_IN
37 AVEE
36 VREF_IN
35 SCL_OUT
34 SDA_OUT
31 CEC_OUT
11ON0
12OP0
13VTTO
14ON1
15OP1
16AVCC
17ON2
20OP3
9IP3
8IN3
22 AVCC
23 AVCC
19ON3
18OP2
32 AMUXVCC
33 VREF_OUT
PIN 1
INDICATOR
07049-003
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type 1 Description
1 IN0 HS I High Speed Input Complement.
2 IP0 HS I High Speed Input.
3 IN1 HS I High Speed Input Complement.
4 IP1 HS I High Speed Input.
5 VTTI Power Input Termination Supply. Nominally connected to AVCC.
6 IN2 HS I High Speed Input Complement.
7 IP2 HS I High Speed Input.
8 IN3 HS I High Speed Input Complement.
9 IP3 HS I High Speed Input.
10, 16, 22, 23, 25, 26, 30 AVCC Power Positive Analog Supply. 3.3 V nominal.
11 ON0 HS O High Speed Output Complement.
12 OP0 HS O High Speed Output.
13 VTTO Power Output Termination Supply. Nominally connected to AVCC.
14 ON1 HS O High Speed Output Complement.
15 OP1 HS O High Speed Output.
17 ON2 HS O High Speed Output Complement.
18 OP2 HS O High Speed Output.
19 ON3 HS O High Speed Output Complement.
20 OP3 HS O High Speed Output.
21 COMP Control Power-On Compensation Pin. Bypass to ground through a 10 µF capacitor.
24, 27, 37, Exposed Pad AVEE Power Negative Analog Supply. 0 V nominal.
28 TX_EN Control High Speed Output Enable Parallel Interface.
29 PE_EN Control High Speed Preemphasis Enable Parallel Interface.
Data Sheet AD8195
Rev. B | Page 7 of 20
Pin No. Mnemonic Type 1 Description
31 CEC_OUT LS I/O CEC Output Side.
32 AMUXVCC Power Positive Auxiliary Buffer Supply. 5 V nominal.
33 VREF_OUT Reference DDC Output Side Pull-Up Reference Voltage.
34
SDA_OUT
LS I/O
DDC Output Side Data Line Input/Output.
35
SCL_OUT
LS I/O
DDC Output Side Clock Line Input/Output.
36 VREF_IN Reference DDC Input Side Pull-Up Reference Voltage.
38
CEC_IN
LS I/O
CEC Input Side.
39
SDA_IN
LS I/O
DDC Input Side Data Line.
40 SCL_IN LS I/O DDC Input Side Clock Line
1 HS = high speed, LS = low speed, I = input, and O = output.
AD8195 Data Sheet
Rev. B | Page 8 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1,
TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.
REFERENCE EYE DIAGRAM AT TP1
DIGITAL
PATTERN
GENERATOR
AD8195
EVALUATION
BOARD
SERIAL DATA
ANALYZER
SMA COAX CABLE
HDMI CABLE
TP1 TP2 TP3
07049-104
Figure 4. Test Circuit Diagram for Rx Eye Diagrams
0.125UI/DIV AT 2.25Gbps
250mV/DIV
07049-105
Figure 5. Rx Eye Diagram at TP2
(Cable = 2 Meters, 24 AWG, Data Rate = 2.25 Gbps)
0.167UI/DIV AT 3.0Gbps
250mV/DIV
07049-206
Figure 6. Rx Eye Diagram at TP2
(Cable = 2 Meters, 24 AWG, Data Rate = 3 Gbps)
0.125UI/DIV AT 2.25Gbps
250mV/DIV
07049-107
Figure 7. Rx Eye Diagram at TP3, EQ = 12 dB
(Cable = 2 Meters, 24 AWG, Data Rate = 2.25 Gbps)
0.167UI/DIV AT 3.0Gbps
250mV/DIV
07049-208
Figure 8. Rx Eye Diagram at TP3, EQ = 12 dB
(Cable = 2 Meters, 24 AWG, Data Rate = 3 Gbps)
Data Sheet AD8195
Rev. B | Page 9 of 20
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1,
TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.
0.125UI/DIV AT 2.25Gbps
250mV/DIV
07049-106
Figure 9 Rx Eye Diagram at TP2
(Cable = 20 Meters, 24 AWG, Data Rate = 2.25 Gbps)
0.167UI/DIV AT 3.0Gbps
250mV/DIV
07049-210
Figure 10 Rx Eye Diagram at TP2
(Cable = 15 Meters, 24 AWG, Data Rate = 3 Gbps)
0.125UI/DIV AT 2.25Gbps
250mV/DIV
07049-108
Figure 11. Rx Eye Diagram at TP3, EQ = 12 dB
(Cable = 20 Meters, 24 AWG, Data Rate = 2.25 Gbps)
0.167UI/DIV AT 3.0Gbps
250mV/DIV
07049-212
Figure 12. Rx Eye Diagram at TP3, EQ = 12 dB
(Cable = 15 Meters, 24 AWG, Data Rate = 3 Gbps)
AD8195 Data Sheet
Rev. B | Page 10 of 20
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1,
TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.
REFERENCE EYE DIAGRAM AT TP1
DIGITAL
PATTERN
GENERATOR
SMA COAX CABLE
HDMI CABLE
TP1 TP2 TP3
AD8195
EVALUATION
BOARD
SERIAL DATA
ANALYZER
07049-109
Figure 13. Test Circuit Diagram for Tx Eye Diagrams
0.125UI/DIV AT 2.25Gbps
250mV/DIV
07049-110
Figure 14. Tx Eye Diagram at TP2, PE = 0 dB, Data Rate = 2.25 Gbps
0.167UI/DIV AT 3.0Gbps
250mV/DIV
07049-215
Figure 15. Tx Eye Diagram at TP2, PE = 0 dB, Data Rate = 3.0 Gbps
0.125UI/DIV AT 2.25Gbps
250mV/DIV
07049-112
Figure 16. Tx Eye Diagram at TP3, PE = 0 dB, Data Rate = 2.25 Gbps
(Cable = 6 Meters, 24 AWG)
0.167UI/DIV AT 3.0Gbps
250mV/DIV
07049-217
Figure 17. Tx Eye Diagram at TP3, PE = 0 dB, Data Rate = 3.0 Gbps
(Cable = 6 Meters, 24 AWG)
Data Sheet AD8195
Rev. B | Page 11 of 20
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1,
data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.
25
0.6
0.5
0.4
0.3
0.2
0.1
00 5 10 15 20
JITTER (UI)
INPUT CABLE LENGTH (m)
ALL CABLES = 24 AWG
480p, 8-BIT
720p/1080i,
8-BIT
1080p, 8-
BIT
1.65Gbps
3.0Gbps 1080p, 12-
BIT
07049-114
Figure 18. Jitter vs. Input Cable Length (See Figure 4 for Test Setup)
2.4 2.6 2.8 3.0 3.2 3.42.22.01.81.61.41.21.00.80.60.40.2
50
40
30
20
10
00
JITTER (ps)
DATA RATE (Gbps)
RJ rms
DJ p-p
07049-115
Figure 19. Jitter vs. Data Rate
3.63.53.43.33.23.13.0
50
40
30
20
10
0
JITTER (ps)
SUPPLY VOLTAGE (V)
RJ rms
DJ p-p
07049-116
Figure 20. Jitter vs. Supply Voltage
161412108642
0.6
0.5
0.4
0.3
0.2
0.1
00
JITTER (UI)
OUTPUT CABLE LENGTH (m)
3.0Gbps
1080p, 12-BIT
1080p, 8-BIT
1.65Gbps 720p/1080i,
8-BIT
480p, 8-BIT
ALL CABLES = 24 AWG
PE = 6dB
07049-117
Figure 21. Jitter vs. Output Cable Length (See Figure 13 for Test Setup)
2.4 2.6 2.8 3.0 3.2 3.42.22.01.81.61.41.21.00.80.60.40.2
1.2
1.0
0.8
0.6
0.4
0.2
00
EYE HEIGHT (V)
DATA RATE (Gbps)
07049-118
Figure 22. Eye Height vs. Data Rate
3.63.53.43.33.23.13.0
EYE HEIGHT (V)
SUPPLY VOLTAGE (V)
1.2
1.0
0.8
0.6
0.4
0.2
0
07049-119
Figure 23. Eye Height vs. Supply Voltage
.9 824.55% 5%. SENKEE
AD8195 Data Sheet
Rev. B | Page 12 of 20
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1,
data rate = 3 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.
2.01.51.00.5
80
70
60
50
40
30
20
10
00
JITTER (ps)
DIFFERENTIAL INPUT VOLTAGE SWING (V)
DJ p-p
RJ rms
07049-120
Figure 24. Jitter vs. Differential Input Voltage Swing
85603510–15
50
40
30
20
10
0
–40
JITTER (ps)
TEMPERATURE (°C)
DJ p-p
RJ rms
07049-121
Figure 25. Jitter vs. Temperature
07049-122
120
100
80
60
40
20
0
RISE/FALL TIME 20% TO 80% (ps)
–40 –20 020 40 60 80
TEMPERATURE (°C)
RISE
FALL
Figure 26. Rise and Fall Time vs. Temperature
3.73.3 3.53.12.92.7
50
45
35
40
30
25
20
15
10
5
0
2.5
JITTER (ps)
INPUT COMMON-MODE VOLTAGE (V)
DJ p-p
RJ rms
07049-123
Figure 27. Jitter vs. Input Common-Mode Voltage
100806040200–20
120
115
110
105
100
95
90
85
80
–40
TEMPERATURE (°C)
DIFFERENTIAL INPUT RESISTANCE (Ω)
07049-124
Figure 28. Differential Input Resistance vs. Temperature
10987654321
0.5
0.4
0.3
0.2
0.1
00
LOAD CURRENT (mA)
DDC/CEC OUTPUT LOGIC LOW VOLTAGE; V
OL
(V)
07049-125
Figure 29.DDC/CEC Output Logic Low Voltage (VOL) vs. Load Current
1r 1E
Data Sheet AD8195
Rev. B | Page 13 of 20
THEORY OF OPERATION
The primary function of the AD8195 is to buffer a single (HDMI
or DVI) link. The HDMI or DVI link consists of four differential,
high speed channels and three auxiliary single-ended, low speed
control signals. The high speed channels include a data-word clock
and three transition minimized differential signaling (TMDS)
data channels running at 10× the data-word clock frequency for
data rates up to 2.25 Gbps. The three low speed control signals
consist of the display data channel (DDC) bus (SDA and SCL)
and the consumer electronics control (CEC) line.
All four high speed TMDS channels are identical; that is, the
pixel clock can be run on any of the four TMDS channels.
Receive channel compensation is provided for the high speed
channels to support long input cables. The AD8195 also includes
selectable preemphasis for driving high loss output cables.
In the intended application, the AD8195 is placed between a
source and a sink, with long cable runs on the input and output.
INPUT CHANNELS
Each high speed input differential pair terminates to the 3.3 V
VTTI power supply through a pair of single-ended 50 Ω on-chip
resistors, as shown in Figure 30. When the transmitter of the
AD8195 is disabled by setting the TX_EN control pin, the input
termination resistors are also disabled to provide a high impedance
node at the TMDS inputs.
The input equalizer provides 12 dB of high frequency boost.
No specific cable length is suggested for this equalization level
because cable performance varies widely between manufacturers;
however, in general, the AD8195 does not degrade or over-
equalize input signals, even for short input cables. The AD8195
can equalize more than 20 meters of 24 AWG cable at 2.25 Gbps,
over reference cables that exhibit an insertion loss of −15 dB.
CABLE
EQ
50Ω50Ω
IPx
TX_EN
INx
AVEE
VTTI
07049-004
Figure 30. High Speed Input Simplified Schematic
OUTPUT CHANNELS
Each high speed output differential pair is terminated to the
3.3 V VTTO power supply through two single-ended 50 Ω
on-chip resistors (see Figure 31).
VTTO
50Ω
50Ω
OPx ONx
AVEE
I
OUT
07049-005
Figure 31. High Speed Output Simplified Schematic
The output termination resistors of the AD8195 back terminate
the output TMDS transmission lines. These back terminations,
as `recommended in the HDMI specification, act to absorb
reflections from impedance discontinuities on the output traces,
improving the signal integrity of the output traces and adding
flexibility to how the output traces can be routed. For example,
interlayer vias can be used to route the AD8195 TMDS outputs
on multiple layers of the PCB without severely degrading the
quality of the output signal. Note that the arrangement of the
ESD structures cause current to flow into the TMDS outputs
when in the off state. The AD8195 outputs will not meet the
requirements of Test ID 7-3 (TMDS-VOFF) of the HDMI
Compliance Test Specification 1.3c. These outputs should only
interface to an internal system node and should not be interfaced
to an HDMI output connector.
The AD8195 has an external control pin, TX_EN, that disables
the transmitter, reducing power when the transmitter is not in
use. Additionally, when the transmitter is disabled, the input
termination resistors are also disabled to present a high impedance
state at the input and indicate to any connected HDMI sources
that the link through the AD8195 is inactive.
Table 7. Transmitter Enable Setting
TX_EN Function
0 Tx/input termination disabled
1 Tx/input termination enabled
The AD8195 also includes two levels of programmable output
preemphasis, 0 dB and 6 dB. The output preemphasis level can
be manually configured by setting the PE_EN pin. No specific
cable length is suggested for use with either preemphasis setting,
as cable performance varies widely among manufacturers.
Table 8. Preemphasis Setting
PE_EN PE Boost
0 0 dB
1 6 dB
AD8195 Data Sheet
Rev. B | Page 14 of 20
PREEMPHASIS
The preemphasized TMDS outputs precompensate the trans-
mitted signal to account for losses in systems with long cable
runs. These long cable runs selectively attenuate the high
frequency energy of the signal, leading to degraded transition
times and eye closure. Similar to a receive equalizer, the goal of
the preemphasis filter is to boost the high frequency energy in
the signal. However, unlike the receive equalizer, the preemphasis
filter is applied before the channel, thus predistorting the
transmitted signal to account for the loss of the channel. The
series connection of the preemphasis filter and the channel
results in a flatter frequency response than that of the channel,
thus leading to improved high frequency energy, improved
transition times, and improved eye opening on the far end of
the channel. Using a preemphasis filter to compensate for
channel losses allows for longer cable runs with or without a
receiver equalizer on the far end of the channel.
When there is no receive equalizer on the far end of the channel,
the preemphasis filter should allow longer cable runs than
would be acceptable with no preemphasis. When there is both a
preemphasis filter on the near end and a receive equalizer on
the far end of the channel, the allowable cable run should be
longer than either compensation could achieve alone. The pulse
response of a preemphasized waveform is shown in Figure 32.
The output voltage levels and symbol descriptions are listed in
Table 9 and Table 10, respectively. The preemphasis circuit is
designed to work up to 2.25 Gbps and does not perform
suitably at higher data rates.
V
OCM
V
H
V
L
V
OSE-BOOST
V
TTO
V
OSE-DC
<T
BIT
V
OCM
V
TTO
V
H
V
L
V
OSE-DC
PREEMPHASIS OFF
PREEMPHASIS ON
07049-006
Figure 32. Preemphasis Pulse Response
AUXILIARY LINES
The auxiliary (low speed) lines provide buffering for the DDC
and CEC signals. The auxiliary lines are powered independently
from the TMDS link; therefore, their functionality can be
maintained even when the system is powered off. In an application,
these lines can be powered by connecting AMUXVCC to the
5 V supply provided from the video source through the input
HDMI connector.
DDC Buffers
The DDC buffers are 5 V tolerant bidirectional lines that can
carry extended display identification data (EDID), HDCP
encryption, and other information, depending on the specific
application. The DDC buffers are bidirectional and fully support
arbitration, clock synchronization, clock stretching, slave acknowl-
edgement, and other relevant features of a standard mode I2C bus.
The DDC buffers also have separate voltage references for the
input side and the output side, allowing the sink to use internal
bus voltages (3.3 V), alleviating the need for 5 V tolerant I/Os
for system ASICs. The logic level for the DDC_IN bus is set by
the voltage on VREF_IN, and the logic level for the DDC_OUT
bus is set by the voltage on VREF_OUT. For example, if the
DDC_IN bus is using 5 V I2C, the VREF_IN power supply pin
should be connected to a 5 V power supply. If the DDC_OUT
bus is using 3.3 V I2C, the VREF_OUT power supply pin should
be connected to a 3.3 V power supply.
CEC Buffer
The CEC buffer is a 3.3 V tolerant bidirectional buffer with
integrated pull-up resistors. This buffer enables full compliance
with all CEC specifications, including but not limited to input
capacitance, logic levels, transition times, and leakage (both with
the system power on and off). This allows the CEC functionality
to be implemented in a standard microcontroller that may not
have CEC compliant I/Os. The CEC buffer is powered from the
AMUXVCC supply.
Table 9. Output Voltage Levels
PE Setting Boost (dB) IT (mA) VOSE-DC (mV p-p) VOSE-BOOST (mV p-p) VOCM (V) VH (V) VL (V)
0 0 20 500 500 3.050 3.3 2.8
1 6 40 500 1000 2.8 3.3 2.3
Table 10. Symbol Definitions
Symbol
Formula
Definition
VOSE-DC IT|PE = 0 × 25 Ω
Single-ended output voltage swing after settling
V
OSE-BOOST
I
T
× 25 Ω
Boosted single-ended output voltage swing
VOCM (DC-Coupled) VTTO – IT/2 × 25 Ω
Common-mode voltage when the output is dc-coupled
VH VOCM + VOSE-BOOST/2 High single-ended output voltage excursion
VL VOCM − VOSE-BOOST/2 Low single-ended output voltage excursion
Data Sheet AD8195
Rev. B | Page 15 of 20
APPLICATIONS INFORMATION
FRONT PANEL BUFFER FOR ADVANCED TV
A front panel input provides easy access to an HDMI connector
for connecting devices, such as an HD camcorder or video game
console, to an HDTV. In designs where the main PCB is not
near the side or front of the HDTV, a front panel HDMI input
must be connected to the main board through a cable. The
AD8195 enables the implementation of a front or side panel
HDMI input for an HDTV by buffering the HDMI signals and
compensating for the cable interconnect to the main board.
A simplified typical front panel buffer circuit is shown in Figure 33.
The AD8195 is designed to have an HDMI/DVI receiver pinout
at its input and a transmitter pinout at its output. This makes
the AD8195 ideal for use in television set front panel connectors
and AVR-type applications where a designer routes both the
inputs and the outputs directly to HDMI/DVI connectors.
One advantage of the AD8195 in a television set front panel
connector is that all of the high speed signals can be routed on
one side (the topside) of the board. The AD8195 provides 12 dB
of input equalization so it can compensate for the signal degra-
dation of long input cables. In addition, the AD8195 can also
provide up to 6 dB of output preemphasis that boosts the output
TMDS signals and allows the AD8195 to precompensate when
driving long PCB traces or high loss output cables. The net
effect of the input equalization and output preemphasis of the
AD8195 is that the AD8195 can compensate for the signal
degradation of both the input and output cables; it acts to reopen
a closed input data eye and transmit a full swing HDMI signal
to an end receiver.
Placement of a shunt resistor from the negative terminal of the
input TMDS clock differential pair to ground is recommended
to prevent amplification of ambient noise resulting in a large
swing signal at the input of the HDMI receiver.
For the CEC and DDC buffer circuits to be active when the
local supply is off, power must be provided to the AD8195
AMUXVCC supply pin from the HDMI source. The 5 V from
the HDMI connector and the local 5 V supply should be isolated
with diodes to prevent contention. Additionally, the diodes
should be selected such that the forward voltage drop from the
local supply is less than from the HDMI source so that current
is not drawn from the HDMI source when the local supply is on.
The rise time of the CEC buffer output is set by the time constant
of the pull-up resistance and the capacitance on the output node.
An additional external pull-up resistance is recommended at
the CEC output to allow for optimal rise times. A Thevenin
equivalent 2 kΩ pull-up to 3.3 V is shown in Figure 34.
The VREF_IN and VREF_OUT pins are voltage references for
the input and output pins of DDC buffer. The external pull-up
resistors for the DDC bus should be connected to the same
voltage as applied to the respective VREF pin.
Typically, an EDID EEPROM is placed prior to the AD8195,
as shown in Figure 34. If desired, the EDID EEPROM can be
downstream of the AD8195. This optional configuration is also
illustrated in Figure 34. Regardless of the configuration, the
pull-up voltage at the DDC output should be on even when the
local system power supply is off.
To ensure that the AD8195 operates properly, Pin 21 (COMP)
should be tied to ground through a 10 µF bypass capacitor. A 34 kΩ
pull-up resistor from COMP to AMUXVCC is integrated on chip.
HDTV SET
HDMI RX
AD8195
MAIN PCB
CABLE
07049-008
Figure 33. AD8195 as a Front Panel Buffer for an HDTV
AD8195 Data Sheet
Rev. B | Page 16 of 20
07049-007
0.01µF
0.01µF
47kΩ47kΩ
1kΩ
5V 3.3V
DDC_SCL
DDC_SDA
TMDS TMDS
2kΩ
ESD
PROTECTION
(OPTIONAL)
AMUXVCC AVCC, VTTI,
VTTO
EDID
EEPROM
HDMI
RECEIVER
SCL_OUT
SDA_OUT
SCL_IN
SDA_IN
CEC
MCU
3.3V OR 5V
VREF_OUT
2kΩ2kΩ
3kΩ
IPA3
INA3
IPA2
INA2
IPA1
INA1
IPA0
INA0
OP3
ON3
OP2
ON2
OP1
ON1
OP0
ON0
CEC_IN
CEC_OUT
AVEE
AD8195
D2+
D2–
D1+
D1–
D0+
D0–
CLK+
CLK–
VREF_IN
AMUXVCC
1µF 0.01µF
AMUXVCC
CABLE OR PCB
INTERCONNECT
EDID
EEPROM
TYPICAL EDID
PLACEMENT
OPTIONAL EDID
PLACEMENT
HDMI
CONNECTOR
D2+
D2–
D1+
D1–
D0+
D0–
CLK+
CLK–
5V
DDC_SCL
DDC_SDA
CEC
HPD
6kΩ
COMP
10µF
Figure 34. AD8195 Typical Application Simplified Schematic
CABLE LENGTHS AND EQUALIZATION
The AD8195 offers 12 dB of equalization for the high speed inputs.
The equalizer of the AD8195 is optimized for video data rates
of 2.25 Gbps and can equalize more than 20 meters of 24 AWG
HDMI cable at the input for 1080p video with deep color.
The length of cable that can be used in a typical HDMI/DVI
application depends on a large number of factors, including the
following:
• Cable quality: the quality of the cable in terms of conductor
wire gauge and shielding. Thicker conductors have lower
signal degradation per unit length.
• Data rate: the data rate being sent over the cable. The signal
degradation of HDMI cables increases with data rate.
• Edge rates: the edge rates of the source input. Slower input
edges result in more significant data eye closure at the end
of a cable.
• Receiver sensitivity: the sensitivity of the terminating
receiver.
TMDS OUTPUT RISE/FALL TIMES
The TMDS outputs of the AD8195 are designed for optimal
performance even when external components are connected,
such as external ESD protection, common-mode filters, and
the HDMI connector. In applications where the output of the
AD8195 is connected to an HDMI output connector, additional
ESD protection is recommended. The capacitance of the addi-
tional ESD protection circuits for the TMDS outputs should be
as low as possible. In a typical application, the output rise/fall
times are compliant with the HDMI specification at the output
of the HDMI connector.
PCB LAYOUT GUIDELINES
The AD8195 is used to buffer two distinctly different types of
signals, both of which are required for HDMI and DVI video.
These signal groups require different treatment when laying out
a PCB.
The first group of signals carries the audiovisual (AV) data encoded
by a technique called transition minimized differential signaling
(TMDS) and, in the case of HDMI, is also encrypted according to
the high bandwidth digital copy protection (HDCP) standard.
HDMI/DVI video signals are differential, unidirectional, and
high speed (up to 2.25 Gbps). The channels that carry the video
data must have controlled impedance, be terminated at the
receiver, and be capable of operating up to at least 2.25 Gbps. It
is especially important to note that the differential traces that
carry the TMDS signals should be designed with a controlled
differential impedance of 100 Ω. The AD8195 provides single-
ended 50 Ω terminations on chip for both its inputs and outputs.
Transmitter termination is not fully specified by the HDMI
standard, but its inclusion improves the overall system signal
integrity.
The second group of signals consists of low speed auxiliary control
signals used for communication between a source and a sink.
These signals include the DDC bus (this is an I2C bus used to
send EDID information and HDCP encryption keys between
the source and the sink) and the CEC line. These auxiliary signals
are bidirectional, low speed, and transferred over a single-ended
transmission line that does not need to have controlled impedance.
The primary concern with laying out the auxiliary lines is ensuring
that they conform to the I2C bus standard and do not have
excessive capacitive loading.
Data Sheet AD8195
Rev. B | Page 17 of 20
TMDS Signals
In the HDMI/DVI standard, four differential pairs carry the
TMDS signals. In DVI, three of these pairs are dedicated to
carrying RGB video and sync data. For HDMI, audio data is
also interleaved with the video data; the DVI standard does not
incorporate audio information. The fourth high speed differential
pair is used for the AV data-word clock and runs at one-tenth
the speed of the TMDS data channels.
The four high speed channels of the AD8195 are identical.
No concession was made to lower the bandwidth of the fourth
channel for the pixel clock, so any channel can be used for any
TMDS signal. The user chooses which signal is routed over
which channel. Additionally, the TMDS channels are symmetric;
therefore, the p and n of a given differential pair are interchange-
able, provided the inversion is consistent across all inputs and
outputs of the AD8195. However, the routing between inputs
and outputs through the AD8195 is fixed. For example, Input
Channel 0 is always buffered to Output Channel 0, and so forth.
The AD8195 buffers the TMDS signals, and the input traces can
be considered electrically independent of the output traces. In
most applications, the quality of the signal on the input TMDS
traces is more sensitive to the PCB layout. Regardless of the data
being carried on a specific TMDS channel, or whether the TMDS
line is at the input or the output of the AD8195, all four high
speed signals should be routed on a PCB in accordance with the
same RF layout guidelines.
Layout for the TMDS Signals
The TMDS differential pairs can be either microstrip traces,
routed on the outer layer of a board, or stripline traces, routed
on an internal layer of the board. If microstrip traces are used,
there should be a continuous reference plane on the PCB layer
directly below the traces. If stripline traces are used, they must
be sandwiched between two continuous reference planes in the
PCB stack-up. Additionally, the p and n of each differential pair
must have a controlled differential impedance of 100 Ω. The
characteristic impedance of a differential pair is a function of
several variables, including the trace width, the distance separating
the two traces, the spacing between the traces and the reference
plane, and the dielectric constant of the PCB binder material.
Interlayer vias introduce impedance discontinuities that can
cause reflections and jitter on the signal path; therefore, it is
preferable to route the TMDS lines exclusively on one layer of the
board, particularly for the input traces. In addition, to prevent
unwanted signal coupling and interference, route the TMDS
signals away from other signals and noise sources on the PCB.
Both traces of a given differential pair must be equal in length
to minimize intrapair skew. Maintaining the physical symmetry
of a differential pair is integral to ensuring its signal integrity;
excessive intrapair skew can introduce jitter through duty cycle
distortion (DCD). The p and n of a given differential pair should
always be routed together in order to establish the required
100 Ω differential impedance. Enough space should be left
between the differential pairs of a given group so that the n of
one pair does not couple to the p of another pair. For example, one
technique is to make the interpair distance 4 to 10 times wider
than the intrapair spacing.
Any group of four TMDS channels (input or output) should have
closely matched trace lengths to minimize interpair skew. Severe
interpair skew can cause the data on the four different channels
of a group to arrive out of alignment with one another. A good
practice is to match the trace lengths for a given group of four
channels to within 0.05 inches on FR4 material.
The length of the TMDS traces should be minimized to reduce
overall signal degradation. Commonly used PCB material, such
as FR4, is lossy at high frequencies, so long traces on the circuit
board increase signal attenuation, resulting in decreased signal
swing and increased jitter through intersymbol interference (ISI).
Controlling the Characteristic Impedance of a TMDS
Differential Pair
The characteristic impedance of a differential pair depends on a
number of variables, including the trace width, the distance
between the two traces, the height of the dielectric material
between the trace and the reference plane below it, and the
dielectric constant of the PCB binder material. To a lesser
extent, the characteristic impedance also depends upon the
trace thickness and the presence of solder mask.
There are many combinations that can produce the correct
characteristic impedance. It is generally required to work with
the PCB fabricator to obtain a set of parameters to produce the
desired results.
One consideration is how to guarantee a differential pair with a
differential impedance of 100 Ω over the entire length of the trace.
One technique is to change the width of the traces in a differential
pair based on how closely one trace is coupled to the other. When
the two traces of a differential pair are close and strongly coupled,
they should have a width that produces a 100 Ω differential
impedance. When the traces split apart to go into a connector,
for example, and are no longer so strongly coupled, the width of
the traces should be increased to yield a differential impedance of
100 Ω in the new configuration.
AD8195 Data Sheet
Rev. B | Page 18 of 20
TMDS Terminations
The AD8195 provides internal 50 Ω single-ended terminations
for all of its high speed inputs and outputs. It is not necessary to
include external termination resistors for the TMDS differential
pairs on the PCB.
The output termination resistors of the AD8195 back terminate
the output TMDS transmission lines. These back terminations
act to absorb reflections from impedance discontinuities on the
output traces, improving the signal integrity of the output traces
and adding flexibility to how the output traces can be routed.
For example, interlayer vias can be used to route the AD8195
TMDS outputs on multiple layers of the PCB without severely
degrading the quality of the output signal.
Auxiliary Control Signals
There are three single-ended control signals associated with
each source or sink in an HDMI/DVI application. These are
CEC and two DDC lines. The two signals on the DDC bus are
SDA and SCL (serial data and serial clock, respectively). These
three signals can be buffered through the AD8195 and do not
need to be routed with the same strict considerations as the
high speed TMDS signals.
In general, it is sufficient to route each auxiliary signal as a
single-ended trace. These signals are not sensitive to impedance
discontinuities, do not require a reference plane, and can be
routed on multiple layers of the PCB. However, it is best to
follow strict layout practices whenever possible to prevent the
PCB design from affecting the overall application. The specific
routing of the CEC and DDC lines depends on the application
in which the AD8195 is being used.
For example, the maximum speed of signals present on the
auxiliary lines is 100 kHz I2C data on the DDC lines; therefore,
any layout that enables 100 kHz I2C to be passed over the DDC
bus should suffice. The HDMI specification, however, places a
strict 50 pF limit on the amount of capacitance that can be
measured on either SDA or SCL at the HDMI input connector.
This 50 pF limit includes the HDMI connector, the PCB, and
whatever capacitance is seen at the input of the AD8195. There
is a similar limit of 150 pF of input capacitance for the CEC line.
The parasitic capacitance of traces on a PCB increases with
trace length. To help ensure that a design satisfies the HDMI
specification, the length of the CEC and DDC lines on the PCB
should be made as short as possible. Additionally, if there is a
reference plane in the layer adjacent to the auxiliary traces in
the PCB stack-up, relieving or clearing out this reference plane
immediately under the auxiliary traces significantly decreases
the amount of parasitic trace capacitance. An example of the
board stack-up is shown in Figure 35.
The AD8195 buffers the auxiliary signals; therefore, only the
input traces, connector, and AD8195 input capacitance must be
considered when designing a PCB to meet HDMI specifications.
PCB DIELECTRIC
LAYER 1: MICROSTRIP
SILKSCREEN
SILKSCREEN
PCB DIELECTRIC
PCB DIELECTRIC
LAYER 2: REFERENCE PLANE
LAYER 3: REFERENCE PLANE
LAYER 4: MICROSTRIP
W3W 3W
REFERENCE LAYER
RELIEVED UNDERNEATH
MICROSTRIP
07049-009
Figure 35. Example Board Stack-Up
Power Supplies
The AD8195 has four separate power supplies referenced to a
single ground, AVEE. The supply/ground pairs are
• AVCC/AVEE
• VT TI/AVEE
• VTTO/AVEE
• AMUXVCC/AVEE.
The AVCC/AVEE (3.3 V) supply powers the core of the AD8195.
The VTTI/AVEE supply (3.3 V) powers the input termination
(see Figure 30). Similarly, the VTTO/AVEE supply (3.3 V)
powers the output termination (see Figure 31). The AMUXVCC/
AVEE supply (5 V) powers the auxiliary buffer core.
In a typical application, all pins labeled AVEE should be connected
directly to ground. All pins labeled AVCC, VTTI, or VTTO
should be connected to 3.3 V, and Pin AMUXVCC should be
tied to 5 V. The AVCC supply powers the TMDS buffers while
AMUXVCC powers the DDC/CEC buffers. The AMUXVCC
pin can be connected to the 5 V supply provided from the input
HDMI connector to ensure that the DDC and CEC buffers
remain functional when the system is powered off. The supplies
can also be powered individually, but care must be taken to
ensure that each stage of the AD8195 is powered correctly.
DDC Reference Inputs
The VREF_IN and VREF_OUT voltages (3.3 V to 5 V) provide
reference levels for the DDC buffers. Both voltages are referenced
to AVEE. The voltage applied at these reference inputs should
be the same as the pull-up voltage for corresponding DDC bus.
Unused DDC/CEC Buffers
If the DDC and the CEC buffers are not used, the AD8195 does
not require a 5 V supply for AMUXVCC. For operation without
the buffers, tie AMUXVCC to AVCC (nominally 3.3 V) and tie
VREF_IN and VREF_OUT to AVEE (nominally ground).
Other buffer pins can be left floating.
Ci 1 #:Eccéwflg.
Data Sheet AD8195
Rev. B | Page 19 of 20
OUTLINE DIMENSIONS
1
40
10
11
31
30
21
20
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
06-01-2012-D
0.50
BSC
PIN 1
INDICATOR
4.50 REF
0.20 MIN
0.50
0.40
0.30
TOP VIEW
12° MAX 0.80 MAX
0.65 TYP
SEATING
PLANE
COPLANARITY
0.08
1.00
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.20 REF
4.25
4.10 SQ
3.95
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
6.10
6.00 SQ
5.90
5.85
5.75 SQ
5.65
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
EXPOSED
PAD
(BOTTOM VIEW)
Figure 36. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm × 6 mm Body, Very Thin Quad
(CP-40-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description
Package
Option
Ordering
Quantity
AD8195ACPZ −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-40-1
AD8195ACPZ-R7 −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7” Tape and Reel CP-40-1 750
AD8195-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
ANALOG DEVICES www.analng.cnm
AD8195 Data Sheet
Rev. B | Page 20 of 20
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07049-0-8/12(B)