Texas Instruments 的 SN54HC74, SN74HC74 規格書

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SNx4HC74 Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset

1 Features

• Buffered inputs

• Wide operating voltage range: 2 V to 6 V

• Wide operating temperature range: -40°C to +85°C

• Supports fanout up to 10 LSTTL loads

• Significant power reduction compared to LSTTL

logic ICs

2 Applications

•Convert a momentary switch to a toggle switch

• Divide a clock signal by 2 or 4

3 Description

The SNx4HC74 devices contain two independent

D-type positive-edge-triggered flip-flops with

asynchronous preset and clear pins for each.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

SN74HC74D SOIC (14) 8.70 mm × 3.90 mm

SN74HC74DB SSOP (14) 6.50 mm × 5.30 mm

SN74HC74N PDIP (14) 19.30 mm × 6.40 mm

SN74HC74NS SO (14) 10.20 mm × 5.30 mm

SN74HC74PW TSSOP (14) 5.00 mm × 4.40 mm

SN54HC74J CDIP (14) 21.30 mm × 7.60 mm

SN54HC74W CFP (14) 9.20 mm × 6.29 mm

SN54HC74FK LCCC (20) 8.90 mm × 8.90 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

xCLK C

xPRE

xCLR

Functional pinout

SN74HC74, SN54HC74

SCLS094F – DECEMBER 1982 – REVISED JUNE 2021

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents

1 Features............................................................................1

2 Applications..................................................................... 1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

Pin Functions.................................................................... 3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics - 74..................................... 5

6.6 Electrical Characteristics - 54..................................... 6

6.7 Timing Requirements - 74...........................................6

6.8 Timing Requirements - 54...........................................7

6.9 Switching Characteristics - 74.....................................7

6.10 Switching Characteristics - 54...................................8

6.11 Operating Characteristics..........................................8

6.12 Typical Characteristics.............................................. 8

7 Parameter Measurement Information............................ 9

8 Detailed Description......................................................10

8.1 Overview................................................................... 10

8.2 Functional Block Diagram......................................... 10

8.3 Feature Description...................................................10

8.4 Device Functional Modes..........................................11

9 Application and Implementation.................................. 12

9.1 Application Information............................................. 12

9.2 Typical Application.................................................... 12

10 Power Supply Recommendations..............................15

11 Layout........................................................................... 16

11.1 Layout Guidelines................................................... 16

11.2 Layout Example...................................................... 16

12 Device and Documentation Support..........................17

12.1 Documentation Support.......................................... 17

12.2 Support Resources................................................. 17

12.3 Trademarks.............................................................17

12.4 Electrostatic Discharge Caution..............................17

12.5 Glossary..................................................................17

13 Mechanical, Packaging, and Orderable

Information.................................................................... 17

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision E (December 2015) to Revision F (June 2021) Page

• Updated to new data sheet standards................................................................................................................ 1

• RθJA increased for the D (86 to 133.6 ℃/W), DB (96 to 107.7 ℃/W), NS (76 to 122.6 ℃/W), and PW (113 to

151.7 ℃/W) and decreased for the N package (80 to 61.9 ℃/W) .....................................................................5

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TEXAS INSTRUMENTS HHHHHHH 115

5 Pin Configuration and Functions

1CLK

1PRE

GND

2CLR

2CLK

2PRE

VCC

1CLR

D, DB, N, NS, PW, J, or W Package

14-Pin SOIC, SSOP, PDIP, SO, TSSOP, CDIP, or CFP

Top View

3 2 1 20 19

9 10 11 12 13

1CLK

1PRE

1CLR

NC VCC

2CLR

1Q GND NC 2Q 2Q

2CLK

2PRE

FK Package

20-Pin LCCC

Top View

Pin Functions

I/O DESCRIPTION

NAME

D, DB, N,

NS, PW, J,

or W

1 CLR 1 2 Input Channel 1, Clear Input, Active Low

1D 2 3 Input Channel 1, Data Input

1CLK 3 4 Input Channel 1, Positive edge triggered clock input

1 PRE 4 6 Input Channel 1, Preset Input, Active Low

1Q 5 8 Output Channel 1, Output

1 Q 6 9 Output Channel 1, Inverted Output

GND 7 10 — Ground

2 Q 8 12 Output Channel 2, Inverted Output

2Q 9 13 Output Channel 2, Output

2 PRE 10 14 Input Channel 2, Preset Input, Active Low

2CLK 11 16 Input Channel 2, Positive edge triggered clock input

2D 12 18 Input Channel 2, Data Input

2 CLR 13 19 Input Channel 2, Clear Input, Active Low

VCC 14 20 — Positive Supply

NC 1, 5, 7, 11, 15,

17 — Not internally connected

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

VCC Supply voltage –0.5 7 V

IIK Input clamp current(2) VI < –0.5 V or VI > VCC ±20 mA

IOK Output clamp current(2) VI < –0.5 V or VI > VCC ±20 mA

IOContinuous output current VO = 0 to VCC ±25 mA

Continuous current through VCC or GND ±50 mA

TJJunction temperature(3) 150 °C

Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated

under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

(3) Guaranteed by design.

6.2 ESD Ratings

VALUE UNIT

V(ESD) Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/

JEDEC JS-001(1) ±2000

Charged-device model (CDM), per JEDEC

specification JESD22-C101(2) ±1500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

VCC Supply voltage 2 5 6 V

VIH High-level input voltage

VCC = 2 V 1.5

VVCC = 4.5 V 3.15

VCC = 6 V 4.2

VIL Low-level input voltage

VCC = 2 V 0.5

VVCC = 4.5 V 1.35

VCC = 6 V 1.8

VIInput voltage 0 VCC V

VOOutput voltage 0 VCC V

Δt/Δv Input transition rise and fall rate

VCC = 2 V 1000

nsVCC = 4.5 V 500

VCC = 6 V 400

TAOperating free-air temperature SN54HC00 –55 125 °C

SN74HC00 –40 85

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6.4 Thermal Information

THERMAL METRIC(1)

SN74HC74 SN54HC74

UNITD (SOIC) DB

(SSOP) N (PDIP) NS (SO) PW

(TSSOP) J (CDIP) W (CFP) FK

(LCCC)

14 PINS 14 PINS 14 PINS 14 PINS 14 PINS 14 PINS 14 PINS 20 PINS

RθJA

Junction-to-ambient

thermal resistance 133.6 107.7 61.9 122.6 151.7 N/A N/A N/A °C/W

Rθ

JC(to

Junction-to-case (top)

thermal resistance 89.0 57.4 49.7 81.8 79.4 15.05 14.65 5.61 °C/W

RθJB

Junction-to-board

thermal resistance 89.5 57.9 41.7 83.8 94.7 N/A N/A N/A °C/W

ΨJT

Junction-to-top

characterization

parameter

45.5 17.6 29.3 45.4 25.2 N/A N/A N/A °C/W

ΨJB

Junction-to-board

characterization

parameter

89.1 57.2 41.4 83.4 94.1 N/A N/A N/A °C/W

Rθ

JC(bo

Junction-to-case

(bottom) thermal

resistance

N/A N/A N/A N/A N/A N/A N/A N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics - 74

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).

PARAMETER TEST CONDITIONS VCC

Operating free-air temperature (TA)

UNIT25°C -40°C to 85°C

MIN TYP MAX MIN TYP MAX

VOH

High-level

output voltage

VI = VIH

or VIL

IOH = –20 µA

2 V 1.9 1.998 1.9

4.5 V 4.4 4.499 4.4

6 V 5.9 5.999 5.9

IOH = –4 mA 4.5 V 3.98 4.3 3.84

IOH = –5.2 mA 6 V 5.48 5.8 5.34

VOL

Low-level output

voltage

VI = VIH

or VIL

IOL = 20 µA

2 V 0.002 0.1 0.1

4.5 V 0.001 0.1 0.1

6 V 0.001 0.1 0.1

IOL = 4 mA 4.5 V 0.17 0.26 0.33

IOL = 5.2 mA 6 V 0.15 0.26 0.33

Input leakage

current VI = VCC or 0 6 V ±0.1 ±1 µA

ICC Supply current VI = VCC

or 0 IO = 0 6 V 4 40 µA

Input

capacitance 2 V to 6 V 3 10 10 pF

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6.6 Electrical Characteristics - 54

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).

PARAMETER TEST CONDITIONS VCC

Operating free-air temperature (TA)

UNIT25°C –40°C to 85°C –55°C to 125°C

MIN TYP MAX MIN TYP MAX MIN TYP MAX

VOH

High-level

output voltage

VI = VIH or

VIL

IOH = -20

µA

2 V 1.9 1.998 1.9 1.9

4.5 V 4.4 4.499 4.4 4.4

6 V 5.9 5.999 5.9 5.9

IOH = -6

mA 4.5 V 3.98 4.3 3.84 3.7

IOH = -7.8

mA 6 V 5.48 5.8 5.34 5.2

VOL

Low-level output

voltage

VI = VIH or

VIL

IOL = 20

µA

2 V 0.002 0.1 0.1 0.1

4.5 V 0.001 0.1 0.1 0.1

6 V 0.001 0.1 0.1 0.1

IOL = 6 mA 4.5 V 0.17 0.26 0.33 0.4

IOL = 7.8

mA 6 V 0.15 0.26 0.33 0.4

Input leakage

current VI = VCC or 0 6 V ±0.1 ±1 ±1 µA

ICC Supply current VI = VCC or

0IO = 0 6 V 2 20 40 µA

Input

capacitance

2 V to

6 V 3 10 10 10 pF

6.7 Timing Requirements - 74

over operating free-air temperature range (unless otherwise noted)

VCC

Operating free-air temperature (TA)

UNIT25°C –40°C to 85°C

MIN TYP MAX MIN TYP MAX

fclock Clock frequency

2 V 6 5

MHz4.5 V 31 25

6 V 0 36 0 29

twPulse duration

PRE or CLR low

2 V 100 125

4.5 V 20 25

6 V 14 21

CLK high or low

2 V 80 100

4.5 V 16 20

6 V 14 17

tsu Setup time before CLK↑

Data

2 V 100 125

4.5 V 20 25

6 V 17 21

PRE or CLR

inactive

2 V 25 30

4.5 V 5 6

6 V 4 5

th Hold time, data after CLK↑

2 V 0 0

ns4.5 V 0 0

6 V 0 0

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6.8 Timing Requirements - 54

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).

VCC

Operating free-air temperature (TA)

UNIT25°C –40°C to 85°C –55°C to 125°C

MIN TYP MAX MIN TYP MAX MIN TYP MAX

fclock Clock frequency

2 V 6 5 4.2

ns4.5 V 31 25 21

6 V 0 36 0 29 0 25

twPulse duration

PRE or CLR

low

2 V 100 125 150

4.5 V 20 25 30

6 V 14 21 25

CLK high or

low

2 V 80 100 120

4.5 V 16 20 24

6 V 14 17 20

tsu Setup time before CLK↑

Data

2 V 100 125 150

4.5 V 20 25 30

6 V 17 21 25

PRE or CLR

inactive

2 V 25 30 40

4.5 V 5 6 8

6 V 4 5 7

th Hold time, data after CLK↑

2 V 0 0 0

MHz4.5 V 0 0 0

6 V 0 0 0

6.9 Switching Characteristics - 74

over operating free-air temperature range (unless otherwise noted)

PARAMETER FROM TO VCC

Operating free-air temperature (TA)

UNIT25°C –40°C to 85°C

MIN TYP MAX MIN TYP MAX

fmax

2 V 6 10 6

MHz4.5 V 31 50 25

6 V 36 60 29

tpd Propagation delay

PRE or

CLR Q or Q

2 V 70 230 290

4.5 V 20 46 58

6 V 15 39 49

CLK Q or Q

2 V 70 175 220

4.5 V 20 35 44

6 V 15 30 39

ttTransition-time Q or Q

2 V 28 75 95

ns4.5 V 8 15 19

6 V 6 13 16

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6.10 Switching Characteristics - 54

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).

PARAMETER FROM TO VCC

Operating free-air temperature (TA)

UNIT25°C –40°C to 85°C –55°C to 125°C

MIN TYP MAX MIN TYP MAX MIN TYP MAX

fmax

2 V 6 10 6 4.2

MHz4.5 V 31 50 25 21

6 V 36 60 29 25

tpd Propagation delay

PRE or

CLR Q or Q

2 V 70 230 290 345

4.5 V 20 46 58 69

6 V 15 39 49 59

CLK Q or Q

2 V 70 175 220 250

4.5 V 20 35 44 50

6 V 15 30 39 42

ttTransition-time Q or Q

2 V 28 75 95 110

ns4.5 V 8 15 19 22

6 V 6 13 16 19

6.11 Operating Characteristics

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

Cpd

Power dissipation capacitance

per gate No load 2 V to 6 V 35 pF

6.12 Typical Characteristics

TA = 25°C

IOH Output High Current (mA)

VOH Output High Voltage (V)

0 1 2 3 4 5 6

2-V

4.5-V

6-V

Figure 6-1. Typical output voltage in the high state

(VOH)

IOL Output Low Current (mA)

VOL Output Low Voltage (V)

0 1 2 3 4 5 6

0.05

0.1

0.15

0.2

0.25

0.3

2-V

4.5-V

6-V

Figure 6-2. Typical output voltage in the low state

(VOL)

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7 Parameter Measurement Information

• Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators

having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.

• The outputs are measured one at a time, with one input transition per measurement.

CL(1)

From Output

Under Test

Test

Point

A. CL= 50 pF and includes probe and jig capacitance.

Figure 7-1. Load Circuit

VOH

VOL

Output

VCC

0 V

Input

tf(1)

tr(1)

90%

10%

90%

10%

tr(1)

90%

10%

tf(1)

90%

10%

A. tt is the greater of tr and tf.

Figure 7-2. Voltage Waveforms Transition Times

Clock

Input 50%

VCC

0 V

50% 50%

VCC

0 V

tsu

Data

Input

Figure 7-3. Voltage Waveforms Setup and Hold

Times

50%

Input 50%

VCC

0 V

Figure 7-4. Voltage Waveforms Pulse Width

50%Input 50%

VCC

0 V

50% 50%

VOH

VOL

tPLH(1) tPHL(1)

VOH

VOL

tPHL(1) tPLH(1)

Output

Output 50% 50%

A. The maximum between tPLH and tPHL is used for tpd.

Figure 7-5. Voltage Waveforms Propagation Delays

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8 Detailed Description

8.1 Overview

The SNx4HC74 devices contain two independent D-type positive-edge-triggered flip-flops with asynchronous

preset and clear pins for each.

8.2 Functional Block Diagram

xCLK C

xPRE

xCLR

8.3 Feature Description

8.3.1 Balanced CMOS Push-Pull Outputs

A balanced output allows the device to sink and source similar currents. The drive capability of this device

may create fast edges into light loads so routing and load conditions should be considered to prevent ringing.

Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without

being damaged. It is important for the output power of the device to be limited to avoid damage due to

over-current. The electrical and thermal limits defined in the Section 6.1 must be followed at all times.

The SN74HC74 can drive a load with a total capacitance less than or equal to the maximum load listed in the

Section 6.9 connected to a high-impedance CMOS input while still meeting all of the datasheet specifications.

Larger capacitive loads can be applied, however it is not recommended to exceed the provided load value. If

larger capacitive loads are required, it is recommended to add a series resistor between the output and the

capacitor to limit output current to the values given in the Section 6.1.

8.3.2 Standard CMOS Inputs

Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground

in parallel with the input capacitance given in the Section 6.5. The worst case resistance is calculated with the

maximum input voltage, given in the Section 6.1, and the maximum input leakage current, given in the Section

6.5, using ohm's law (R = V ÷ I).

Signals applied to the inputs need to have fast edge rates, as defined by the input transition time in the Section

6.3 to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a device

with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.

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8.3.3 Clamp Diode Structure

The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Figure 8-1.

CAUTION

Voltages beyond the values specified in the Section 6.1 table can cause damage to the device.

The recommended input and output voltage ratings may be exceeded if the input and output clamp-

current ratings are observed.

GND

Logic

Input Output

VCC

Device

-IIK

+IIK +IOK

-IOK

Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output

8.4 Device Functional Modes

Table 8-1. Function Table

INPUTS OUTPUTS

PRE CLR CLK D Q Q

L H X X H L

H L X X L H

L L X X H(1) H(1)

H H ↑ H H L

H H ↑ L L H

H H L X Q0Q 0

(1) This configuration is nonstable; that is, it does not persist when

PRE or CLR returns to its inactive (high) level.

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

Toggle switches are typically large, mechanically complex and relatively expensive. It is desirable to use a

momentary switch instead because they are small, mechanically simple and low cost. Some systems require a

toggle switch's functionality but are space or cost constrained and must use a momentary switch instead.

If the data input (D) of the D-type flip-flop is tied to the inverted output ( Q), then each clock pulse will cause

the value at the output (Q) to toggle. The momentary switch can be debounced and connected through a

Schmitt-trigger buffer to the clock input (CLK) to toggle the output.

This application also utilizes a power-on reset circuit to ensure that the output always starts in the LOW state

when power is applied.

9.2 Typical Application

CLR Output

PRE

VCC

CLK

VCC

Figure 9-1. Typical application schematic

9.2.1 Design Requirements

9.2.1.1 Power Considerations

Ensure the desired supply voltage is within the range specified in the Section 6.3. The supply voltage sets the

device's electrical characteristics as described in the Section 6.5.

The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the

SN74HC74 plus the maximum supply current, ICC, listed in the Section 6.5. The logic device can only source or

sink as much current as it is provided at the supply and ground pins, respectively. Be sure not to exceed the

maximum total current through GND or VCC listed in the Section 6.1.

Total power consumption can be calculated using the information provided in CMOS Power Consumption and

Cpd Calculation.

Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear

and Logic (SLL) Packages and Devices.

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CAUTION

The maximum junction temperature, TJ(max) listed in the Section 6.1, is an additional limitation to

prevent damage to the device. Do not violate any values listed in the Section 6.1. These limits are

provided to prevent damage to the device.

9.2.1.2 Input Considerations

Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is

completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used

sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used

for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the

SN74HC74, as specified in the Section 6.5, and the desired input transition rate. A 10-kΩ resistor value is often

used due to these factors.

The SN74HC74 has standard CMOS inputs, so input signal edge rates cannot be slow. Slow input edge rates

can cause oscillations and damaging shoot-through current. The recommended rates are defined in the Section

6.3.

Refer to the Section 8.3 for additional information regarding the inputs for this device.

9.2.1.3 Output Considerations

The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will

decrease the output voltage as specified by the VOH specification in the Section 6.5. Similarly, the ground voltage

is used to produce the output LOW voltage. Sinking current into the output will increase the output voltage as

specified by the VOL specification in the Section 6.5.

Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.

Refer to Section 8.3 for additional information regarding the outputs for this device.

9.2.1.4 Timing Considerations

The SN74HC74 is a clocked device. As such, it requires special timing considerations to ensure normal

operation.

Primary timing factors to consider:

• Maximum clock frequency: the maximum operating clock frequency defined in Section 6.7 is the maximum

frequency at which the device is guaranteed to function. This value refers specifically to the triggering

waveform, measuring from one trigger level to the next.

• Pulse duration: ensure that the triggering event duration is larger than the minimum pulse duration, as

defined in the Section 6.7.

• Setup time: ensure that the data has changed at least one setup time prior to the triggering event, as defined

in the Section 6.7.

• Hold time: ensure that the data remains in the desired state at least one hold time after the triggering event,

as defined in the Section 6.7.

9.2.2 Detailed Design Procedure

1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the

device and electrically close to both the VCC and GND pins. An example layout is shown in the Section 11.

2. Ensure the capacitive load at the output is ≤ 70 pF. This is not a hard limit, however it will ensure optimal

performance. This can be accomplished by providing short, appropriately sized traces from the SN74HC74

to the receiving device.

3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum

output current from the Section 6.1 is not violated. Most CMOS inputs have a resistive load measured in

megaohms; much larger than the minimum calculated above.

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4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase

can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd

Calculation

9.2.3 Application Curves

Time (100 Ps/div)

Voltage (2 V/div)

D001D001

Vout

Vin

Figure 9-2. Waveform for non-debounced switch.

Time (200 ms/div)

Voltage (2 V/div)

D002

Vout

Vin

Figure 9-3. Waveform for debounced switch.

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10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in

the Section 6.3. Each VCC terminal should have a bypass capacitor to prevent power disturbance. A 0.1-μF

capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different

frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor

should be installed as close to the power terminal as possible for best results, as shown in Figure 11-1.

www.ti.com

SN74HC74, SN54HC74

SCLS094F – DECEMBER 1982 – REVISED JUNE 2021

Product Folder Links: SN74HC74 SN54HC74

I TEXAS INSTRUMENTS

11 Layout

11.1 Layout Guidelines

When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many

cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of

a triple-input AND gate are used. Such unused input pins must not be left unconnected because the undefined

voltages at the outside connections result in undefined operational states. All unused inputs of digital logic

devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to

prevent them from floating. The logic level that must be applied to any particular unused input depends on the

function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic

function or is more convenient.

11.2 Layout Example

1CLR

1PRE

GND VCC

2CLR

2PRE

2QGND

VCC

2CLK

1CLK

0.1 F

Unused input

tied to GND

Bypass capacitor

placed close to the

device

Avoid 90°

corners for

signal lines

Recommend GND flood fill for

improved signal isolation, noise

reduction, and thermal dissipation

Unused output

left floating

Unused inputs

tied to VCC

Figure 11-1. Example layout for the SN74HC74

SN74HC74, SN54HC74

SCLS094F – DECEMBER 1982 – REVISED JUNE 2021 www.ti.com

Product Folder Links: SN74HC74 SN54HC74

l TEXAS INSTRUMENTS

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

•HCMOS Design Considerations

•CMOS Power Consumption and CPD Calculation

•Designing with Logic

12.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.3 Trademarks

TI E2E™ is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com

SN74HC74, SN54HC74

SCLS094F – DECEMBER 1982 – REVISED JUNE 2021

Product Folder Links: SN74HC74 SN54HC74

I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples

PACKAGE OPTION ADDENDUM

www.ti.com 14-Aug-2021

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

5962-8405601VCA ACTIVE CDIP J 14 1 Non-RoHS

& Green SNPB N / A for Pkg Type -55 to 125 5962-8405601VC

SNV54HC74J

5962-8405601VDA ACTIVE CFP W 14 1 Non-RoHS

& Green SNPB N / A for Pkg Type -55 to 125 5962-8405601VD

SNV54HC74W

84056012A ACTIVE LCCC FK 20 1 Non-RoHS

& Green SNPB N / A for Pkg Type -55 to 125 84056012A

SNJ54HC

74FK

8405601CA ACTIVE CDIP J 14 1 Non-RoHS

& Green SNPB N / A for Pkg Type -55 to 125 8405601CA

SNJ54HC74J

8405601DA ACTIVE CFP W 14 1 Non-RoHS

& Green SNPB N / A for Pkg Type -55 to 125 8405601DA

SNJ54HC74W

JM38510/65302B2A ACTIVE LCCC FK 20 1 Non-RoHS

& Green SNPB N / A for Pkg Type -55 to 125 JM38510/

65302B2A

JM38510/65302BCA ACTIVE CDIP J 14 1 Non-RoHS

& Green SNPB N / A for Pkg Type -55 to 125 JM38510/

65302BCA

JM38510/65302BDA ACTIVE CFP W 14 1 Non-RoHS

& Green SNPB N / A for Pkg Type -55 to 125 JM38510/

65302BDA

M38510/65302B2A ACTIVE LCCC FK 20 1 Non-RoHS

& Green SNPB N / A for Pkg Type -55 to 125 JM38510/

65302B2A

M38510/65302BCA ACTIVE CDIP J 14 1 Non-RoHS

& Green SNPB N / A for Pkg Type -55 to 125 JM38510/

65302BCA

M38510/65302BDA ACTIVE CFP W 14 1 Non-RoHS

& Green SNPB N / A for Pkg Type -55 to 125 JM38510/

65302BDA

SN54HC74J ACTIVE CDIP J 14 1 Non-RoHS

& Green SNPB N / A for Pkg Type -55 to 125 SN54HC74J

SN74HC74D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74

SN74HC74DBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74

SN74HC74DBRG4 ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74

SN74HC74DE4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74

I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Sample: Sample: Samples Samples Samples Samples Samples Samples

PACKAGE OPTION ADDENDUM

www.ti.com 14-Aug-2021

Addendum-Page 2

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

SN74HC74DG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74

SN74HC74DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC74

SN74HC74DRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74

SN74HC74DT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74

SN74HC74N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC74N

SN74HC74NE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC74N

SN74HC74NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74

SN74HC74PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74

SN74HC74PWG4 ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74

SN74HC74PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC74

SN74HC74PWT ACTIVE TSSOP PW 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74

SNJ54HC74FK ACTIVE LCCC FK 20 1 Non-RoHS

& Green SNPB N / A for Pkg Type -55 to 125 84056012A

SNJ54HC

74FK

SNJ54HC74J ACTIVE CDIP J 14 1 Non-RoHS

& Green SNPB N / A for Pkg Type -55 to 125 8405601CA

SNJ54HC74J

SNJ54HC74W ACTIVE CFP W 14 1 Non-RoHS

& Green SNPB N / A for Pkg Type -55 to 125 8405601DA

SNJ54HC74W

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 14-Aug-2021

Addendum-Page 3

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54HC74, SN54HC74-SP, SN74HC74 :

•Catalog : SN74HC74, SN54HC74

•Automotive : SN74HC74-Q1, SN74HC74-Q1

•Enhanced Product : SN74HC74-EP, SN74HC74-EP

•Military : SN54HC74

•Space : SN54HC74-SP

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 14-Aug-2021

Addendum-Page 4

•Enhanced Product - Supports Defense, Aerospace and Medical Applications

•Military - QML certified for Military and Defense Applications

•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«Pt» Reel Dlameter A0 Dimension designed to accommodate the component Width ED Dimension designed to accommodate the component tengtn K0 Dimension designed to accommodate the component thickness 7 w Overau Width onhe carrier tape i P1 Pitch between successive cavtty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE C) O O D O O D O SprocketHotes ,,,,,,,,,,, ‘ User Dtrecllon 0' Feed Pockel Quadrants

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

SN74HC74DBR SSOP DB 14 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1

SN74HC74DR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.1 8.0 16.0 Q1

SN74HC74DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

SN74HC74DR SOIC D 14 2500 330.0 16.4 6.6 9.3 2.1 8.0 16.0 Q1

SN74HC74DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

SN74HC74DT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

SN74HC74NSR SO NS 14 2000 330.0 16.4 8.45 10.55 2.5 12.0 16.2 Q1

SN74HC74PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

SN74HC74PWR TSSOP PW 14 2000 330.0 12.4 6.85 5.45 1.6 8.0 12.0 Q1

SN74HC74PWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 20-Mar-2022

Pack Materials-Page 1

l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SN74HC74DBR SSOP DB 14 2000 853.0 449.0 35.0

SN74HC74DR SOIC D 14 2500 364.0 364.0 27.0

SN74HC74DR SOIC D 14 2500 853.0 449.0 35.0

SN74HC74DR SOIC D 14 2500 340.5 336.1 32.0

SN74HC74DR SOIC D 14 2500 366.0 364.0 50.0

SN74HC74DRG4 SOIC D 14 2500 340.5 336.1 32.0

SN74HC74DRG4 SOIC D 14 2500 853.0 449.0 35.0

SN74HC74DT SOIC D 14 250 210.0 185.0 35.0

SN74HC74NSR SO NS 14 2000 853.0 449.0 35.0

SN74HC74PWR TSSOP PW 14 2000 853.0 449.0 35.0

SN74HC74PWR TSSOP PW 14 2000 366.0 364.0 50.0

SN74HC74PWT TSSOP PW 14 250 853.0 449.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 20-Mar-2022

Pack Materials-Page 2

l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width $ — B - Alignment groove width

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)

5962-8405601VDA W CFP 14 1 506.98 26.16 6220 NA

84056012A FK LCCC 20 1 506.98 12.06 2030 NA

JM38510/65302B2A FK LCCC 20 1 506.98 12.06 2030 NA

M38510/65302B2A FK LCCC 20 1 506.98 12.06 2030 NA

SN74HC74D D SOIC 14 50 506.6 8 3940 4.32

SN74HC74D D SOIC 14 50 507 8 3940 4.32

SN74HC74DE4 D SOIC 14 50 506.6 8 3940 4.32

SN74HC74DE4 D SOIC 14 50 507 8 3940 4.32

SN74HC74DG4 D SOIC 14 50 507 8 3940 4.32

SN74HC74DG4 D SOIC 14 50 506.6 8 3940 4.32

SN74HC74N N PDIP 14 25 506 13.97 11230 4.32

SN74HC74NE4 N PDIP 14 25 506 13.97 11230 4.32

SN74HC74PW PW TSSOP 14 90 530 10.2 3600 3.5

SN74HC74PWG4 PW TSSOP 14 90 530 10.2 3600 3.5

SNJ54HC74FK FK LCCC 20 1 506.98 12.06 2030 NA

PACKAGE MATERIALS INFORMATION

www.ti.com 20-Mar-2022

Pack Materials-Page 3

MECHANICAL DATA AME; CHEF“ ELAR‘REE ?< (a="" cm;="" w”)="" ,eamess="" c="" ’7="" ﬂﬂﬂﬂﬂﬂ\="" f="" e="" e="" e="" e="" ,="" kwwwg="" qﬁjrm“="" a="" i:="" i7="" i4="" i:="" i:="" e7="" eiﬂﬁiﬂﬁzj="" vvwwttﬂﬂ="" 1="" notes="" ah="" ineur="" dimensions="" are="" in="" inches="" (minmeiers).="" this="" cruwg="" i5="" subjeci="" i0="" chcnge="" without="" noiice="" this="" package="" car="" he="" hermeticuiiy="" secied="" mm="" a="" metai="" ic="" i'ciis="" wiihi="" jedec="" n87004="" 50m)="" {mm="" instruments="" w.="" (i.="" cam="">

MECHANICAL DATA NS (R-PDSO-G") PLASTIC SMALL—OUTLINE PACKAGE 14-PINS SHOWN HHFHHFH j j t t H H j, A jﬁ/—\ % lgLLLLLiLLL/ﬁif A MAX 1060 1060 1290 1530 A MW 990 9,90 1230 14‘70 4040062/0 03/03 VOTES: A. AH Hneur dimenswons are m mHHmetevs a, Tm: druwmg 5 subject to change wmom name. 0 Body dwmenswons do not mamas mom ﬂash 0v pmtmswom not to exceed 0,15 INSTRUMEN'IS www.li.m

MECHANICAL DATA W (R—GDFP—F14) CERAM‘C DUAL FLATPACK Ease and Seating Wane 0.250 (6.60) 00‘5 (W) 0235 (5.97) f 0. 026 (0 as) ‘ ‘ 0.005 0.20 _ 00 2.03) 0.004 (0.10) 0,045 1.14 47 0,280 (7.11) MAX 4» 0.019 0.48 1 H i 0.015 50.35; :3 I: T I: :1 :I I: 0.050 (1.27) (:3 ::I 0.390 (9 91) 7' I: :1 0.335 (0.51) :l I: 1:3 ::1 1:3 ::1 “-005 (0-13) “‘N 4 Manes 1:3 I: i 7 E f 0.560 (9.11) 0.360 (0.14) 0.250 (0.35) 0,250 (6.35) 404013072/r 01/11 NOTES: A. AH Hnear dimensions are in inches (m1111meters). B. This dram’ng 1: 5mm \0 change mm noﬁce. c, This package can be hermeticany sea1ed mm 0 ceramic lid usmg glass iriL 0, \ndex paint '15 pmw'ded an cap for terminm idenmcutiun omy. E. Faus within M1L STD 1835 GDFPW’FH i TEXAS INSTRUMENTS www.mmm

GENERIC PACKAGE VIEW J 14 CDIP - 5.08 mm max heigm CERAMIC DUAL IN LINE PACKAGE [I l l 'I I.“ Images above are jusl a represenlalion of the package family, aclual package may vary Refel lo the produd dala sheel for package details. 4040053756 I TEXAS INSTRI IMFNTS

www.ti.com

PACKAGE OUTLINE

14X .008-.014

[0.2-0.36]

TYP

-15

AT GAGE PLANE

-.314.308 -7.977.83[ ]

14X -.026.014 -0.660.36[ ]

14X -.065.045 -1.651.15[ ]

.2 MAX TYP

[5.08] .13 MIN TYP

[3.3]

TYP-.060.015 -1.520.38[ ]

4X .005 MIN

[0.13]

12X .100

[2.54]

.015 GAGE PLANE

[0.38]

-.785.754 -19.9419.15[ ]

B -.283.245 -7.196.22[ ]

CDIP - 5.08 mm max heightJ0014A

CERAMIC DUAL IN LINE PACKAGE

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for

reference only. Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This package is hermitically sealed with a ceramic lid using glass frit.

4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.

5. Falls within MIL-STD-1835 and GDIP1-T14.

PIN 1 ID

(OPTIONAL)

SCALE 0.900

SEATING PLANE

.010 [0.25] C A B

www.ti.com

EXAMPLE BOARD LAYOUT

ALL AROUND

[0.05] MAX.002

.002 MAX

[0.05]

ALL AROUND

SOLDER MASK

OPENING

METAL

(.063)

[1.6]

(R.002 ) TYP

[0.05]

14X ( .039)

[1]

( .063)

[1.6]

12X (.100 )

[2.54]

(.300 ) TYP

[7.62]

CDIP - 5.08 mm max heightJ0014A

CERAMIC DUAL IN LINE PACKAGE

4214771/A 05/2017

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED

SCALE: 5X

SEE DETAIL A SEE DETAIL B

SYMM

DETAIL A

SCALE: 15X

SOLDER MASK

OPENING

METAL

DETAIL B

13X, SCALE: 15X

MECHANICAL DATA D U1 4)} 0 (3'4) DLASHC SMALL 0U ¥N¥ 4040047 5/M 06/1‘ NO'ES, A AH Hnec' dimensmrs c'e m 'mc'ves ['nﬂhmeter5> B Th5 drawer ‘5 subje», ,0 change mm: Home, A Body \cngth docs rm mac mod Hoar, p'omswons, (xv gmc bms Mom mm warmers, or gm buns sha‘ nm exceed 3005 (015) eam swce @ Body mm does 101 meme 11mm ﬁsh. E Rdererce JEDEC MS 012 mam AB, nter‘ec: ﬂash sfu‘ not exceed 0017 (043) each swde {If TEXAS INSTRUMENTS www.1i.com

LAND PATTERN DATA D (R7PDSOmGl4) PLASTlC SMALL OUTLINE Example Board Layout Sterlazlogpeulyngs (Mole c) —— <—14x0,55 -hhheb&&t="" tmedddiﬁ§n%="" 5.40="" 5,40="" @eeeeeej="" rﬁhﬂ§eﬂhj="" —=""> ——l 2x1,27 Example Non Soldermask Delined Pad Example Pad Geometry (See Note c) F Example l / Solder Mask Opening 7 0 07 f (See Note E) All Armlnd ,/ tzllmss/E oa/lz NOTES: A. All linear dimensions are in millimeters. a, Tnis drawan is subject to cnonae wl'lhuul notice. c. Publlcutl’on chs7351 is recommended tor alternate desl’gns. D. Laser ctming apertures w‘lth trapezoidal walls and also roundlng comers wlll otter better paste release. Customers should contact their board assembly site for stencil design recommendations, Reter tc ch—7525 lor otner stencil recommendations. E. Customers snoola contact their ooard looricotion site lor solder musk tolerances between ond oroond signol oods. {I} Tums INSTRUMENTS www.li.com

MECHANICAL DATA "7’7 : 3‘ AST‘C SMAH CJ’ N7 HHHHHHH . . ‘7,4’ 44*, A f;—‘ NO'ES' A AH Hnec' dimensmrs c'e m m'\\me(ers Dwmens'amnq cnd tu‘erc'vcmg per ASME w 5M 1994, Tm drawer ‘5 subje», ,o "hangs wnrau: Home, Budy \evvgih ‘ues m W" Le mom Hush, pyuws‘m Ur guts Ms M exceed 0,15 each m & Rudy wde does NM Wands \Mer end ﬂair \Meﬁead 'Wclsh shaH um exceed 0‘75 each S‘de E Fa‘s WM" JEDEC M07153 MUM "\u>h, main: bus, 01 guie buns shuH {if TEXAS INSTRUMENTS www.ci.com

PW (RiPDsoicM) LAND PATTERN DATA PLASTHC SMALL OUTLINE Example Board Layout (Male 0) —>| ‘,——12x0 65 HHHHHHHi 5,60 HHHHHHHHi l“ l l l Example Non So‘dermask Deﬁned Pad 4 x 1,60 / H l <—0,07 y/="" ah="" around="" pad="" seamelry="" (see="" nale="" c)="" solder="" mask="" opening="" (see="" note="" e)="" stencil="" 0="" en'ln="" s="" (notepd)="" ‘3="" 14x0="" 30="" h="" '«,lzxo="" 65="" ~hhhhhh~="" 5,60="" hhhhhhh—="" example="" example="" 421128472/6="" 08/15="" notes:="" ah="" h‘lneor="" dimensions="" one="" in="" rnihll'rneters.="" tn‘ls="" dvowing="" is="" subject="" lp="" change="" wltnoul="" nallee.="" publl'cotlon="" hpcjssh="" is="" recommended="" lar="" allemale="" deslgns.="" laser="" cutllng="" apertures="" wch="" tropexoidm="" walls="" and="" also="" raund‘lna="" comers="" wlll="" we!="" better="" pasle="" release="" customers="" show="" contact="" their="" board="" assembly="" sl’te="" (ov="" stenci‘="" design="" recommendations.="" reler="" to="" ”50—7525="" lur="" other="" stencl‘="" recommendotluns="" customers="" shou‘d="" contact="" their="" board="" hoercot'lon="" shte="" (or="" solder="" musk="" tolerances="" between="" and="" around="" s'lgnol="" pods.="" *1?="" tums="" instruments="" www.ti.com="">

MECHANICAL DATA N (R—PDlP-T“) PLASTIC DUAL—IN—LINE PACKAGE 16 P15 SHOWN PWS " A L . [NM 15 a 20 16 9 0 775 U 777 0 SZU '1 USE 3 , 1H HH HH r% r’H r"—1 r’H H1 1 A VAX “9‘69? (191591 (23,37) (25,92) 0 250 (6,50‘ A MN [1145‘ 0142‘ 0.350 new 3 O 240 (6.10), 15 92/ (1832/ (2 .59) (23,58) MSiUO‘ (A AA AA Ari AA AA AA R1 &. VAR1AT1CN M RR AC AD 1 B 0070( (17s) 0015 (111) A 0045 (1,111 g n > , ‘ -) 3.020 (0,51) MW w o 5 (0 35) 0200( 38) MAX f, ), Gnu E Home 1 1‘ 9 fix—1%)” 1 0125’ 1/111 4% 0010 (v.37 ) NOM 31a) U L»- J 0450 (13,92) MAX L 202‘ (0,53) » e c 015 (0,35) / \ a; 00‘s (0,Zb)® / \ 1 1 \\¥,// 11/18 Pm (My > @ 20 Pm vendor upho'v mom/r 17/7037 NO'FS A AH Mnec' mmensmr‘ﬁ: B 1m: drawmq 1s sume m muss (m1111mevem) 0 change mm): noﬁce /c\ FuHs wumn JEDEC M57001, except 15 an: 20 p171 'r1111mLm body 1mm (01m A) A The 70 p171 and 15m} shmﬂder Md” 15 a ve'vdnr 0311071, eher NIH Dr 111 wkﬂh INSI'RUMENTS www.1i.com

oo A‘ioyi 55 ﬁHHHHHHHHHHHHﬁ {'3 TEXAS INSTRUMENTS

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

4040065 /E 12/01

28 PINS SHOWN

Gage Plane

8,20

7,40

0,55

0,95

0,25

12,90

12,30

10,50

8,50

Seating Plane

9,907,90

10,50

9,90

0,38

5,60

5,00

0,22

2016

6,50

0,05 MIN

5,905,90

DIM

A MAX

A MIN

PINS **

2,00 MAX

6,90

7,50

0,65 M

0,15

0°–ā8°

0,10

0,09

0,25

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

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