VideoLibrary

PLL Frequency Planning for Spurious Signal Elimination

Analog Devices developed a frequency planning technique, used in conjunction with Phase Locked Loop (PLL) devices, that can eliminate unwanted spurious signals in the output spectrum. Learn how the technique works, its benefits and how to apply it.

7/7/2016 4:41:17 PM

PLL Frequency Planning for Spurious Signal Elimination

ImageManufacturer Part NumberDescriptionAvailable QuantityPriceView Details
EVAL BOARD FOR HMC704LP4E129856-HMC704LP4EEVAL BOARD FOR HMC704LP4E0 - ImmediateSee Page for PricingView Details
EVAL BOARD FOR HMC703LP4EEKIT01-HMC703LP4EEVAL BOARD FOR HMC703LP4E3 - Immediate$8,779.69View Details
EVAL BOARD FOR HMC830LP6GEEKIT01-HMC830LP6GEEVAL BOARD FOR HMC830LP6GE0 - ImmediateSee Page for PricingView Details
EVAL BOARD FOR HMC1031MS8EEVAL01-HMC1031MS8EEVAL BOARD FOR HMC1031MS8E0 - ImmediateSee Page for PricingView Details
EVAL BOARD FOR HMC833LP6GEEKIT01-HMC833LP6GEEVAL BOARD FOR HMC833LP6GE0 - ImmediateSee Page for PricingView Details

Related Videos

Precision DAC Lesson 3: Dynamic Performance Key Specifications
Precision DAC Lesson 3: Dynamic Performance Key Specifications

Publish Date: 2022-02-21

Explaining Phase Noise
Explaining Phase Noise

Publish Date: 2018-10-16

76-81GHz Autonomous Driving CMOS RADAR
76-81GHz Autonomous Driving CMOS RADAR

Publish Date: 2018-03-15

Related Product Highlight

ADF4169 Fractional-N Frequency Synthesizer ADI's ADF4169 device comes in a 24-pin LFCSP package and has a temperature range of -40°C to +125°C.
Interactive RF Signal Chain ADI has complete RF Signal Chain solutions from components to design and development resources available at your fingertips.
Motor Control Solutions Analog Devices covers solutions for all motor control applications whether Brushless DC, AC Induction or Servo.

Related Articles and Blogs

What is the Difference Between Timing Jitter and Phase Noise? Jitter and phase noise are related specifications that quantify the variation in system timing.
The Fundamentals of Phase Locked Loop Frequency Synthesizers With phase locked loop analog frequency synthesizers using integer N and fractional N topologies designers can generate stable clock frequencies up to 30 GHz.
Build a True Wireless Fitness Hearable—Part 2: Audio Processing Use an advanced audio codec that combines low power and extensive functionality to deliver high quality audio and long battery life in fitness hearables.

Related Product Training Modules

RF Spur Charts and Spur Tables Overview of spur charts and tables to predict the performance of down-converting RF mixers.
Data Converters- Five Things to Know About DACs Part 5: Dynamic Performance This presentation will overview DAC dynamic performance factors.
Data Converters- Five Things to Know About DACs Part 4: Buffering Considerations for reference, output, and integrated buffering and buffer amp selection.