The DMAC supports three different transfers: normal transfer mode, repeat transfer mode and block transfer mode. In normal mode, the DMAC transfers a single data item each time the DMAC is triggered. It can be triggered from a number of hardware sources or by a software request. During each transfer, a single 8-, 16-, or 32-bit data item is transferred from the source address to the destination address. Each time the DMAC is triggered, another data item is transferred from the source to the destination. The source & destination address registers keep track of where to move the data from and to. The DMAC can be configured to leave the source & destination addresses unchanged after a transfer, or to automatically increment or decrement one or both. Each address’ behavior can be configured independently allowing easy transfer to and from peripheral registers to memory buffers. Channel 0 has an additional mode that allows an offset to be added to an address rather than just a simple increment or decrement function. The transfer counter is decremented after each transfer, counting down to zero. It is 16-bits wide, allowing over 60,000 transfers to take place before the CPU has to intervene. Setting the transfer counter to zero puts the DMAC in free-run mode. Finally, the DMAC can generate an interrupt to the CPU at the end of each transfer. To restart the DMAC after the end of the transfer, one needs to reset the source & destination addresses and the transfer counter.