True reverse current blocking has the same structure as the previous slide to control the bulk but also includes a comparator monitoring voltage drop from V_OUT to V_IN during the ON state to make a logical decision if the Load Switch should be disabled in the event V_OUT is greater than V_IN. When V_OUT exceeds V_IN, the monitored delta V across the PMOS is compared to a preset internal node threshold voltage denoted as VT_RCB. When this threshold is exceeded, the PMOS of the Load Switch is disabled. With control of both the parasitic diode path and the gate, the state of the load switch being enabled or disabled does not matter and true reverse current blocking is achieved.