LMK1D1204/8 4-Channel or 8-Channel Output LVDS 1.8 V, 2.5 V, and 3.3 V Buffers

Texas Instruments' LMK1D1204/8 clock buffers distribute one of two selectable clock inputs (IN0 and IN1) to four or eight pairs of differential LVDS clock outputs (OUT0 through OUT7) with minimum skew for clock distribution. The devices can accept two clock sources into an input multiplexer. The inputs can be LVDS, LVPECL, LP-HCSL, HCSL, CML, or LVCMOS. These buffers are designed for driving 50 Ω transmission lines. In the case of driving the inputs in single-ended mode, the appropriate bias voltage must be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (logic low). The devices supports a fail-safe function. The LMK1D1204/8 incorporate an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal. The devices operate in a 1.8 V or 2.5 V or 3.3 V supply environment and offer an ambient temperature range of -40°C to +105°C.