LPDDR4 and LPDDR4X DRAMs

Insignis delivers the NLQ series LPDDR4 and NLX series LPDDR4X SDRAM as JEDEC standard drop-in replacements. It is organized as 1- or 2-channels per device, and the individual channel is 8 banks and 16-bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate architecture is essentially a 16n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 16n bits prefetched to achieve very high bandwidth. This LPDDR4 device uses a 2- or 4-clock architecture on the command/address (CA) Bus to reduce the number of input pins in the system. The 6-bit CABus contains command, address, and bank information. Each command uses a 1-, 2-, or 4-clock cycle, during which command information is transferred on the positive edge of the clock.