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Zero ASIC
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Tutorial: Constructing the Parallella aluminum case
Parallella: a Smart(er)TV
Parallella Introduction
關於 Zero ASIC
Zero ASIC 是私人持有的半導體元件公司，總部位於美國麻州劍橋。Zero ASIC 正在開發全球首款針對終端使用者應用的自動化按需客製化系統級封裝設計和製造平台。Zero ASIC 的突破性晶片技術將 ASIC 的開發成本和時間降低幾個數量級，為各種能量受限的高效能系統消除客製化晶片製作的阻礙。
其他內容
ADDITIONAL LINKS
ANALYST REPORTS
- 451 Research Analysts Predicts Accelerators For Future
- Adapteva Believes High-Performance Computing is Ready for an Epiphany
- Adapteva Demos 100Gflops
- Adapteva Included in Gartner Report on Market Trends
- Adapteva: More Flops, Less Watts
- Adapteva’s Epiphany Floating Point Processor Core: A Leading-Edge Lithography May Finally Open Doors
- Epiphany Included in Guide to CPU Cores and Processor IP from Linley Group
- Processors that can do 20 GFLOPS/W
EPIPHANY RESOURCES
PARRALLELLA COMMUNITY FORUM
PARRALLELLA RESOURCES
PRODUCT TRAINING PRESENTATIONS
- A 1024-core 70GFLOP/W Floating Point Manycore Microprocessor
- A 1024-core 70GFLOPS/W Floating Point Manycore Microprocessor
- A 25 GFLOP/W Software Programmable Floating Point Accelerator
- A Manycore Coprocessor Architecture for Heterogeneous Computing
- A Scalable Processor Architecture for the Next Generation of Low Power Supercomputer
- A Sub 2 W 64-Core 100 GFLOPS Accelerator Programmable in C/C++ or OpenCL
- An Alternative to GPU Acceleration For Mobile Platforms (Updated) (GF@DAC-2013)
- An Introduction to the Epiphany Manycore Architecture
- Hybrid System Design: The Only Practical Way
- Improving Engineering Efficiency Through Tiled Hierarchical Flows
- Keynote: Kickstarting the Transition to Parallel Computing With Open Hardware
- Keynote: Presenting the Parallella (MIT ARMFEST-2013)
- Keynote: There’s STILL Plenty of Room at the Bottom!
- Parallella: A Love Story
- Peaceful Coexistence Between Architectures
- The Future of HPC: Task-Parallel, Heterogeneous, Efficient, Open
- The Good, the Bad, the Ugly of Semiconductor Crowd Funding
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