Analog Devices Inc. 的 AD623 規格書

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Single and Dual-Supply, Rail-to-Rail,
Low Cost Instrumentation Amplifier
Data Sheet
AD623
Rev. G Document Feedback
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FEATURES
Easy to use
Rail-to-rail output swing
Input voltage range extends 150 mV below ground
(single supply)
Low power, 550 µA maximum quiescent current
Gain set with one external resistor
Gain range: 1 to 1000
High accuracy dc performance
0.10% gain error (G = 1)
0.35% gain error (G > 1)
Noise: 35 nV/√Hz RTI noise at 1 kHz
Optimal dynamic specifications
800 kHz bandwidth (G = 1)
20 µs settling time to 0.01% (G = 10)
APPLICATIONS
Low power medical instrumentation
Transducer interfaces
Thermocouple amplifiers
Industrial process controls
Difference amplifiers
Low power data acquisition
GENERAL DESCRIPTION
The AD623 is an integrated, single- or dual-supply instrumentation
amplifier that delivers rail-to-rail output swing using supply
voltages from 2.7 V to 12 V. T he AD623 offers user flexibility by
allowing single gain set resistor programming and by conforming
to the 8-lead industry standard pinout configuration. With no
external resistor, the AD623 is configured for unity gain (G = 1),
and with an external resistor, the AD623 can be programmed for
gains of up to 1000.
The accuracy of the AD623 is the result of increasing ac
common-mode rejection ratio (CMRR) coincident with
increasing gain. Line noise harmonics are rejected due to
constant CMRR up to 200 Hz. The AD623 has a wide input
common-mode range and amplifies signals with common-
mode voltages as low as 150 mV below ground. The AD623
maintains optimal performance with dual and single polarity
power supplies.
Table 1. Low Power Upgrades for the AD623
Part No. Total Supply Voltage, VS (V dc)
Typical Quiescent
Current, IQ (µA)
AD8235
5.5
30
AD8236 5.5 33
AD8237 5.5 33
AD8226
36
350
AD8227 36 325
AD8420 36 85
AD8422 36 300
AD8426 36 325 (per channel)
FUNCTIONAL BLOCK DIAGRAM
00778-054
50kΩ
50kΩ 50kΩ
50kΩ
50kΩ 50kΩ
OUTPUT
REF
6
5
8
1
R
G
–R
G
+R
G
A1
A2
A3
+V
S
7
–V
S
4
V
DIFF
2
–
+
V
DIFF
2
–
+
V
CM
2
–IN
3
+IN
Figure 1.
AD623 Data Sheet
Rev. G | Page 2 of 32
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 4
Single Supply ................................................................................. 4
Dual Supplies ................................................................................ 6
Specifications Common to Dual and Single Supplies ............. 8
Absolute Maximum Ratings ............................................................ 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 23
Applications Information .............................................................. 24
Basic Connection ....................................................................... 24
Gain Selection ............................................................................. 24
Reference Terminal .................................................................... 24
Input and Output Offset Voltage Error ................................... 24
Input Protection ......................................................................... 25
RF Interference ........................................................................... 25
Grounding ................................................................................... 26
Input Differential and Common-Mode Range vs. Supply and
Gain .............................................................................................. 28
Additional Information ............................................................. 29
Evaluation Board ............................................................................ 30
General Description ................................................................... 30
Outline Dimensions ....................................................................... 31
Ordering Guide .......................................................................... 32
REVISION HISTORY
9/2020—Rev. F to Rev. G
Changed AD623A to AD623ANZ, AD623ARZ and AD623B to
AD623BNZ, AD623BRZ .............................................. Throughout
Changes to General Description Section ...................................... 1
Changes to Figure 5 Caption, Figure 6 Caption, and Figure 8
Caption ............................................................................................. 10
Changes to Figure 10 Caption, Figure 11, Figure 12, Figure 13,
and Figure 14 ................................................................................... 12
Changes to Figure 15 to Figure 20 ................................................ 13
Changes to Figure 21 to Figure 26 ................................................ 14
Changes to Figure 27 to Figure 32 ................................................ 15
Changes to Figure 33 to Figure 38 ................................................ 16
Changes to Figure 39 to Figure 40 ................................................ 17
Added Figure 41 to Figure 44; Renumbered Sequentially ........ 17
Added Figure 45 to Figure 50 ........................................................ 18
Added Figure 51 to Figure 56 ........................................................ 19
Added Figure 57 to Figure 62 ........................................................ 20
Added Figure 63 to Figure 66 ........................................................ 21
Deleted Single-Supply Data Acquisition System Section and
Figure 53; Renumbered Sequentially ........................................... 21
Added Figure 67 to Figure 69 ........................................................ 22
Change to Figure 70 ....................................................................... 23
Changes to Basic Connection Section and Reference Terminal
Section .............................................................................................. 24
Changes to RF Interference Section ............................................ 25
Change to Figure 77 ....................................................................... 26
Changes to Figure 79 and Output Buffering Section ................. 27
Changes to Input Differential and Common-Mode Range vs.
Supply and Gain Section ................................................................ 28
Changes to Ordering Guide .......................................................... 32
4/2018—Rev. E to Rev. F
Changes to Gain Error Parameter, Nonlinearity Parameter,
Offset Referred to the Input vs. Supply (PSR) Parameter, and
Output Swing Parameter, Table 2 .................................................... 3
Changes to Gain Error Parameter and Offset Referred to the
Input vs. Supply (PSR) Parameter, Table 3 ..................................... 5
Changes to Current Noise Parameter, Table 4 ............................... 7
Changes to Ordering Guide .......................................................... 26
6/2016—Rev. D to Rev. E
Changes to Features Section, General Description Section,
and Figure 1 ........................................................................................ 1
Deleted Connection Diagram Section ............................................ 1
Added Functional Block Diagram Section and Table 1;
Renumbered Sequentially ................................................................ 1
Changes to Single Supply Section ................................................... 3
Changes to Table 3 ............................................................................. 6
Changed Both Dual and Single Supplies Section to
Specifications Common to Dual and Single Supplies Section .... 7
Changes to Table 5 ............................................................................. 8
Added Pin Configuration and Function Descriptions Section,
Figure 2, and Table 6; Renumbered Sequentially .......................... 9
Changes to Figure 5 Caption, Figure 6 Caption, and
Figure 8 Caption ............................................................................. 10
Changes to Figure 17 Caption through Figure 20 Caption ...... 11
Changes to Figure 21 Caption through Figure 26 Caption ...... 12
Changes to Figure 27 Caption and Figure 28 Caption .............. 13
Changes to Theory of Operation Section.................................... 17
Changes to Basic Connection Section ......................................... 18
Changes to Input and Output Offset Voltage Error Section, and
Input Protection Section ................................................................ 19
Data Sheet AD623
Rev. G | Page 3 of 32
Added Additional Information Section ....................................... 23
Added Evaluation Board Section and Figure 56 ......................... 24
Updated Outline Dimensions ........................................................ 25
Changes to Ordering Guide ........................................................... 26
7/2008—Rev. C to Rev. D
Updated Format .................................................................. Universal
Changes to Features Section and General Description Section .. 1
Changes to Table 3 ............................................................................ 6
Changes to Figure 40 ...................................................................... 14
Changes to Theory of Operation Section .................................... 15
Changes to Figure 42 and Figure 43 ............................................. 16
Changes to Table 7 .......................................................................... 19
Updated Outline Dimensions ........................................................ 22
Changes to Ordering Guide ........................................................... 23
9/1999—Rev. B to Rev. C
AD623 Data Sheet
Rev. G | Page 4 of 32
SPECIFICATIONS
SINGLE SUPPLY
Typical at 25°C, single supply, +VS = 5 V, −VS = 0 V, a n d load resistance (RL) = 10 kΩ, unless otherwise noted.
Table 2.
Test Conditions/
Comments
AD623ANZ,
AD623ARZ AD623ARM
AD623BNZ,
AD623BRZ
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
GAIN G = 1 +
(100 k/external
resistor (RG))
Gain Range 1 1000 1 1000 1 1000
Gain Error1 G1 output voltage
(VOUT) = 0.15 V to
3.5 V
G > 1 VOUT =
0.15 V to 4.5 V
G = 1 0.03 0.10 0.03 0.10 0.03 0.05 %
G = 10 0.10 0.35 0.10 0.35 0.10 0.35 %
G = 100 0.10 0.35 0.10 0.35 0.10 0.35 %
G = 1000 0.10 0.35 0.10 0.35 0.10 0.35 %
Nonlinearity G1 VOUT =
0.15 V to 3.5 V
G > 1 VOUT =
0.15 V to 4.5 V
G = 1 to 1000 50 50 50 ppm
Gain vs. Temperature
G = 1 5 10 5 10 5 10 ppm/°C
G > 11 50 50 50 ppm/°C
VOLTAGE OFFSET Total referred to
input (RTI) error =
VOSI + VOSO/G
Input Offset, VOSI 25 200 200 500 25 100 µV
Over Temperature 350 650 160 µV
Average Temperature
Coefficient (Tempco)
0.1 2 0.1 2 0.1 1 µV/°C
Output Offset, VOSO 200 1000 500 2000 200 500 µV
Over Temperature 1500 2600 1100 µV
2.5
10
2.5
10
2.5
10
µV/°C
Offset Referred to the
Input vs. Supply (PSR)
G = 1 80 100 80 100 80 100 dB
G = 10 100 120 100 120 100 120 dB
G = 100 100 130 100 130 100 130 dB
G = 1000 100 130 100 130 100 130 dB
INPUT CURRENT
Input Bias Current 17 25 17 25 17 25 nA
Over Temperature 27.5 27.5 27.5 nA
Average Tempco 25 25 25 pA/°C
Input Offset Current 0.25 2 0.25 2 0.25 2 nA
Over Temperature 2.5 2.5 2.5 nA
Average Tempco 5 5 5 pA/°C
Data Sheet AD623
Rev. G | Page 5 of 32
Test Conditions/
Comments
AD623ANZ,
AD623ARZ AD623ARM
AD623BNZ,
AD623BRZ
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
INPUT
Differential 2||2 2||2 2||2 GΩ||pF
Common-Mode 2||2 2||2 2||2 GΩ||pF
Input Voltage Range2 VS = 3 V to 12 V (−VS) −
0.15
(+VS) −
1.5
(−VS) −
0.15
(+VS) −
1.5
(−VS) −
0.15
(+VS) −
1.5
V
at 60 Hz with 1 kΩ
Source Imbalance
G = 1 Common-mode
voltage (VCM) = 0 V
to 3 V
70 80 70 80 77 86 dB
V
CM
= 0 V to 3 V
90
100
90
100
94
100
dB
G = 100 VCM = 0 V to 3 V 105 110 105 110 105 110 dB
G = 1000 VCM = 0 V to 3 V 105 110 105 110 105 110 dB
OUTPUT
Output Swing RL = 10 kΩ 0.2 (+VS) −
0.5
0.2 (+VS) −
0.5
0.2 (+VS) −
0.5
V
RL = 100 kΩ 0.05 (+VS) −
0.15
0.05 (+VS) −
0.15
0.05 (+VS) −
0.15
V
DYNAMIC RESPONSE
Small Signal −3 dB
Bandwidth
800
800
800
kHz
G = 10 100 100 100 kHz
G = 100 10 10 10 kHz
G = 1000 2 2 2 kHz
Slew Rate 0.3 0.3 0.3 V/µs
Settling Time to 0.01% VS = 5 V
G = 1 Step size = 3.5 V 30 30 30 µs
G = 10 Step size = 4 V,
VCM = 1.8 V
20 20 20 µs
1 Does not include effects of external resistor, RG.
2 One input grounded. G = 1.
AD623 Data Sheet
Rev. G | Page 6 of 32
DUAL SUPPLIES
Typical at 25°C dual supply, VS = ±5 V, and RL = 10 kΩ, unless otherwise noted.
Table 3.
Test Conditions/
Comments
AD623ANZ,
AD623ARZ AD623ARM
AD623BNZ,
AD623BRZ
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
GAIN G = 1 + (100 k/RG)
Gain Range 1 1000 1 1000 1 1000
Gain Error1 G1 VOUT =
−4.8 V to +3.5 V
G > 1 VOUT =
−4.8 V to 4.5 V
G = 1 0.03 0.10 0.03 0.10 0.03 0.05 %
G = 10
0.10
0.35
0.10
0.35
0.10
0.35
%
G = 100 0.10 0.35 0.10 0.35 0.10 0.35 %
G = 1000 0.10 0.35 0.10 0.35 0.10 0.35 %
Nonlinearity G1 VOUT =
−4.8 V to +3.5 V
G > 1 VOUT =
−4.8 V to +4.5 V
G = 1 to 1000 50 50 50 ppm
Gain vs. Temperature
G = 1 5 10 5 10 5 10 ppm/°C
G > 11 50 50 50 ppm/°C
VOLTAGE OFFSET Total RTI error =
VOSI + VOSO/G
Input Offset, VOSI 25 200 200 500 25 100 µV
Over Temperature
350
650
160
µV
Average Tempco 0.1 2 0.1 2 0.1 1 µV/°C
Output Offset, VOSO 200 1000 500 2000 200 500 µV
Over Temperature 1500 2600 1100 µV
Average Tempco 2.5 10 2.5 10 2.5 10 µV/°C
Offset Referred to the
Input vs. Supply (PSR)
G = 1 80 100 80 100 80 100 dB
G = 10 100 120 100 120 100 120 dB
G = 100 100 130 100 130 100 130 dB
G = 1000 100 130 100 130 100 130 dB
INPUT CURRENT
Input Bias Current 17 25 17 25 17 25 nA
Over Temperature 27.5 27.5 27.5 nA
Average Tempco
25
25
25
pA/°C
Input Offset Current 0.25 2 0.25 2 0.25 2 nA
Over Temperature 2.5 2.5 2.5 nA
Average Tempco 5 5 5 pA/°C
INPUT
Input Impedance
Differential 2||2 2||2 2||2 GΩ||pF
Common-Mode 2||2 2||2 2||2 GΩ||pF
Input Voltage Range2 VS = +2.5 V to ±6 V (−VS) –
0.15
(+VS) –
1.5
(−VS) –
0.15
(+VS) –
1.5
(−VS) –
0.15
(+VS) –
1.5
V
Data Sheet AD623
Rev. G | Page 7 of 32
Test Conditions/
Comments
AD623ANZ,
AD623ARZ AD623ARM
AD623BNZ,
AD623BRZ
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
Common-Mode Rejection
at 60 Hz with 1 kΩ
Source Imbalance
G = 1 VCM =
+3.5 V to −5.15 V
70 80 70 80 77 86 dB
G = 10 VCM =
+3.5 V to −5.15 V
90 100 90 100 94 100 dB
G = 100 VCM =
+3.5 V to −5.15 V
105 110 105 110 105 110 dB
G = 1000 VCM =
+3.5 V to −5.15 V
105 110 105 110 105 110 dB
OUTPUT
Output Swing RL = 10 kΩ,
VS = ±5 V
(−VS) +
0.2
(+VS) −
0.5
(−VS) +
0.2
(+VS) −
0.5
(−VS) +
0.2
(+VS) −
0.5
V
RL = 100 kΩ (−VS) +
0.05
(+VS) −
0.15
(−VS) +
0.05
(+VS) −
0.15
(−VS) +
0.05
(+VS) −
0.15
V
DYNAMIC RESPONSE
Small Signal −3 dB
Bandwidth
G = 1 800 800 800 kHz
G = 10 100 100 100 kHz
G = 100 10 10 10 kHz
G = 1000 2 2 2 kHz
Slew Rate
0.3
0.3
0.3
V/µs
Settling Time to 0.01% VS = ±5 V, 5 V step
G = 1 30 30 30 µs
G = 10 20 20 20 µs
1 Does not include effects of external resistor, RG.
2 One input grounded. G = 1.
AD623 Data Sheet
Rev. G | Page 8 of 32
SPECIFICATIONS COMMON TO DUAL AND SINGLE SUPPLIES
Table 4.
Test Conditions/
Comments
AD623ANZ,
AD623ARZ AD623ARM
AD623BNZ,
AD623BRZ
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
NOISE
Voltage Noise, 1 kHz Total RTI noise =
√((eNI)2 + (2eNO/G)2)
Input, Voltage Noise, eni 35 35 35 nV/√Hz
Output, Voltage Noise, eno 50 50 50 nV/√Hz
RTI, 0.1 Hz to 10 Hz
G = 1 3.0 3.0 3.0 µV p-p
G = 1000 1.5 1.5 1.5 µV p-p
Current Noise f = 1 kHz 100 100 100 fA/√Hz
0.1 Hz to 10 Hz 2.5 2.5 2.5 pA p-p
REFERENCE INPUT
Input Resistance, RIN 100 ±
20%
100 ±
20%
100 ±
20%
kΩ
Input Current, IIN Input voltage (V+IN)
= 0 V, reference
voltage (VREF) = 0 V
50 60 50 60 50 60 µA
Voltage Range
−V
S
+V
S
−V
S
+V
S
−V
S
+V
S
V
Gain to Output 1 ±
0.0002
1 ±
0.0002
1 ±
0.0002
V/V
POWER SUPPLY
Operating Range Dual supply ±2.5 ±6 ±2.5 ±6 ±2.5 ±6 V
Single supply 2.7 12 2.7 12 2.7 12 V
Quiescent Current Dual supply 375 550 375 550 375 550 µA
Single supply 305 480 305 480 305 480 µA
Over Temperature 625 625 625 µA
TEMPERATURE RANGE
For Specified Performance −40 +85 −40 +85 −40 +85 °C
Am ESD [elemosmiz d :harge) sensitive device‘ Charged dewzes and (mum baavdi (an dmhavge wwhoux daemon mmough mus pvoducl femurs: paxemed ov pvcprlemy pvoKchon cwcumy. damage may occuv on devlces summed m hlgh energy ESD Thevelove, propev ESD pvetaunons shou‘d be men an avoid pevfovmante degradaman m Iosx of funnmnalwy
Data Sheet AD623
Rev. G | Page 9 of 32
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Supply Voltage 12 V
Internal Power Dissipation1
650 mW
Differential Input Voltage ±6 V
Output Short-Circuit Duration Indefinite
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
1 Specification is for device in free air:
8-Lead PDIP Package: θJA = 95°C/W
8-Lead SOIC Package: θJA = 155°C/W
8-Lead MSOP Package: θJA = 200°C/W
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
AD623 Data Sheet
Rev. G | Page 10 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
00778-001
TOP VIEW
(Not to Scale)
1
2
3
4
–IN
+IN
–V
S
–R
G8
7
6
5
+V
S
OUTPUT
REF
+R
G
AD623
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1
−R
G
Inverting Terminal of External Gain Setting Resistor, R
G
.
2 −IN Inverting In-Amp Input.
3 +IN Noninverting In-Amp Input.
4 −VS Negative Supply Terminal.
5 REF In-Amp Output Reference Input. The voltage input establishes the common-mode voltage of the output.
6 OUTPUT In-Amp Output.
7 +VS Positive Supply Terminal.
8 +RG Noninverting Terminal of External Gain Setting Resistor, RG.
Data Sheet AD623
Rev. G | Page 11 of 32
TYPICAL PERFORMANCE CHARACTERISTICS
At 25°C, VS = ±5 V, and RL = 10 kΩ, unless otherwise noted.
–100 –80 –60 –40 –20 020 40 60 80 100 120 140
UNITS
INPUT OFFSET VOLTAGE (µV)
280
0
240
200
160
80
40
120
260
220
180
140
60
20
100
300
00778-003
Figure 3. Typical Distribution of Input Offset Voltage,
N-8 and R-8 Package Options
–800 –600 –400 –200 0200 400 600 800
UNITS
OUTPUT OFFSET VOLTAGE (µV)
0
480
420
360
300
240
180
120
60
00778-004
Figure 4. Typical Distribution of Output Offset Voltage,
N-8 and R-8 Package Options
–80 –60 –40 –20 020 40 60 80 100
UNITS
INPUT OFFSET VOLTAGE (µV)
0
22
20
18
16
14
12
10
8
6
4
2
00778-005
Figure 5. Typical Distribution of Input Offset Voltage,
+VS = 5 V, −VS = 0 V, VREF = +0.125 V, N-8 and R-8 Package Options
–600 –500 –400 –300 –200 –100 0100 200 300 400 500
UNITS
OUTPUT OFFSET VOLTAGE (µV)
0
22
20
18
16
14
12
10
8
6
4
2
00778-006
Figure 6. Typical Distribution of Output Offset Voltage,
+VS = 5 V, −VS = 0 V, VREF = +0.125 V, N-8 and R-8 Package Options
–0.245 –0.240 –0.235 –0.230 –0.225 –0.220 –0.215 –0.210
UNITS
INPUT OFFSET CURRENT (nA)
0
210
180
150
120
90
60
30
00778-007
Figure 7. Typical Distribution for Input Offset Current,
N-8 and R-8 Package Options
–0.025 –0.020 –0.015 –0.010 –0.005 00.005 0.010
UNITS
INPUT OFFSET CURRENT (nA)
0
20
18
16
14
12
10
8
6
4
2
00778-008
Figure 8. Typical Distribution for Input Offset Current,
+VS = 5 V, −VS = 0 V, VREF = +0.125 V, N-8 and R-8 Package Options
3, Ex 52>: Ema: 25$“; mmaz mu
AD623 Data Sheet
Rev. G | Page 12 of 32
75 130
125120
115110
10510095908580
UNITS
CMRR (dB)
0
1600
1400
1200
1000
800
600
400
200
00778-009
Figure 9. Typical Distribution for CMRR (G = 1)
1100k10k1k100
10
VOLTAGE NOISE SPECTRAL DENSITY (nV/ Hz RTI)
FREQUENCY (Hz)
10
1k
100
G= 1000
G= 100
G= 10
G = 1
00778-010
Figure 10. Voltage Noise Spectral Density vs. Frequency, N-8 Package Option
1k
100
10 1100k
VOLTAGE NOISE SPECTRAL DENSITY (nV/√Hz RTI)
FREQUENCY (Hz)
10 100 1k 10k
G = 1000
G = 100
G = 10
G = 1
00778-111
Figure 11. Voltage Noise Spectral Density vs. Frequency,
RM-8 and R-8 Package Options
420–2–4
I
BIAS
(nA)
COMMON-MODE VOLTAGE (V)
14
15
16
17
18
19
20
21
22
00778-011
Figure 12. Bias Current (IBIAS) vs. Common-Mode Voltage, N-8 Package
Option
16
11
12
13
14
15
–6 –4 –2 024
I
BIAS
(nA)
COMMON-MODE VOLTAGE (V)
00778-113
Figure 13. IBIAS vs. Common-Mode Voltage,
RM-8 and R-8 Package Options
–60 –40 –20 020 40 60 80 100 120 140
I
BIAS
(nA)
TEMPERATURE (°C)
0
5
10
15
20
25
30
00778-012
Figure 14. IBIAS vs. Temperature, N-8 Package Option
3.. 3.5:. Ema: 253% ms: waxfi
Data Sheet AD623
Rev. G | Page 13 of 32
–60 –40 –20 020 40 60 80 100 120 140
TEMPERATURE (°C)
16
10
11
12
13
14
15
I
BIAS
(nA)
00778-115
Figure 15. IBIAS vs. Temperature, RM-8 and R-8 Package Options
11k
100
10
CURRENT NOISE SPECTRAL DENSITY (fA/ Hz)
FREQUENCY (Hz)
10
1k
100
00778-013
Figure 16. Current Noise Spectral Density vs. Frequency, N-8 Package Option
110 100 1k
CURRENT NOISE SPECTRAL DENSITY (fA/√Hz)
1k
100
10
FREQUENCY (Hz)
00778-117
Figure 17. Current Noise Spectral Density vs. Frequency,
RM-8 and R-8 Package Options
–4 20 1–1–2–3
I
BIAS
(nA)
COMMON-MODE VOLTAGE (V)
16.0
16.5
17.0
17.5
18.0
18.5
19.0
19.5
20.0
00778-014
Figure 18. IBIAS vs. Common-Mode Voltage, VS = ±2.5 V, N-8 Package Option
19
18
16
17
14
15
13–4 –3 –2 –1 01 2
COMMON-MODE VOLTAGE (V)
I
BIAS
(nA)
00778-119
Figure 19. IBIAS vs. Common-Mode Voltage, VS = ±2.5 V,
RM-8 and R-8 Package Option
CH1 10mV A 1s 100mV VERT
00778-015
Figure 20. 0.1 Hz to 10 Hz Current Noise (0.71 pA/DIV), N-8 Package Option
AD623 Data Sheet
Rev. G | Page 14 of 32
2.0
–2.0
–1.0
0.5
1.5
0
–1.5
–0.5
1.0
024681357910
CURRENT NOISE (p
A
p-p)
TIME (Seconds)
00778-121
Figure 21. 0.1 Hz to 10 Hz Current Noise vs. Time,
RM-8 and R-8 Package Option
1µV/DIV 1s
00778-016
Figure 22. 0.1 Hz to 10 Hz RTI Voltage Noise (1 DIV = 1 μV p-p),
N-8 Package Option
4
–4
–2
1
3
0
–3
–1
2
024681357910
RTI VOLTAGE NOISE (µVp-p)
TIME (s)
G = 1
G = 1000
00778-123
Figure 23. RTI Voltage Noise, 0.1 Hz to 10 Hz vs. Time,
RM-8 and R-8 Package Options
120
30
40
50
60
70
80
90
100
110
1 10 100 1k 10k 100k
COMMON-MODE REJECTION (dB)
FREQUENCY (Hz)
G = ×1000
G = ×100
G = ×10
G = ×1
00778-017
Figure 24. Common-Mode Rejection vs. Frequency, +VS = 5 V, − VS = 0 V, VREF
= 2.5 V, for Various Gain Settings, N-8 Package Option
10 100 1k 10k 100k
COMMON-MODE REJECTION (dB)
FREQUENCY (Hz)
00778-125
120
110
100
90
80
70
60
50
40
30
20
10
0
G = 1000
G = 100
G = 10
G = 1
Figure 25. Common-Mode Rejection vs. Frequency, +VS = 5 V, − VS = 0 V, VREF
= 2.5 V, for Various Gain Settings, RM-8 and R-8 Package Options
120
30
40
50
60
70
80
90
100
110
1 10 100 1k 10k 100k
COMMON-MODE REJECTION (dB)
FREQUENCY (Hz)
G = ×1000
G = ×100
G = ×10
G = ×1
00778-018
Figure 26. Common-Mode Rejection vs. Frequency for Various Gain Settings,
N-8 Package Option
Data Sheet AD623
Rev. G | Page 15 of 32
10 100 1k 10k 100k
COMMON-MODE REJECTION (dB)
FREQUENCY (Hz)
00778-127
130
120
110
100
90
80
70
60
50
40
30
20
10
0
G = 1000
G = 100
G = 10
G = 1
Figure 27. Common-Mode Rejection vs. Frequency for Various Gain Settings,
RM-8 and R-8 Package Options
70
–30
–20
–10
0
10
20
30
40
50
60
100 1k 10k 100k 1M
GAIN (dB)
FREQUENCY (Hz)
G = 1000
G = 100
G = 10
G = 1
00778-019
Figure 28. Gain vs. Frequency (+VS = 5 V, −VS = 0 V), VREF = 2.5 V,
for Various Gain Settings, N-8 Package Option
70
–1010 100 1k 10k 100k 1M
GAIN (dB)
FREQUENCY (Hz)
0
10
20
30
40
50
60
G = 1000
G = 100
G = 10
G = 1
00778-129
Figure 29. Gain vs. Frequency (+VS = 5 V, −VS = 0 V), VREF = 2.5 V,
for Various Gain Settings, RM-8 and R-8 Package Options
5
–6
–5
–4
–3
–2
–1
0
1
2
3
4
–5–4–3–2–1012345
COMMON-MODE INPUT (V)
MAXIMUM OUTPUT VOLTAGE (V)
V
S
= ±2.5V
00778-020
Figure 30. Common-Mode Input vs. Maximum Output Voltage,
G = 1, RL = 100 kΩ for Two Supply Voltages, N-8 Package Option
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6–5 –4 –3 –2 –1 0 1 2 3 4 5
COMMON-MODE INPUT (V)
MAXIMUM OUTPUT VOLTAGE (V)
V
S
= ±2.5 V
00778-131
Figure 31. Common-Mode Input vs. Maximum Output Voltage,
G = 1, RL = 100 kΩ for Two Supply Voltages, RM-8 and R-8 Package Options
5
–6
–5
–4
–3
–2
–1
0
1
2
3
4
–5–4–3–2–1012345
COMMON-MODE INPUT (V)
MAXIMUM OUTPUT VOLTAGE (V)
00778-021
V
S
= ±2.5V
Figure 32. Common-Mode Input vs. Maximum Output Voltage,
G ≥ 10, RL = 100 kΩ, for Two Supply Voltages, N-8 Package Option
/ \ \ \ /
AD623 Data Sheet
Rev. G | Page 16 of 32
MAXIMUM OUTPUT VOLTAGE (V)
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
COMMON-MODE INPUT (V)
–6–5–4–3–2–101234 65
V
S
= ±2.5 V
00778-133
Figure 33. Common-Mode Input vs. Maximum Output Voltage,
G ≥ 10, RL = 100 kΩ, for Two Supply Voltages, RM-8 and R-8 Package Options
5
–1
0
1
2
3
4
012345
COMMON-MODE INPUT (V)
MAXIMUM OUTPUT VOLTAGE (V)
00778-022
Figure 34. Common-Mode Input. vs. Maximum Output Voltage,
G = 1, +VS = 5 V, −VS = 0 V, RL = 100 kΩ, N-8 Package Option
5
–1
0
2
4
1
3
012345
COMMON-MODE INPUT (V)
MAXIMUM OUTPUT VOLTAGE (V)
00778-135
Figure 35. Common-Mode Input vs. Maximum Output Voltage,
G = 1, +VS = 5 V, −VS = 0 V, RL = 100 kΩ, RM-8 and R-8 Package Options
5
–1
0
1
2
3
4
012345
COMMON-MODE INPUT (V)
MAXIMUM OUTPUT VOLTAGE (V)
00778-023
Figure 36. Common-Mode Input vs. Maximum Output Voltage,
G ≥ 10, +VS = 5 V, −VS = 0 V, RL = 100 kΩ, N-8 Package Option
5
–1
0
2
4
1
3
012345
COMMON-MODE INPUT (V)
MAXIMUM OUTPUT VOLTAGE (V)
00778-137
Figure 37. Common-Mode Input vs. Maximum Output Voltage,
G ≥ 10, +VS = 5 V, −VS = 0 V, RL = 100 kΩ, RM-8 and R-8 Package Options
140
120
100
80
60
40
20
01 10 100 1k 10k 100k
POSITIVE PSRR (dB)
FREQUENCY (Hz)
G = 1000
G = 100
G = 10
G = 1
00778-024
Figure 38. Positive Power Supply Rejection Ratio (PSRR) vs. Frequency, N-8
Package Option
/
Data Sheet AD623
Rev. G | Page 17 of 32
140
01 10 100 1k 10k 100k
POSITIVE PSRR (dB)
FREQUENCY (Hz)
20
40
60
80
100
120
G = 1000
G = 100
G = 10
G = 1
00778-139
Figure 39. Positive PSRR vs. Frequency, RM-8 and R-8 Package Options
140
120
100
80
60
40
20
01 10 100 1k 10k 100k
POSITIVE PSRR (dB)
FREQUENCY (Hz)
G = 1000
G = 100
G = 10
G = 1
00778-025
Figure 40. Positive PSRR vs. Frequency, +VS = 5V, −VS = 0 V,
for Various Gain Settings, N-8 Package Option
140
0
20
40
80
120
60
100
1 10 100 1k 10k 100k
POSITIVE PSRR (dB)
FREQUENCY (Hz)
G = 1000
G = 100
G = 10
G = 1
00778-141
Figure 41. Positive PSRR vs. Frequency, +VS = 5V, −VS = 0 V,
for Various Gain Settings, RM-8 and R-8 Package Options
140
120
100
80
60
40
20
01 10 100 1k 10k 100k
NEGATIVE PSRR (dB)
FREQUENCY (Hz)
G = 1000
G = 100
G = 10
G = 1
00778-026
Figure 42. Negative PSRR vs. Frequency for Various Gain Settings,
N-8 Package Option
160
0
40
20
60
100
140
80
120
NEGATIVE PSRR (dB)
1 10 100 1k 10k 100k
FREQUENCY (Hz)
G = 1000
G = 100
G = 10
G = 1
00778-143
Figure 43. Negative PSRR vs. Frequency for Various Gain Settings,
RM-8 and R-8 Package Options
10
8
6
4
2
0020
V
S
= ±5V
V
S
= ±2.5V
40 60 80 100
OUTPUT VOLTAGE (V p-p)
FREQUENCY (kHz)
00778-027
Figure 44. Large Signal Response, G ≤ 10 for Two Supply Voltages
AD623 Data Sheet
Rev. G | Page 18 of 32
1k
100
10
1110 100 1k
SETTLING TIME (µs)
GAIN (V/V)
00778-028
Figure 45. Settling Time to 0.01% vs. Gain, for a 5 V Step at Output,
CL = 100 pF
500µV 1V 20µs
00778-029
Figure 46. Large Signal Pulse Response and Settling Time,
G = −1 (0.250 mV = 0.01%), CL = 100 pF, N-8 Package Option
3
2
1
0
–1
–2
–3
–20 0180
OUTPUT VOLTAGE (V)
TIME (µs)
20 40 60 80 100 120 140 160
300
200
100
0
–100
–200
–300
ERROR VOLTAGE (mV)
00778-147
Figure 47. Large Signal Pulse Response and Settling Time,
G = −1 (0.250 mV = 0.01%), CL = 100 pF, RM-8 and R-8 Package Options
500µV 1V 10µs
00778-030
Figure 48. Large Signal Pulse Response and Settling Time,
G = −10 (0.250 mV = 0.01%), CL = 100 pF, N-8 Package Option
3
2
1
0
–1
–2
–3
–10 80
OUTPUT VOLTAGE (V)
TIME (µs)
300
200
100
0
–100
–200
–300
ERROR VOLTAGE (mV)
010 20 30 40 50 60 70
V
OUT
DELTA_mV
00778-149
Figure 49. Large Signal Pulse Response and Settling Time,
G = −10 (0.250 mV = 0.01%), CL = 100 pF, RM-8 and R-8 Package Options
10mV 2V 50µs
00778-031
Figure 50. Large Signal Pulse Response and Settling Time,
G = 100, CL = 100 pF, N-8 Package Option
Data Sheet AD623
Rev. G | Page 19 of 32
3
2
1
0
–1
–2
–3
–40 10 60 110 160 210 260 310 360
OUTPUT VOLTAGE (V)
TIME (µs)
300
200
100
0
–100
–200
–300
ERROR VOLTAGE (mV)
00778-151
Figure 51. Large Signal Pulse Response and Settling Time,
G = 100, CL = 100 pF, RM-8 and R-8 Package Options
20mV 2V 500µs
00778-032
Figure 52. Large Signal Pulse Response and Settling Time,
G = −1000 (5 mV = 0.01%), CL = 100 pF, N-8 Package Option
3
2
1
0
–1
–2
–3
–1.0 –0.5 3.0
OUTPUT VOLTAGE (V)
TIME (ms)
300
200
100
0
–100
–200
–300
ERROR VOLTAGE (mV)
00.5 1.0 1.5 2.0 2.5
00778-153
Figure 53. Large Signal Pulse Response and Settling Time,
G = −1000 (5 mV = 0.01%), CL = 100 pF, RM-8 and R-8 Package Options
20mV 2µs
00778-033
Figure 54. Small Signal Pulse Response, G = 1, RL = 10 kΩ, CL = 100 pF,
N-8 Package Option
120
–120 020
OUTPUT VOLTAGE (mV)
TIME (µs)
–100
–80
–60
–40
–20
0
20
40
60
80
100
246810 12 14 16 18
00778-155
Figure 55. Small Signal Pulse Response, G = 1, RL = 10 kΩ, CL = 100 pF,
RM-8 and R-8 Package Options
20mV 5µs
00778-034
Figure 56. Small Signal Pulse Response, G = 10, RL = 10 kΩ, CL = 100 pF,
N-8 Package Option
AD623 Data Sheet
Rev. G | Page 20 of 32
120
–20
–40
–60
–80
–100
–120 040
OUTPUT VOLTAGE (mV)
TIME (µs)
0
20
40
60
80
100
510 15 20 25 30 35
00778-157
Figure 57. Small Signal Pulse Response, G = 10, RL = 10 kΩ, CL = 100 pF,
RM-8 and R-8 Package Options
20mV 50µs
00778-035
Figure 58. Small Signal Pulse Response, G = 100, RL = 10 kΩ, CL = 100 pF,
N-8 Package Option
120
–20
–40
–60
–80
–100
–120 04.0
OUTPUT VOLTAGE (mV)
TIME (ms)
0
20
40
60
80
100
0.5 1.0 1.5 2.0 2.5 3.0 3.5
00778-159
Figure 59. Small Signal Pulse Response, G = 100, RL = 10 kΩ, CL = 100 pF,
RM-8 and R-8 Package Options
20mV 500µs
00778-036
Figure 60. Small Signal Pulse Response, G = 1000, RL = 10 kΩ, CL = 100 pF,
N-8 Package Option
120
–20
–40
–60
–80
–100
–120 04.0
OUTPUT VOLTAGE (mV)
TIME (ms)
0
20
40
60
80
100
0.5 1.0 1.5 2.0 2.5 3.0 3.5
00778-161
Figure 61. Small Signal Pulse Response, G = 1000, RL = 10 kΩ, CL = 100 pF,
RM-8 and R-8 Package Options
200µV
1V
00778-037
Figure 62. Gain Nonlinearity, G = −1 (50 ppm/DIV), N-8 Package Option
Data Sheet AD623
Rev. G | Page 21 of 32
5
–5
–10
–15
–20
–25
–30
–4.8 3.2
GAIN NONLINEARITY (ppm)
OUTPUT VOLTAGE (V)
0
–3.8 –2.8 –1.8 –0.8 0.2 1.2 2.2
00778-163
Figure 63. Gain Nonlinearity vs. Output Voltage, G = −1,
RM-8 and R-8 Package Options
20µV 1V
00778-038
Figure 64. Gain Nonlinearity, G = −10 (6 ppm/DIV), N-8 Package Option
6
2
0
–2
–4
–6
–4.8 4.23.2
GAIN NONLINEARITY (ppm)
OUTPUT VOLTAGE (V)
4
–3.8 –2.8 –1.8 –0.8 0.2 1.2 2.2
00778-165
Figure 65. Gain Nonlinearity vs. Output Voltage, G = −10,
RM-8 and R-8 Package Options
50µV 1V
00778-039
Figure 66. Gain Nonlinearity, G = −100, 15 ppm/DIV, N-8 Package Option
AD623 Data Sheet
Rev. G | Page 22 of 32
70
20
0
–10
–20
–30
–4.8 4.23.2
GAIN NONLINEARITY (ppm)
OUTPUT VOLTAGE (V)
30
40
50
60
–3.8 –2.8 –1.8 –0.8 0.2 1.2 2.2
00778-167
Figure 67. Gain Nonlinearity vs. Output Voltage, G = −100,
RM-8 and R-8 Package Options
V+
(V+) –0.5
(V+) –1.5
(V+) –2.5
(V–) +0.5
V– 00.5 1.0 1.5 2.0
OUTPUT VOLTAGE SWING (V)
OUTPUT CURRENT (mA)
00778-040
Figure 68. Output Voltage Swing vs. Output Current, N-8 Package Option
5
4
3
2
1
00 2 3 5 7 8 961 4 10 11
POSITIVE OUTPUT VOLTAGE SWING (V)
OUTPUT CURRENT (mA)
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
NEGATIVE OUTPUT VOLTAGE SWING (V)
SWING FROM –V
S
SWING FROM +V
S
00778-169
Figure 69. Positive and Negative Output Voltage Swing vs. Output Current,
RM-8 and R-8 Package Options
*3 “9%
Data Sheet AD623
Rev. G | Page 23 of 32
THEORY OF OPERATION
The AD623 is an instrumentation amplifier based on a modified
classic 3-op-amp approach to ensure single- or dual-supply
operation even at common-mode voltages at the negative supply
rail. Low voltage offsets (input and output), absolute gain
accuracy, and one external resistor to set the gain make the
AD623 a versatile instrumentation amplifier.
The input signal is applied to positive-negative-positive (PNP)
transistors acting as voltage buffers and providing a common-
mode signal to the input amplifiers (see Figure 70). An absolute
value 50 kΩ resistor in each amplifier feedback ensures gain
programmability.
The differential output is
C
G
O
V
R
V
+
=kΩ100
1
The differential voltage is then converted to a single-ended
voltage using the output amplifier, which also rejects any
common-mode signal at the output of the input amplifiers.
Because the amplifiers can swing to either supply rail, as well as
have their common-mode range extended to below the negative
supply rail, the range over which the AD623 can operate is further
enhanced (see Figure 30, Figure 31, Figure 32, and Figure 33).
The output voltage at Pin 6 (OUTPUT) is measured with
respect to the potential at Pin 5 (REF). The impedance of the REF
pin is 100 kΩ. Therefore, in applications requiring voltage
conversion, a small resistor between Pin 5 (REF) and Pin 6
(OUTPUT) is all that is needed.
+V
S
+V
S
–V
S
7
4
–IN
+IN
2
3
7
–V
S
4
50kΩ 50kΩ 50kΩ
50kΩ 50kΩ 50kΩ
OUTPUT
REF
6
5
8
1
R
G
–R
G
+R
G
00778-041
Figure 70. Simplified Schematic
Because of the voltage feedback topology of the internal op
amps, the bandwidth of the instrumentation amplifier decreases
with increasing gain. At unity gain, the output amplifier limits
the bandwidth.
AD623 Data Sheet
Rev. G | Page 24 of 32
APPLICATIONS INFORMATION
BASIC CONNECTION
Figure 71 and Figure 72 show the basic connection circuits for
the AD623. The +VS and −VS terminals are connected to the
power supply. The supply can be either bipolar (VS = ±2.5 V to
±6 V) or single supply (−VS = 0 V, + VS = 2.7 V to 12 V).
Capacitively decouple power supplies close to the power pins of
the device. For optimal results, use surface-mount 0.1 µF ceramic
chip capacitors and 10 µF electrolytic tantalum capacitors.
00778-042
R
G
R
G
V
IN
OUTPUT V
OUT
REF
R
G
REF (INPUT)
+2.5V TO +6V
+V
S
10µF
0.1µF
–2.5V TO –6V
–V
S
10µF
0.1µF
Figure 71. Dual-Supply Basic Connection
00778-055
R
G
R
G
V
IN
OUTPUT V
OUT
REF
R
G
REF (INPUT)
+3V TO +12V
+V
S
10µF
0.1µF
Figure 72. Single-Supply Basic Connection
The input voltage, which can be either single-ended (tie either
−IN or +IN to ground) or differential, is amplified by the
programmed gain. The output signal appears as the voltage
difference between the OUTPUT pin and the externally applied
voltage on the REF input. For a ground referenced output,
ground REF.
GAIN SELECTION
The gain of the AD623 is programmed by the RG resistor, or
more precisely, by whatever impedance appears between Pin 1
and Pin 8. The AD623 offers accurate gains using 0.1% to 1%
tolerance resistors. Table 7 shows the required values of RG for
the various gains. Note that for G = 1, the RG terminals are
unconnected (RG = ∞). For any arbitrary gain, RG can be
calculated by
RG = 100 kΩ/(G − 1)
Table 7. Required Values of Gain Resistors
Desired
Gain
1% Standard Table
Value of RG
Calculated Gain Using
1% Resistors
2 100 kΩ 2
5 24.9 kΩ 5.02
10 11 kΩ 10.09
20 5.23 kΩ 20.12
33 3.09 kΩ 33.36
40
2.55 kΩ
40.21
50 2.05 kΩ 49.78
65 1.58 kΩ 64.29
100 1.02 kΩ 99.04
200 499 Ω 201.4
500 200 Ω 501
1000 100 Ω 1001
REFERENCE TERMINAL
The reference terminal potential defines the zero output voltage
and is especially useful when the load does not share a precise
ground with the rest of the system. The reference terminal
provides a direct means of injecting a precise offset to the
output. The reference terminal is also useful when bipolar
signals are being amplified because the terminal can provide a
virtual ground voltage. The voltage on the reference terminal
can vary from −VS to +VS.
INPUT AND OUTPUT OFFSET VOLTAGE ERROR
The offset voltage (VOS) of the AD623 is attributed to two
sources: those originating in the two input stages where the
instrumentation amplifier gain is established, and those
originating in the subtractor output stage. The output error is
divided by the programmed gain when referred to the input. In
practice, the input errors dominate at high gain settings,
whereas the output error prevails when the gain is set at or near
unity.
Calculate the VOS error for any given gain as follows:
Total Error Referred to Input (RTI)
= Input Error + (Output Error/G)
Total Error Referred to Output (RTO)
= (Input Error × G) + Output Error
The RTI offset errors and noise voltages for different gains are
listed in Table 8.
Data Sheet AD623
Rev. G | Page 25 of 32
INPUT PROTECTION
Internal supply referenced clamping diodes allow the input,
reference, output, and gain terminals of the AD623 to safely
withstand overvoltages of 0.3 V above or below the supplies.
This overvoltage protection is true at all gain settings and when
cycling power on and off. Overvoltage protection is particularly
important because the signal source and amplifier can be
powered separately.
If the overvoltage exceeds this value, limit the current through
these diodes to about 10 mA using external current-limiting
resistors (see Figure 73). The size of this resistor is defined by
the supply voltage and the required overvoltage protection.
R
G
V
OVER
V
OVER
AD623
OUTPUT
+V
S
–V
S
R
LIM
R
LIM
I = 10mA MAX
R
LIM
= V
OVER
–V
S
+ 0.7V
10mA
00778-043
Figure 73. Input Protection
RF INTERFERENCE
All instrumentation amplifiers can rectify high frequency out-
of-band signals. When rectified, these signals appear as dc
offset errors at the output. The circuit in Figure 74 provides RFI
suppression without reducing performance within the pass band of
the instrumentation amplifier. Resistor 1 (R1) and Capacitor 1
(C1), and likewise, Resistor 2 (R2) and Capacitor 2 (C2), form a
low-pass resistor capacitor (RC) filter that has a −3 dB bandwidth
equal to f = 1/(2 π R1C1). Using the component values shown in
Figure 74, this filter has a −3 dB bandwidth of approximately 40
kHz. The R1 and R2 resistors were chosen to be large enough to
isolate the input of the circuit from the capacitors but not large
enough to significantly increase the noise of the circuit. To
preserve common-mode rejection in the pass band of the
amplifier, the C1 and C2 capacitors must be ±5% tolerance, or
low cost 20% capacitors can be tested and binned to provide
closely matched devices.
00778-044
R
G
–IN
+IN
AD623 V
OUT
R1
4.02kΩ
1%
R2
4.02kΩ
1% REFERENCE
+V
S
0.01µF
0.33µF
+V
S
0.01µF0.33µF
C1
1000pF
5%
C3
0.047µF
C2
1000pF
5%
NOTES:
1. LOCATE C1 TO C3 AS CLOSE TO THE INPUT PINS AS POSSIBLE.
Figure 74. Circuit to Attenuate RF Interference
C3 is needed to maintain common-mode rejection at low
frequencies. R1 and R2, as well as C1 and C2, form a bridge
circuit whose output appears across the input pins of the
instrumentation amplifier. Any mismatch between C1 and C2
unbalances the bridge and reduces the common-mode
rejection. C3 ensures that any RF signals are common-mode
(the same on both instrumentation amplifier inputs) and are
not applied differentially. This second low-pass network, R1 + R2
and C3, has a −3 dB frequency equal to 1/(2π(R1 + R2)(C3)).
Using a C3 value of 0.047 µF, t he −3 dB signal bandwidth of this
circuit is approximately 400 Hz. The typical dc offset shift over
frequency is less than 1.5 µV, and the RF signal rejection of the
circuit is greater than 71 dB. The 3 dB signal bandwidth of this
circuit can be increased to 900 Hz by reducing R1 and R2 to
2.2 kΩ. The performance is similar to using 4 kΩ resistors,
except that the circuitry preceding the instrumentation amplifier
must drive a lower impedance load.
Table 8. RTI Error Sources
Maximum Total Input Offset Error (µV) Maximum Total Input Offset Drift (µV/°C) Total Input Referred Noise (nV/√Hz)
Gain
AD623ANZ,
AD623ARZ
AD623BNZ,
AD623BRZ
AD623ANZ,
AD623ARZ
AD623BNZ,
AD623BRZ
AD623ANZ,
AD623ARZ
AD623BNZ,
AD623BRZ
1 1200 600 12 11 62 62
2 700 350 7 6 45 45
5 400 200 4 3 38 38
10 300 150 3 2 35 35
20
250
125
2.5
1.5
35
35
50 220 110 2.2 1.2 35 35
100 210 105 2.1 1.1 35 35
1000 200 100 2 1 35 35
AD623 Data Sheet
Rev. G | Page 26 of 32
The circuit in Figure 74 must be built using a printed circuit
board (PCB) with a ground plane on both sides. All component
leads must be as short as possible. The R1 and R2 resistors can
be common 1% metal film units. However, the C1 and C2
capacitors must be ±5% tolerance devices to avoid degrading
the common-mode rejection of the circuit. Either the traditional
5% silver mica units or Panasonic ±2% polyphenylene sulfide (PPS)
film capacitors are recommended.
In many applications, shielded cables minimize noise. For
optimal CMR over frequency, the shield must be properly driven.
Figure 75 shows an active guard driver that is configured to
improve ac common-mode rejection by bootstrapping the
capacitances of input cable shields, thus minimizing the
capacitance mismatch between the inputs.
AD623
OUTPUT
REF
+V
S
–V
S
2
1
8
3
6
5
7
4
R
G
2
R
G
2
AD8031
100Ω
00778-045
–IN
+IN
Figure 75. Common-Mode Shield Driver
GROUNDING
Because the AD623 output voltage is developed with respect
to the potential on the reference terminal, many grounding
problems can be solved by simply tying the REF pin to the
appropriate local ground. Tie the REF pin to a low impedance
point for optimal CMR.
The use of ground planes is recommended to minimize the
impedance of ground returns (and therefore the size of dc
errors). To isolate low level analog signals from a noisy digital
environment, many data acquisition components have separate
analog and digital ground returns (see Figure 76). All ground
pins from mixed signal components, such as analog-to-digital
converters (ADCs), must be returned through the high quality
analog ground plane. Maximum isolation between analog and
digital is achieved by connecting the ground planes back at the
supplies. The digital return currents from the ADC that flow in
the analog ground plane, in general, have a negligible effect on
noise performance.
If there is only a single power supply available, it must be shared
by both digital and analog circuitry. Figure 77 shows how to
minimize interference between the digital and analog circuitry.
As in the previous case, use separate analog and digital ground
planes (reasonably thick traces can be used as an alternative to a
digital ground plane). Connect these ground planes at the ground
pin of the power supply. Run separate traces from the power
supply to the supply pins of the digital and analog circuits. Ideally,
each device has its own power supply trace, but these can be
shared by a number of devices, as long as a single trace is not used
to route current to both digital and analog circuitry.
AGND V
DD
MICROPROCESSOR
AD623
2
3
6
5
7
4
ANALOG POWER SUPPLY
GND–5V+5V
DIGITAL POWER SUPPLY
+5VGND
4
V
IN1
1
V
DD
6
AGND
14
DGND
3
V
IN2
ADC
AD7892-2
0.1µF
0.1µF0.1µF 0.1µF
12
00778-046
Figure 76. Optimal Grounding Practice for a Bipolar Supply Environment with Separate Analog and Digital Supplies
V
DD
AGND
MICROPROCESSOR
AD623
2
3
6
5
7
4
4
V
IN1
1
V
DD
6
AGND
14
DGND
ADC
AD7892-2
0.1µF
0.1µF 0.1µF
12
POWER SUPPLY
+5V GND
00778-047
Figure 77. Optimal Ground Practice in a Single-Supply Environment
Data Sheet AD623
Rev. G | Page 27 of 32
Ground Returns for Input Bias Currents
Input bias currents are dc currents that must flow to bias the
input transistors of an amplifier, which are usually transistor
base currents. When amplifying floating input sources, such as
transformers or ac-coupled sources, there must be a direct dc
path into each input so that the bias current can flow. Figure 78,
Figure 79, and Figure 80 show how a bias current path can be
provided for transformer coupling, thermocouple, and
capacitive ac coupling. In dc-coupled resistive bridge
applications, providing this path is generally not necessary
because the bias current simply flows from the bridge supply
through the bridge into the amplifier. However, if the impedances
that the two inputs see are large and differ by a large amount
(>10 kΩ), the offset current of the input stage causes dc errors
proportional with the input offset voltage of the amplifier.
AD623
OUTPUT
TO POWER
SUPPLY
GROUND
REF
LOAD
+V
S
–V
S
2
1
8
3
6
5
7
4
R
G
–IN
+IN
00778-048
Figure 78. Ground Returns for Bias Currents with Transformer-Coupled
Inputs
AD623
OUTPUT
TO POWER
SUPPLY
GROUND
REF
LOAD
+V
S
–V
S
2
1
8
3
6
5
7
4
R
G
–IN
+IN
00778-049
Figure 79. Ground Returns for Bias Currents with Thermocouple Inputs
AD623
OUTPUT
TO POWER
SUPPLY
GROUND
REF
LOAD
+V
S
–V
S
2
1
8
3
6
5
7
4
R
G
–IN
+IN
100kΩ 100kΩ
00778-050
Figure 80. Ground Returns for Bias Currents with AC-Coupled Inputs
Output Buffering
The AD623 is designed to drive loads of 10 kΩ or greater. If the
load is less than this value, the output of the AD623 must be
buffered with a precision single-supply op amp, such as the
OP113. This op amp can swing from 0 V to 4 V on its output
while driving a load as small as 600 Ω (see Figure 81). Table 9
summarizes the performance of some buffer op amps.
5V
0.1µF 5V
0.1µF
AD623
OP113
R
G
V
IN
REFERENCE V
OUT
00778-051
Figure 81. Output Buffering
Table 9. Buffering Options
Op Amp Description
OP113 Single-supply, high output current
OP191 Rail-to-rail input and output, low supply current
Amplifying Signals with Low Common-Mode Voltage
Because the common-mode input range of the AD623 extends
0.1 V below ground, it is possible to measure small differential
signals that have low or no common-mode component. Figure 82
shows a thermocouple application where one side of the J-type
thermocouple is grounded.
5V
0.1µF
AD623
R
G
1.02kΩ
REF
J-TYPE
THERMOCOUPLE OUTPUT
2V
00778-053
Figure 82. Amplifying Bipolar Signals with Low Common-Mode Voltage
Over a temperature range of −200°C to +200°C, the J-type thermo-
couple delivers a voltage ranging from −7.890 mV to +10.777 m V.
A programmed gain on the AD623 of 100 (RG = 1.02 kΩ) and a
voltage on the REF pin of 2 V result in the output voltage ranging
from 1.110 V to 3.077 V relative to ground.
rrrrr
AD623 Data Sheet
Rev. G | Page 28 of 32
INPUT DIFFERENTIAL AND COMMON-MODE
RANGE vs. SUPPLY AND GAIN
Figure 83 shows a simplified block diagram of the AD623. The
voltages at the outputs of Amplifier 1 (A1) and Amplifier 2 (A2)
are given by
VA2 = VCM + VDIFF/2 + 0.6 V + VDIFF × RF/RG
= VCM + 0.6 V + VDIFF × Gain/2
VA1 = VCM − VDIFF/2 + 0.6 V + VDIFF × RF/RG
= VCM + 0.6 V − VDIFF × Gain/2
+V
S
7
4
–V
S
+V
S
7
4
–V
S
2
3
–IN
+IN
R
F
50kΩ 50kΩ 50kΩ
R
F
50kΩ 50kΩ 50kΩ
OUTPUT
REF
6
5
8
1
GAIN
R
G
A1
A2
A3
V
DIFF
2
–
+
V
DIFF
2
–
+
V
CM
00778-055
Figure 83. Simplified Block Diagram
The voltages on these internal nodes are critical in determining
whether the output voltage is clipped. The VA1 and VA2 voltages
can swing from approximately 10 mV above the negative supply
(−VS or ground) to within approximately 100 mV of the positive
rail before clipping occurs. Based on this, and from the previous
equations, the maximum and minimum input common-mode
voltages are given by the following equations:
VCMMAX = +VS − 0.7 V − VDIFF × Gain/2
VCMMIN = −VS − 0.590 V + VDIFF × Gain/2
These equations can be rearranged to give the maximum possible
differential voltage (positive or negative) for a particular common-
mode voltage, gain, and power supply. Because the signals on
A1 and A2 can clip on either rail, the maximum differential
voltage is the lesser of the two equations.
|VDIFFMAX| = 2 (+VS − 0.7 V − VCM)/Gain
|VDIFFMAX| = 2 (VCM − −VS + 0.590 V)/Gain
However, the range on the differential input voltage range is
also constrained by the output swing. Therefore, the range of
VDIFF may need to be lower according to the following equation:
Input Range ≤ Available Output Swing/Gain
For a bipolar input voltage with a common-mode voltage that is
roughly half way between the rails, VDIFFMAX is half the value that
the previous equations yield because the REF pin is at midsupply.
Note that the available output swing is given for different supply
conditions in the Specifications section.
The equations can be rearranged to result in the maximum gain
for a fixed set of input conditions. The maximum gain is the
lesser of the two equations.
GainMAX = 2 (+VS − 0.7 V − VCM)/VDIFF
GainMAX = 2 (VCM − −VS + 0.590 V)/VDIFF
Again, it is recommended that the resulting gain multiplied by
the input range is less than the available output swing. If this is
not the case, the maximum gain is given by
GainMAX = Available Output Swing/Input Range
Also, for bipolar inputs (that is, input range = 2 VDIFF), the
maximum gain is half the value yielded by the previous equations
because the REF pin must be at midsupply.
The maximum gain and resulting output swing for different input
conditions is shown in Table 10. Output voltages are referenced
to the voltage on the REF pin.
For the purposes of computation, it is necessary to break down the
input voltage into its differential and common-mode components.
Therefore, when one of the inputs is grounded or at a fixed
voltage, the common-mode voltage changes as the differential
voltage changes. An example of this is the thermocouple
amplifier in Figure 82. The inverting input on the AD623 is
grounded. Therefore, when the input voltage is −10 mV, the
voltage on the noninverting input is −10 mV. For the purpose of
the signal swing calculations, this input voltage must be
composed of a common-mode voltage of −5 mV (that is, (+IN
+ −IN)/2) and a differential input voltage of −10 mV (that is,
+IN − −IN).
Data Sheet AD623
Rev. G | Page 29 of 32
Table 10. Maximum Attainable Gain and Resulting Output Swing for Different Input Conditions
VCM (V)
Differential
Voltage (VDIFF) REF Pin (V) Supply Voltages (V) Maximum Gain
Closest 1%
Gain Resistor Resulting Gain Output Swing (V)
0 ±10 mV 2.5 +5 118 866 Ω 116 ±1.2
0 ±100 mV 2.5 +5 11.8 9.31 kΩ 11.7 ±1.1
0 ±10 mV 0 ±5 490 205 Ω 488 ±4.8
0 ±100 mV 0 ±5 49 2.1 kΩ 48.61 ±4.8
0 ±1 V 0 ±5 4.9 26.1 kΩ 4.83 ±4.8
2.5 ±10 mV 2.5 +5 242 422 Ω 238 ±2.3
2.5 ±100 mV 2.5 +5 24.2 4.32 kΩ 24.1 ±2.4
2.5 ±1 V 2.5 +5 2.42 71.5 kΩ 2.4 ±2.4
1.5 ±10 mV 1.5 +3 142 715 Ω 141 ±1.4
1.5 ±100 mV 1.5 +3 14.2 7.68 kΩ 14 ±1.4
0 ±10 mV 1.5 +3 118 866 Ω 116 ±1.1
0 ±100 mV 1.5 +3 11.8 9.31 kΩ 11.74 ±1.1
ADDITIONAL INFORMATION
For an updated design of the AD623, see the AD8223.
For a selection guide to all Analog Devices instrumentation
amplifiers, see the Instrumentation Amplifiers page on the
Analog Devices website at www.analog.com/inamps.
For additional information on instrumentation amplifiers, refer
to the following:
MT-061, Instrumentation Amplifier (In-Amp) Basics
MT-070, In-Amp Input RFI Protection
A Designer's Guide to Instrumentation Amplifiers, Counts,
Lew and Charles Kitchen
AD623 Data Sheet
Rev. G | Page 30 of 32
EVALUATION BOARD
GENERAL DESCRIPTION
The EVAL-INAMP-62RZ can be used to evaluate the AD620,
AD621, AD622, AD623, AD627, AD8223, and AD8225
instrumentation amplifiers. In addition to the basic in-amp
connection, circuit options enable the user to adjust the offset
voltage, apply an output reference, or provide shield drivers
with user supplied components. The board is shipped with an
assortment of instrumentation amplifier ICs in the legacy SOIC
pinout, such as the AD620, AD621, AD622, AD623, AD8223,
and AD8225. The board also has an alternative footprint for a
through-hole, 8-le ad P DI P.
Figure 84 shows a photograph of the evaluation boards for all
Analog Devices instrumentation amplifiers. For additional
information, see the EVAL-INAMP user guide (UG-261).
00778-056
Figure 84. Evaluation Boards for Analog Devices In-Amps
Eééél
Data Sheet AD623
Rev. G | Page 31 of 32
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
070606-A
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
SEATING
PLANE
0.015
(0.38)
MIN
0.210 (5.33)
MAX
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
8
14
5
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.100 (2.54)
BSC
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.005 (0.13)
MIN
Figure 85. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body (N-8)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8 5
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 86. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
ANALOG DEVICES www.3nalog.cnm
AD623 Data Sheet
Rev. G | Page 32 of 32
COMPLIANT TO JEDEC STANDARDS MO-187-AA
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
10-07-2009-B
Figure 87. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature
Range Package Description
Package
Option
Marking
Code
AD623ANZ −40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8
AD623ARZ −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD623ARZ-R7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel R-8
AD623ARZ-RL −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel R-8
AD623ARMZ
−40°C to +85°C
8-Lead Mini Small Outline Package [MSOP]
RM-8
J0A
AD623ARMZ-REEL −40°C to +85°C 8-Lead Mini Small Outline Package [MSOP], 13" Tape and Reel RM-8 J0A
AD623ARMZ-REEL7 −40°C to +85°C 8-Lead Mini Small Outline Package [MSOP], 7" Tape and Reel RM-8 J0A
AD623BNZ −40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8
AD623BRZ −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD623BRZ-R7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel R-8
AD623BRZ-RL −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel R-8
EVAL-INAMP-62RZ Evaluation Board
1 Z = RoHS Compliant Part.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00778-9/20(G)