Texas Instruments 的 SN65/75HVD10-12(Q) 規格書

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SNx5HVD1x 3.3-V RS-485 Transceivers

1 Features

• Operates with a 3.3-V supply

• Bus-pin ESD protection exceeds 16-kV HBM

• 1/8 Unit-load option available (up to 256 nodes on

the bus)

• Optional driver output transition times for signaling

rates 1of 1 Mbps, 10 Mbps, and

32 Mbps

• Meets or exceeds the requirements of ANSI TIA/

EIA-485-A

• Bus-pin short-circuit protection from –7 V to

12 V

• Low-current standby mode: 1 µA, typical

• Open-circuit, idle-bus, and shorted-bus fail-safe

receiver

• Thermal shutdown protection

• Glitch-free power-up and power-down protection

for hot-plugging applications

• SN75176 footprint

2 Applications

• Digital motor control

•Utility meters

• Chassis-to-chassis interconnects

• Electronic security stations

• Industrial process control

•Building automation

•Point-of-sale (POS) terminals and networks

3 Description

The SN65HVD10, SN75HVD10, SN65HVD11,

SN75HVD11, SN65HVD12, and SN75HVD12 bus

transceivers all combine a 3-state differential line

driver, as well as a differential input line receiver

that operates with a single 3.3-V power supply. They

are designed for balanced transmission lines and

meet or exceed ANSI standard TIA/EIA-485-A and

ISO 8482:1993. These differential bus transceivers

are monolithic integrated circuits, designed for

bidirectional data communication on multipoint bus-

transmission lines. The drivers and receivers have

active-high and active-low enables, that can be

externally connected together to function as direction

control. Very low device standby supply current, can

be achieved by disabling the driver and the receiver.

The driver differential outputs and receiver differential

inputs connect internally to form a differential input/

output (I/O) bus port, that is designed to offer

minimum loading to the bus whenever the driver is

disabled or VCC = 0. These parts feature wide positive

and negative common-mode voltage ranges, making

them suitable for party-line applications.

Device Information

PART NUMBER PACKAGE(1) BODY SIZE (NOM)

SN65HVD10

SOIC (8) 4.90 mm × 3.91 mm

SN65HVD11

SN65HVD12

SN75HVD10

PDIP (8) 9.81 mm × 6.35 mm

SN75HVD11

SN75HVD12

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

RTRT

A B

R RE DE D

A B

R RE DE D

Typical Application Diagram

1The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).

SN65HVD10, SN65HVD11, SN65HVD12

SN75HVD10, SN75HVD11, SN75HVD12

SLLS505P – FEBRUARY 2002 – REVISED FEBRUARY 2022

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

I TEXAS INSTRUMENTS

Table of Contents

1 Features............................................................................1

2 Applications..................................................................... 1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................3

7 Specifications.................................................................. 4

7.1 Absolute Maximum Ratings........................................ 4

7.2 ESD Ratings............................................................... 4

7.3 Recommended Operating Conditions.........................4

7.4 Thermal Information....................................................5

7.5 Driver Electrical Characteristics.................................. 5

7.6 Receiver Electrical Characteristics............................. 6

7.7 Power Dissipation Characteristics.............................. 6

7.8 Driver Switching Characteristics................................. 7

7.9 Receiver Switching Characteristics.............................8

7.10 Dissipation Ratings................................................... 8

7.11 Typical Characteristics.............................................. 9

8 Parameter Measurement Information.......................... 11

9 Detailed Description......................................................17

9.1 Overview................................................................... 17

9.2 Functional Block Diagram......................................... 17

9.3 Feature Description...................................................17

9.4 Device Functional Modes..........................................17

10 Application and Implementation................................ 19

10.1 Application Information........................................... 19

10.2 Typical Application.................................................. 20

11 Power Supply Recommendations..............................23

12 Layout...........................................................................23

12.1 Layout Guidelines................................................... 23

12.2 Layout Example...................................................... 24

12.3 Thermal Considerations..........................................24

13 Device and Documentation Support..........................26

13.1 Device Support....................................................... 26

13.2 Related Links.......................................................... 26

13.3 Receiving Notification of Documentation Updates..26

13.4 Support Resources................................................. 26

13.5 Trademarks.............................................................26

13.6 Electrostatic Discharge Caution..............................26

13.7 Glossary..................................................................26

14 Mechanical, Packaging, and Orderable

Information.................................................................... 26

4 Revision History

Changes from Revision O (February 2017) to Revision P (February 2022) Page

• Changed the Thermal Information table............................................................................................................. 5

Changes from Revision N (July 2015) to Revision O (February 2017) Page

• Added MIN value of –55°C to the Storage temperature in Absolute Maximum Ratings ....................................4

Changes from Revision M (July 2013) to Revision N (July 2015) Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device

Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout

section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information

section ............................................................................................................................................................... 1

Changes from Revision L (July 2013) to Revision M (July 2013) Page

• Changed the VIT+ TYP value From: –0.65 V To: –0.065 V ................................................................................ 6

Changes from Revision K (September 2011) to Revision L (July 2013) Page

• Added TYP = –0.65 V to VIT+ .............................................................................................................................6

• Added TYP = –0.1 V to VIT– ...............................................................................................................................6

Changes from Revision J (February 2009) to Revision K (September 2011) Page

• Added new section 'LOW-POWER STANDBY MODE', in the Application Information section........................18

SN65HVD10, SN65HVD11, SN65HVD12

SN75HVD10, SN75HVD11, SN75HVD12

SLLS505P – FEBRUARY 2002 – REVISED FEBRUARY 2022 www.ti.com

Product Folder Links: SN65HVD10 SN65HVD11 SN65HVD12 SN75HVD10 SN75HVD11 SN75HVD12

I TEXAS INSTRUMENTS HHHH HHHH

5 Device Comparison Table

PART NUMBER SIGNALING RATE UNIT LOADS TASOIC MARKING

SOIC(1) PDIP

SN65HVD10D SN65HVD10P 32 Mbps 1/2

–40°C to 85°C

VP10

SN65HVD11D SN65HVD11P 10 Mbps 1/8 VP11

SN65HVD12D SN65HVD12P 1 Mbps 1/8 VP12

SN75HVD10D SN75HVD10P 32 Mbps 1/2

–0°C to 70°C

VN10

SN75HVD11D SN75HVD11P 10 Mbps 1/8 VN11

SN75HVD12D SN75HVD12P 1 Mbps 1/8 VN12

SN65HVD10QD SN65HVD10QP 32 Mbps 1/2 –40°C to 125°C VP10Q

SN65HVD11QD SN65HVD11QP 10 Mbps 1/8 VP11Q

(1) The D package is available as a tape and reel. Add an R suffix to the part number (that is, SN75HVD11DR) for this option.

6 Pin Configuration and Functions

VCC

GND

Figure 6-1. D, JD, or HKJ Package

8-Pin SOIC or PDIP

(Top View)

Table 6-1. Pin Functions

PIN TYPE DESCRIPTION

NAME NO.

A 6 Bus input/output Driver output or receiver input (complementary to B)

B 7 Bus input/output Driver output or receiver input (complementary to A)

D 4 Digital input Driver data input

DE 3 Digital input Active-high driver enable

GND 5 Reference potential Local device ground

R 1 Digital output Receive data output

RE 2 Digital input Active-low receiver enable

VCC 8 Supply 3-V to 3.6-V supply

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SN65HVD10, SN65HVD11, SN65HVD12

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SLLS505P – FEBRUARY 2002 – REVISED FEBRUARY 2022

Product Folder Links: SN65HVD10 SN65HVD11 SN65HVD12 SN75HVD10 SN75HVD11 SN75HVD12

TEXAS INSTRUMENTS

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range unless otherwise noted (1) (2)

MIN MAX UNIT

VCC Supply voltage –0.3 6 V

Voltage at A or B –9 14 V

Input voltage at D, DE, R, or RE –0.5 VCC + 0.5 V

Voltage input, transient pulse, A and B, through 100 Ω, see Figure 8-12 –50 50 V

IOReceiver output current –11 11 mA

Continuous total power dissipation See Section 7.10

TJJunction temperature 170 °C

Tstg Storage temperature –55 145 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Section 7.3 is not implied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.

7.2 ESD Ratings

VALUE UNIT

V(ESD)

Electrostatic

discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) Pins 5, 6, and 7 ±16000

All pins ±4000

Charged device model (CDM), per JEDEC specification

JESD22-C101(2) All pins ±1000

Electrical fast transient/burst(3) Pins 5, 6, and 7 ±4000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(3) Tested in accordance with IEC 61000-4-4.

7.3 Recommended Operating Conditions

over operating free-air temperature range unless otherwise noted

MIN NOM MAX UNIT

VCC Supply voltage 3 3.6

VI or VIC Voltage at any bus terminal (separately or common mode) –7(1) 12

VIH High-level input voltage D, DE, RE 2 VCC

VIL Low-level input voltage D, DE, RE 0 0.8

VID Differential input voltage See Figure 8-8 –12 12

IOH High-level output current Driver –60 mA

Receiver –8

IOL Low-level output current Driver 60 mA

Receiver 8

RLDifferential load resistance 54 60 Ω

CLDifferential load capacitance 50 pF

Signaling rate

HVD10 32

MbpsHVD11 10

HVD12 1

TJ (2) Junction temperature 145 °C

(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.

(2) See thermal characteristics table for information regarding this specification.

SN65HVD10, SN65HVD11, SN65HVD12

SN75HVD10, SN75HVD11, SN75HVD12

SLLS505P – FEBRUARY 2002 – REVISED FEBRUARY 2022 www.ti.com

Product Folder Links: SN65HVD10 SN65HVD11 SN65HVD12 SN75HVD10 SN75HVD11 SN75HVD12

TEXAS INSTRUMENTS

7.4 Thermal Information

THERMAL METRIC(1)

SNx5HVD1xx

UNITD (SOIC) P (PDIP)

8 Pins 8 Pins

RθJA Junction-to-ambient thermal resistance 116.7 84.3 °C/W

Rθ

JC(top)

Junction-to-case (top) thermal resistance 56.3 65.4 °C/W

RθJB Junction-to-board thermal resistance 63.4 62.1 °C/W

ψJT Junction-to-top characterization parameter 8.8 31.3 °C/W

ψJB Junction-to-board characterization parameter 62.6 60.4 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Driver Electrical Characteristics

Over recommended operating conditions unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT

VIK Input clamp voltage II = –18 mA –1.5 V

|VOD| Differential output voltage(2)

IO = 0 2 VCC

VRL = 54 Ω, See Figure 8-1 1.5

Vtest = –7 V to 12 V, See Figure 8-2 1.5

Δ|VOD|Change in magnitude of differential output

voltage See Figure 8-1 and Figure 8-2 –0.2 0.2 V

VOC(PP)

Peak-to-peak common-mode output

voltage

See Figure 8-3

400 mV

VOC(SS) Steady-state common-mode output voltage 1.4 2.5 V

ΔVOC(SS)

Change in steady-state common-mode

output voltage –0.05 0.05 V

IOZ High-impedance output current See receiver input currents

IIInput current D –100 0 μA

DE 0 100

IOS Short-circuit output current –7 V ≤ VO ≤ 12 V –250 250 mA

C(OD) Differential output capacitance VOD = 0.4 sin(4E6πt) + 0.5 V, DE at 0 V 16 pF

ICC Supply current

RE at VCC,

D and DE at VCC,

No load

Receiver disabled and

driver enabled 9 15.5 mA

RE at VCC,

D at VCC,

DE at 0 V,

No load

Receiver disabled

and driver disabled

(standby)

1 5 μA

RE at 0 V,

D and DE at VCC,

No load

Receiver enabled and

driver enabled 9 15.5 mA

(1) All typical values are at 25°C and with a 3.3-V supply.

(2) For TA > 85°C, VCC is ±5%.

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SN65HVD10, SN65HVD11, SN65HVD12

SN75HVD10, SN75HVD11, SN75HVD12

SLLS505P – FEBRUARY 2002 – REVISED FEBRUARY 2022

Product Folder Links: SN65HVD10 SN65HVD11 SN65HVD12 SN75HVD10 SN75HVD11 SN75HVD12

TEXAS INSTRUMENTS

7.6 Receiver Electrical Characteristics

Over recommended operating conditions unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT

VIT+ Positive-going input threshold voltage IO = –8 mA –0.065 –0.01

VIT–

Negative-going input threshold

voltage IO = 8 mA –0.2 –0.1

Vhys Hysteresis voltage (VIT+ – VIT–) 35 mV

VIK Enable-input clamp voltage II = –18 mA –1.5 V

VOH High-level output voltage VID = 200 mV, IOH = –8 mA, see Figure 8-8 2.4 V

VOL Low-level output voltage VID = –200 mV, IOL = 8 mA, see Figure 8-8 0.4 V

IOZ High-impedance-state output current VO = 0 or VCC, RE at VCC –1 1 μA

IIBus input current

VA or VB = 12 V

HVD11, HVD12,

Other inputs at 0 V

0.05 0.11

VA or VB = 12 V, VCC = 0 V 0.06 0.13

VA or VB = –7 V –0.1 –0.05

VA or VB = –7 V, VCC = 0 V –0.05 –0.04

VA or VB = 12 V

HVD10,

Other inputs at 0 V

0.2 0.5

VA or VB = 12 V, VCC = 0 V 0.25 0.5

VA or VB = –7 V –0.4 –0.2

VA or VB = –7 V, VCC = 0 V –0.4 –0.15

IIH High-level input current, RE VIH = 2 V –30 0 μA

IIL Low-level input current, RE VIL = 0.8 V –30 0 μA

CID Differential input capacitance VID = 0.4 sin(4E6πt) + 0.5 V, DE at 0 V 15 pF

ICC Supply current

RE at 0 V

D and DE at 0 V

No load

Receiver enabled and driver

disabled 4 8 mA

RE at VCC

D at VCC

DE at 0 V

No load

Receiver disabled and driver

disabled (standby) 1 5 μA

RE at 0 V

D and DE at VCC

No load

Receiver enabled and driver

enabled 9 15.5 mA

(1) All typical values are at 25°C and with a 3.3-V supply.

7.7 Power Dissipation Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

PDDevice power dissipation

RL= 60 Ω, CL = 50 pF,

DE at VCC, RE at 0 V,

Input to D is a 50% duty-cycle

square wave at indicated signaling

rate

HVD10

(32Mbps) 198 250

HVD11

(10Mbps) 141 176

HVD12

(500 kbps) 133 161

TAAmbient air temperature(1) High-K board, no airflow D pkg –40 116 °C

No airflow(2) P pkg –40 123

TJSD Thermal shutdown junction temperature(1) 165 °C

(1) See Section 12.3.1 section for an explanation of these parameters.

(2) JESD51−10, Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements.

SN65HVD10, SN65HVD11, SN65HVD12

SN75HVD10, SN75HVD11, SN75HVD12

SLLS505P – FEBRUARY 2002 – REVISED FEBRUARY 2022 www.ti.com

Product Folder Links: SN65HVD10 SN65HVD11 SN65HVD12 SN75HVD10 SN75HVD11 SN75HVD12

I TEXAS INSTRUMENTS

7.8 Driver Switching Characteristics

Over recommended operating conditions unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT

tPLH

Propagation delay time,

low-to-high-level output

HVD10

RL = 54 Ω, CL = 50 pF

See Figure 8-4

5 8.5 16

nsHVD11 18 25 40

HVD12 135 200 300

tPHL

Propagation delay time,

high-to-low-level output

HVD10 5 8.5 16

nsHVD11 18 25 40

HVD12 135 200 300

Differential output signal

rise time

HVD10 3 4.5 10

nsHVD11 10 20 30

HVD12 100 170 300

Differential output signal

fall time

HVD10 3 4.5 10

nsHVD11 10 20 30

HVD12 100 170 300

tsk(p) Pulse skew (|tPHL – tPLH|)

HVD10 1.5

nsHVD11 2.5

HVD12 7

tsk(pp) (2) Part-to-part skew

HVD10 6

nsHVD11 11

HVD12 100

tPZH

Propagation delay

time, high-impedance-to-

high-level output

HVD10

RL = 110 Ω, RE at 0 V

See Figure 8-5

nsHVD11 55

HVD12 300

tPHZ

Propagation delay

time, high-level-to-high-

impedance output

HVD10 25

nsHVD11 55

HVD12 300

tPZL

Propagation delay

time, high-impedance-to-

low-level output

HVD10

RL = 110 Ω, RE at 0 V

See Figure 8-6

nsHVD11 55

HVD12 300

tPLZ

Propagation delay

time, low-level-to-high-

impedance output

HVD10 26

nsHVD11 75

HVD12 400

tPZH

Propagation delay time, standby-to-high-

level output

RL = 110 Ω, RE at 3 V

See Figure 8-5 6 μs

tPZL

Propagation delay time, standby-to-low-

level output

RL = 110 Ω, RE at 3 V

See Figure 8-6 6 μs

(1) All typical values are at 25°C and with a 3.3-V supply.

(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices

operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

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SN65HVD10, SN65HVD11, SN65HVD12

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SLLS505P – FEBRUARY 2002 – REVISED FEBRUARY 2022

Product Folder Links: SN65HVD10 SN65HVD11 SN65HVD12 SN75HVD10 SN75HVD11 SN75HVD12

TEXAS INSTRUMENTS

7.9 Receiver Switching Characteristics

Over recommended operating conditions unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT

tPLH

Propagation delay time,

low-to-high-level output HVD10

VID = –1.5 V to 1.5 V

CL = 15 pF

See Figure 8-9

12.5 20 25

tPHL

Propagation delay time,

high-to-low-level output HVD10 12.5 20 25

tPLH

Propagation delay time,

low-to-high-level output

HVD11

HVD12 30 55 70 ns

tPHL

Propagation delay time,

high-to-low-level output

HVD11

HVD12 30 55 70 ns

tsk(p) Pulse skew (|tPHL – tPLH|)

HVD10 1.5

nsHVD11 4

HVD12 4

tsk(pp) (2) Part-to-part skew

HVD10 8

nsHVD11 15

HVD12 15

trOutput signal rise time CL = 15 pF

See Figure 8-9

1 2 5 ns

tfOutput signal fall time 1 2 5

tPZH (1) Output enable time to high level

CL = 15 pF, DE at 3 V

See Figure 8-10

tPZL (1) Output enable time to low level 15

tPHZ Output disable time from high level 20

tPLZ Output disable time from low level 15

tPZH (2) Propagation delay time, standby-to-high-

level output CL = 15 pF, DE at 0

See Figure 8-11

μs

tPZL (2) Propagation delay time, standby-to-low-

level output 6

(1) All typical values are at 25°C and with a 3.3-V supply

(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices

operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

7.10 Dissipation Ratings

PACKAGE TA ≤ 25°C

POWER RATING

DERATING FACTOR(1)

ABOVE TA = 25°C

TA = 70°C

POWER RATING

TA = 85°C

POWER RATING

TA = 125°C

POWER RATING

D(2) 597 mW 4.97 mW/°C 373 mW 298 mW 100 mW

D(3) 990 mW 8.26 mW/°C 620 mW 496 mW 165 mW

P 1290 mW 10.75 mW/°C 806 mW 645 mW 215 mW

(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.

(2) Tested in accordance with the Low-K thermal metric definitions of EIA/JESD51-3.

(3) Tested in accordance with the High-K thermal metric definitions of EIA/JESD51-7.

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Product Folder Links: SN65HVD10 SN65HVD11 SN65HVD12 SN75HVD10 SN75HVD11 SN75HVD12

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7.11 Typical Characteristics

0 5 10 15 20 25 30 35 40

ICC

TA= 25°C

RE at VCC

DE at VCC

VCC = 3.6 V

VCC = 3.3 V

VCC = 3 V

− RMS Supply Current − mA

Signaling Rate − Mbps

RL= 54 W

CL= 50 pF

Figure 7-1. HVD10 RMS Supply Current vs Signaling Rate

0 2.5 5 7.5 10

VCC = 3.6 V

VCC = 3.3 V

VCC = 3 V

Signaling Rate − Mbps

ICC− RMS Supply Current − mA

TA= 25°C

RE at VCC

DE at VCC

RL= 54 W

CL= 50 pF

Figure 7-2. HVD11 RMS Supply Current vs Signaling Rate

100 400 700 1000

VCC = 3.6 V

VCC = 3.3 V

VCC = 3 V

Signaling Rate − kbps

ICC− RMS Supply Current − mA

TA= 25°C

RE at VCC

DE at VCC

RL= 54 W

CL= 50 pF

Figure 7-3. HVD12 RMS Supply Current vs Signaling Rate

−200

−150

−100

−50

100

150

200

250

300

−7 −6−5 −4−3 −2−1 0 1 2 3 4 5 6 7 8 9 10 11 12

− Bus Input Current −IIuA

VI− Bus Input Voltage − V

VCC = 0 V

VCC = 3.3 V

TA= 25°C

DE at 0 V

Figure 7-4. HVD10 Bus Input Current vs Bus Input Voltage

−60

−50

−40

−30

−20

−10

−7 −6 −5 −4 −3 −2 −1 0 1 2 3 4 5 6 7 8 9 10 11 12

− Bus Input Current −IIuA

VI− Bus Input Voltage − V

VCC = 0 V

VCC = 3.3 V

TA= 25°C

DE at 0 V

Figure 7-5. HVD11 or HVD12 Bus Input Current vs Bus Input

Voltage

−200

−150

−100

−50

100

150

−4 −2 0 2 4 6

TA = 25°C

DE at VCC

D at VCC

VCC = 3.3 V

VOH − Driver High-Level Output Voltage − V

IOH − High-Level Output Current − mA

Figure 7-6. High-Level Output Current vs Driver High-Level

Output Voltage

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SN65HVD10, SN65HVD11, SN65HVD12

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7.11 Typical Characteristics (continued)

−20

100

120

140

160

180

200

−4 −2 0 2 4 6 8

TA = 25°C

DE at VCC

D at 0 V

VCC = 3.3 V

VOL − Driver Low-Level Output Voltage − V

IOL− Low-Level Output Current − mA

Figure 7-7. Low-Level Output Current vs Driver Low-Level

Output Voltage

− Driver Differential Output − V

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

−40 −15 10 35 60 85

VOD

TA− Free-Air Temperature − °C

VCC = 3.3 V

DE at VCC

D at VCC

Figure 7-8. Driver Differential Output vs Free-Air Temperature

VCC − Supply Voltage − V

−35

−30

−25

−20

−40

−15

−10

−5

− Driver Output Current − mA

0 0.50 1 1.50 2 2.50 3 3.50

TA = 25°C

DE at VCC

D at VCC

RL = 54 Ω

Figure 7-9. Driver Output Current vs Supply Voltage

HVD12

HVD11

100

400

500

600

-7 -2 3 8 13

HVD10

EnableTime − ns

V −

(TEST) Common-ModeVoltage − V

200

300

Figure 7-10. Enable Time vs Common-Mode Voltage

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8 Parameter Measurement Information

IOA

VOD 54 1%Ω±

0 or 3 V

VOA

VOB

IOB

VCC

Figure 8-1. Driver VOD Test Circuit and Voltage and Current Definitions

60 Ω ±1%

VOD

0 or 3 V

+−7 V < V(test) < 12 V

VCC

375 Ω ±1%

Figure 8-2. Driver VOD With Common-Mode Loading Test Circuit

VOC

27 Ω ± 1%

Input

VOC(PP) DV

OC(SS)

VOC

27 Ω ± 1%

CL= 50 pF ±20%

VCC

CLIncludes Fixture and

Instrumentation Capacitance

Input: PRR = 500 kHz, 50% Duty Cycle, tr < 60 ns, tf < 6 ns ZO = 50 Ω

Figure 8-3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage

VOD

RL= 54 Ω

± 1%

50 Ω

tPLH tPHL

1.5 V 1.5 V

3 V

≈2 V

≈–2 V

90%

10%

0 V

VOD

trtf

CL= 50 pF ±20%

CLIncludes Fixture

and Instrumentation

Capacitance

VCC

Input

Generator

90%

0 V

10%

Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 60 ns, tf < 6 ns ZO = 50 Ω

Figure 8-4. Driver Switching Test Circuit and Voltage Waveforms

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RL= 110 Ω

± 1%

Input

Generator 50 Ω

3 V

0.5 V

3 V

0 V

VOH

≈0 V

tPHZ

tPZH

1.5 V 1.5 V

CL= 50 pF ±20%

CLIncludes Fixture

and Instrumentation

Capacitance

2.3 V

Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 60 ns, tf < 6 ns ZO = 50 Ω

Figure 8-5. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms

Input

Generator 50 Ω

3 V VO

3 V

1.5 V 1.5 V

tPZL tPLZ

2.3 V

0.5 V

≈3 V

0 V

VOL

RL= 110 Ω

± 1%

CL= 50 pF ±20%

CLIncludes Fixture

and Instrumentation

Capacitance

≈3 V

Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 60 ns, tf < 6 ns ZO = 50 Ω

Figure 8-6. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms

60 W

1%±

50 Ω

375 Ω 1%±

-7 V < V < 12 V

(TEST)

VOD

V (low)

t (diff)

pZL

t (diff)

pZH

0 or 3 V

375 Ω 1%±

50%

0 V

1.5 V

-1.5 V

V (high)

Input

Generator

The time tPZL(x) is the measure from DE to VOD(x). VOD is valid when it is greater than 1.5 V.

Figure 8-7. Driver Enable Time from DE to VOD

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VID

IBVO

VIC

VA+ VB

Figure 8-8. Receiver Voltage and Current Definitions

Input

Generator 50 Ω

Generator: PRR = 500 kHz, 50% Duty Cycle, tr<6 ns, tf<6 ns, Zo= 50 Ω

1.5 V

0 V

1.5 V 1.5 V

3 V

VOH

VOL

1.5 V

10%

1.5 V

tPLH tPHL

trtf

90%

CL= 15 pF ±20%

CLIncludes Fixture

and Instrumentation

Capacitance

0 V

90%

10%

Figure 8-9. Receiver Switching Test Circuit and Voltage Waveforms

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50 Ω

Generator: PRR = 500 kHz, 50% Duty Cycle, t r<6 ns, tf<6 ns, Zo= 50 Ω

3 V

0 V or 3 V

3 V

1.5 V 1.5 V

tPZH(1) tPHZ

1.5 V

VOH –0.5 V

3 V

0 V

VOH

≈0 V

CL= 15 pF ±20%

CLIncludes Fixture

and Instrumentation

Capacitance

D1 kΩ ± 1%

D at 3 V

S1 to B

tPZL(1) tPLZ

1.5 V VOL +0.5 V

≈3 V

VOL

D at 0 V

S1 to A

Input

Generator

Figure 8-10. Receiver Enable and Disable Time Test Circuit and Voltage Waveforms With Drivers Enabled

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Input

Generator 50 Ω

Generator: PRR = 100 kHz, 50% Duty Cycle, t r<6 ns, tf<6 ns, Zo= 50 Ω

3 V

1.5 V

tPZH(2)

1.5 V

3 V

0 V

VOH

GND

0 V or 1.5 V

1.5 V or 0 V CL= 15 pF ±20%

CLIncludes Fixture

and Instrumentation

Capacitance

1 kΩ ± 1% A

A at 1.5 V

B at 0 V

S1 to B

tPZL(2)

1.5 V

3 V

VOL

A at 0 V

B at 1.5 V

S1 to A

Figure 8-11. Receiver Enable Time From Standby (Driver Disabled)

Pulse Generator ,

15 ms Duration,

1% Duty Cycle

tr, tf≤100 ns

100 W

± 1%

0 V or 3 V

3 V or 0 V

NOTE: This test is conducted to test survivability only. Data stability at the R output is not specified.

Figure 8-12. Test Circuit, Transient Over Voltage Test

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9 V

1 kΩ

100 kΩ

Input

VCC

D and RE Inputs

9 V

1 kΩ

100 kΩ

Input

VCC

DE Input

16 V

R3 R1

Input

A Input

16 V

R3 R1

Input

B Input

16 V

VCC

A and B Outputs

9 V

VCC

R Output

5 Ω

Output

VCC

SN65HVD10

SN65HVD11

SN65HVD12

R1/R2

9 kW

36 kW

45 kW

180 kW

VCC

Output

Figure 8-13. Equivalent Input and Output Schematic Diagrams

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9 Detailed Description

9.1 Overview

The SN65HVD10, SN65HVD11, and SN65HVD12 are 3.3 V, half-duplex, and RS-485 transceivers that are

available in 3 speed grades suitable for data transmission up to 32 Mbps, 10 Mbps, and 1 Mbps.

These devices have both active-high driver enables and active-low receiver enables. A standby current of less

than

5 µA can be achieved by disabling both driver and receiver.

9.2 Functional Block Diagram

9.3 Feature Description

Internal ESD protection circuits protect the transceiver bus terminals against ±16-kV Human Body Model (HBM)

electrostatic discharges and ±4-kV electrical fast transients (EFT) according to IEC61000-4-4.

The SN65HVD1x half-duplex family provides internal biasing of the receiver input thresholds for open-circuit,

bus-idle, or short-circuit fail-safe conditions, as well as a typical receiver hysteresis of 35 mV.

9.4 Device Functional Modes

When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input

D. A logic high at D causes A to turn high and B to turn low. In this case, the differential output voltage defined

as VOD = VA – VB is positive. When D is low, the output states reverse, B turns high, A becomes low, and VOD is

negative.

When DE is low, both outputs turn high-impedance. In this condition, the logic state at D is irrelevant. The DE

pin has an internal pulldown resistor to ground; therefore, when left open, the driver is disabled (high-impedance)

by default. The D pin has an internal pullup resistor to VCC; therefore, when left open while the driver is enabled,

output A turns high and B turns low.

Table 9-1. Driver Functions(1)

INPUT ENABLE OUTPUTS FUNCTION

D DE A B

H H H L Actively drive bus High

L H L H Actively drive bus Low

X L Z Z Driver disabled

X OPEN Z Z Driver disabled by default

OPEN H H L Actively drive bus High by default

(1) H = high level; L = low level; Z = high impedance; X = irrelevant; ? = indeterminate

When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage

defined as VID = VA – VB is positive and higher than the positive input threshold, VIT+, the receiver output, R,

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turns high. When VID is negative and lower than the negative input threshold, VIT–, the receiver output, R, turns

low. If VID is between VIT+ and VIT–, the output is indeterminate.

When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID

are irrelevant. Internal biasing of the receiver inputs causes the output to go fail-safe-high when the transceiver

is disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or when the bus is not

actively driven (idle bus).

Table 9-2. Receiver Functions(1)

DIFFERENTIAL INPUT

VID = VA – VB

ENABLE

OUTPUT

RFUNCTION

VID > VIT+ L H Receive valid bus High

VIT– < VID < VIT+ L ? Indeterminate bus state

VID < VIT– L L Receive valid bus Low

X H Z Receiver disabled

X OPEN Z Receiver disabled by default

Open-circuit bus L H Fail-safe high output

Short-circuit bus L H Fail-safe high output

(1) H = high level; L = low level; Z = high impedance; X = irrelevant; ? = indeterminate

9.4.1 Low-Power Standby Mode

When both the driver and receiver are disabled (DE low and RE high) the device is in standby mode. If the

enable inputs are in this state for less than 60 ns, the device does not enter standby mode. This guards against

inadvertently entering standby mode during driver or receiver enabling. Only when the enable inputs are held in

this state for 300 ns or more, the device is assured to be in standby mode. In this low-power standby mode, most

internal circuitry is powered down, and the supply current is typically less than 1 µA. When either the driver or

the receiver is re-enabled, the internal circuitry becomes active.

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10 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

10.1 Application Information

The SN65HVD10, 'HVD11, and 'HVD12 are half-duplex RS-485 transceivers commonly used for asynchronous

data transmissions. The driver and receiver enable pins allow the configuration of different operating modes.

a) Independent driver and

receiver enable signals

b) Combined enable signals for

use as directional control pin

c) Receiver always on

Figure 10-1. Half-Duplex Transceiver Configurations

1. Using independent enable lines provides the most flexible control, as it allows the driver and the receiver

to be turned on and off individually. While this configuration requires two control lines, it allows selective

listening into the bus traffic, whether the driver is transmitting data or not.

2. Combining the enable signals simplify the interface to the controller, by forming a single direction-control

signal. In this configuration, the transceiver operates as a driver when the direction-control line is high, and

as a receiver when the direction-control line is low.

3. Only one line is required when connecting the receiver-enable input to ground and controlling only the

driver-enable input. In this configuration, a node not only receives the data from the bus, but also the data it

sends and can verify that the correct data have been transmitted.

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10.2 Typical Application

An RS-485 bus consists of multiple transceivers connected in parallel to a bus cable. To eliminate line

reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic

impedance, Z0, of the cable. This method, known as parallel termination, allows higher data rates over a longer

cable length.

RTRT

A B

R RE DE D

A B

R RE DE D

Figure 10-2. Typical RS-485 Network With Half-Duplex Transceivers

10.2.1 Design Requirements

RS-485 is a robust electrical standard suitable for long-distance networking, that may be used in a wide range of

applications with varying requirements, such as distance, data rate, and number of nodes.

10.2.1.1 Data Rate and Bus Length

There is an inverse relationship between data rate and bus length, meaning the higher the data rate, the shorter

the cable length; and conversely, the lower the data rate, the longer the cable may be without introducing data

errors. While most RS-485 systems use data rates between 10 kbps and 100 kbps, some applications require

data rates up to 250 kbps at distances of 4000 feet and longer. Longer distances are possible by allowing small

signal jitter of up to 5 or 10%.

Cable Length (ft)

Data Rate (bps)

10000

1000

100

100 1k 10 k 100 k 1M 10 M 100 M

Conservative

Characteristics

5%, 10%, and 20% Jitter

Figure 10-3. Cable Length vs Data Rate Characteristic

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10.2.1.2 Stub Length

When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as

the stub, should be as short as possible. Stubs present a nonterminated piece of bus line, which can introduce

reflections as the length of the stub increases. As a general guideline, the electrical length or round-trip delay

of a stub should be less than one-tenth of the rise time of the driver, therefore giving a maximum physical stub

length as shown in Equation 1.

L(STUB) ≤ 0.1 × tr × v × c(1)

where

• tr is the 10/90 rise time of the driver

•v is the signal velocity of the cable or trace as a factor of c

•c is the speed of light (3 × 108 m/s)

Per Equation 1, Table 10-1 lists the maximum cable-stub lengths for the minimum-driver output rise-times of the

SN65HVD1x full-duplex family of transceivers for a signal velocity of 78%.

Table 10-1. Maximum Stub Length

DEVICE MINIMUM DRIVER OUTPUT

RISE TIME (ns)

MAXIMUM STUB LENGTH

(m) (ft)

SN65HVD10 3 0.07 0.23

SN65HVD11 10 0.23 0.75

SN65HVD12 100 2.34 7.67

10.2.1.3 Bus Loading

The RS-485 standard specifies that a compliant driver must be able to driver 32 unit loads (UL), where 1

unit load represents a load impedance of approximately 12 kΩ. SN65HVD11 and HVD12 are both 1/8 UL

transceivers, which means that up to 256 receivers can be connected to the bus. The SN65HVD10 is a 1/4 UL

transceiver, and up to 64 receivers can be connected to the bus.

10.2.1.4 Receiver Fail-safe

The differential receivers of the SN65HVD1x family are fail-safe to invalid bus states caused by:

• Open bus conditions, such as a disconnected connector

• Shorted bus conditions, such as cable damage shorting the twisted-pair together

• Idle bus conditions that occur when no driver on the bus is actively driving.

In any of these cases, the differential receiver will output a fail-safe logic High state so that the output of the

receiver is not indeterminate.

Receiver fail-safe is accomplished by offsetting the receiver thresholds, such that the input indeterminate range

does not include zero volts differential. To comply with the RS-422 and RS-485 standards, the receiver output

must output a High when the differential input VID is more positive than +200 mV, and must output a Low when

VID is more negative than –200 mV. The receiver parameters which determine the fail-safe performance are

VIT(+) and VIT(–). As shown in Section 7.6, differential signals more negative than –200 mV will always cause

a Low receiver output, and differential signals more positive than +200 mV will always cause a High receiver

output.

When the differential input signal is close to zero, it is still above the maximum VIT(+) threshold of –10 mV, and

the receiver output will be High.

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I TEXAS INSTRUMENTS Vcc Cupyngm©2o11 Texas Instruments Incurpomea TeK Run: 25.nMS/s Sample [ T ] “WW 2* m N “Am 2.nov M2.00}As Aux! 71.17V1renzooz 5 1”” 13:25:50 Receiver Oulpul

10.2.2 Detailed Design Procedure

To protect bus nodes against high-energy transients, the implementation of external transient protection devices

is therefore necessary. Figure 10-4 shows a protection circuit against 10-kV ESD (IEC 61000-4-2), 4-kV EFT

(IEC 61000-4-4), and 1-kV surge (IEC 61000-4-5) transients.

Vcc

GND

Vcc

10 k

XCVR

TVS

Vcc

0.1 μF

RxD

TxD

DIR

MCU

Figure 10-4. Transient Protection Against ESD, EFT, and Surge Transients

Table 10-2. Bill of Materials

DEVICE FUNCTION ORDER NUMBER MANUFACTURER

XCVR 3.3-V, full-duplex RS-485

transceiver

SN65HVD1xD TI

R1, R2 10-Ω, pulse-proof, thick-

film resistor

CRCW0603010RJNEAHP Vishay

TVS Bidirectional 400-W

transient suppressor

CDSOT23-SM712 Bourns

10.2.3 Application Curve

Figure 10-5 demonstrates operation of the SN65HVD12 at a signaling rate of 250 kbps. Two SN65HVD12

transceivers are used to transmit data through a 2,000 foot (600 m) segment of Commscope 5524 category

5e+ twisted pair cable. The bus is terminated at each end by a 100-Ω resistor, matching the cable characteristic

impedance.

Driver Input

Driver Output

Receiver Input

Receiver Output

Figure 10-5. SN65HVD12 Input and Output Through 2000 Feet of Cable

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11 Power Supply Recommendations

To assure reliable operation at all data rates and supply voltages, each supply must be buffered with a 100-nF

ceramic capacitor located as close to the supply pins as possible. The TPS76333 linear voltage regulator is

suitable for the 3.3-V supply.

12 Layout

12.1 Layout Guidelines

On-chip IEC-ESD protection is sufficient for laboratory and portable equipment, but never sufficient for EFT and

surge transients occurring in industrial environments. Therefore, robust and reliable bus node design requires

the use of external transient protection devices.

It is because ESD and EFT transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz,

that high-frequency layout techniques must be applied during PCB design.

1. Place the protection circuitry close to the bus connector to prevent noise transients from entering the board.

2. Use VCC and ground planes to provide low-inductance. Note that high-frequency currents follow the path of

least inductance and not the path of least impedance.

3. Design the protection components into the direction of the signal path. Do not force the transient currents to

divert from the signal path to reach the protection device.

4. Apply 100-nF to 220-nF bypass capacitors as close as possible to the VCC pins of transceiver, UART, and

controller ICs on the board.

5. Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to

minimize effective via-inductance.

6. Use 1-kΩ to 10-kΩ pull-up or pull-down resistors to enable lines to limit noise currents in these lines during

transient events.

7. Insert pulse-proof series resistors into the A and B bus lines if the TVS clamping voltage is higher than

the specified maximum voltage of the transceiver bus terminals. These resistors limit the residual clamping

current into the transceiver and prevent it from latching up.

8. While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide

varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient

blocking units (TBUs) that limit transient current to less than 1 mA.

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12.2 Layout Example

MCU

Via to ground

XCVR

JMP

Via to VCC

TVS

Figure 12-1. SN65HVD1x Layout Example

12.3 Thermal Considerations

12.3.1 Thermal Characteristics of IC Packages

RθJA (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to

ambient temperature divided by the operating power.

RθJA is not a constant and is a strong function of:

• the PCB design (50% variation)

• altitude (20% variation)

• device power (5% variation)

RθJA can be used to compare the thermal performance of packages when specific test conditions are defined

and used. Standardized testing includes specification of PCB construction, test chamber volume, sensor

locations, and the thermal characteristics of holding fixtures. RθJA is often misused when it is used to calculate

junction temperatures for other installations.

TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition

thermal performance, and it consists of a single copper trace layer 25 mm long and 2-oz thick. The high-k board

gives best case in-use condition, and it consists of two 1-oz buried power planes with a single copper trace layer

25 mm long and 2-oz thick. A 4% to 50% difference in RθJA can be measured between these two test cards.

RθJC (Junction-to-Case Thermal Resistance) is defined as the difference in junction temperature to case

divided by the operating power. It is measured by putting the mounted package up against a copper block cold

plate to force heat to flow from the die, through the mold compound into the copper block.

RθJC is a useful thermal characteristic when a heat sink is applied to package. It is not a useful characteristic

to predict junction temperature, because it provides pessimistic numbers if the case temperature is measured

in a nonstandard system and junction temperatures are backed out. It can be used with RθJB in 1-dimensional

thermal simulation of a package system.

RθJB (Junction-to-Board Thermal Resistance) is defined as the difference in the junction temperature and the

PCB temperature at the center of the package (closest to the die) when the PCB is clamped in a cold-plate

structure. RθJB is only defined for the high-k test card.

RθJB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal

resistance (especially for BGAs with thermal balls) and can be used for simple 1-dimensional network analysis of

package system, see Figure 12-2.

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Ambient Nod: Amhicm R. Surfam Nud: E]: CalculatcdchasuIni R Juucﬁm l 3,, Calculatcw'Mcmcd R

Figure 12-2. PCB Thermal Resistances

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13 Device and Documentation Support

13.1 Device Support

13.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to order now.

Table 13-1. Related Links

PARTS PRODUCT FOLDER ORDER NOW TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

SN65HVD10 Click here Click here Click here Click here Click here

SN65HVD11 Click here Click here Click here Click here Click here

SN65HVD12 Click here Click here Click here Click here Click here

SN75HVD10 Click here Click here Click here Click here Click here

SN75HVD11 Click here Click here Click here Click here Click here

SN75HVD12 Click here Click here Click here Click here Click here

13.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

13.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

13.5 Trademarks

TI E2E™ is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

13.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

13.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

SN65HVD10, SN65HVD11, SN65HVD12

SN75HVD10, SN75HVD11, SN75HVD12

SLLS505P – FEBRUARY 2002 – REVISED FEBRUARY 2022 www.ti.com

Product Folder Links: SN65HVD10 SN65HVD11 SN65HVD12 SN75HVD10 SN75HVD11 SN75HVD12

I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Samples Sample: Sample: Samples Samples Samples Samples Samples Samples Samples Samples Samples

PACKAGE OPTION ADDENDUM

www.ti.com 23-Nov-2021

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

SN65HVD10D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP10

SN65HVD10DG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP10

SN65HVD10DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP10

SN65HVD10DRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP10

SN65HVD10P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 65HVD10

SN65HVD10QD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 VP10Q

SN65HVD10QDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 VP10Q

SN65HVD10QDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 VP10Q

SN65HVD11D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP11

SN65HVD11DG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP11

SN65HVD11DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP11

SN65HVD11DRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP11

SN65HVD11P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 65HVD11

SN65HVD11QD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 VP11Q

SN65HVD11QDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 VP11Q

SN65HVD11QDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 VP11Q

SN65HVD12D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP12

SN65HVD12DG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP12

SN65HVD12DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP12

SN65HVD12DRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP12

I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples

PACKAGE OPTION ADDENDUM

www.ti.com 23-Nov-2021

Addendum-Page 2

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

SN65HVD12P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 65HVD12

SN75HVD10D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 VN10

SN75HVD10DG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 VN10

SN75HVD10DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 VN10

SN75HVD10P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 75HVD10

SN75HVD11D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 VN11

SN75HVD11DG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 VN11

SN75HVD11DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 VN11

SN75HVD11DRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 VN11

SN75HVD12D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 VN12

SN75HVD12DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 VN12

SN75HVD12P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 75HVD12

SN75HVD12PE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 75HVD12

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 23-Nov-2021

Addendum-Page 3

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN65HVD10, SN65HVD11, SN65HVD12 :

•Enhanced Product : SN65HVD10-EP, SN65HVD12-EP

NOTE: Qualified Version Definitions:

•Enhanced Product - Supports Defense, Aerospace and Medical Applications

l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«Pt» Reel Dlameter A0 Dimension designed to accommodate the component Width Bo Dimension deSigned to accommodate the component iengtn K0 Dimension designed to accommodate the component thickness 7 w OveraH Wiotn ot the carrier tape i P1 Pitch between successive cawty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE a O O D O O D D SprocketHotes ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrants

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

SN65HVD10DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

SN65HVD10QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

SN65HVD11DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

SN65HVD11QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

SN65HVD12DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

SN75HVD10DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

SN75HVD11DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

SN75HVD12DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 1

l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SN65HVD10DR SOIC D 8 2500 340.5 336.1 25.0

SN65HVD10QDR SOIC D 8 2500 340.5 336.1 25.0

SN65HVD11DR SOIC D 8 2500 340.5 336.1 25.0

SN65HVD11QDR SOIC D 8 2500 340.5 336.1 25.0

SN65HVD12DR SOIC D 8 2500 340.5 336.1 25.0

SN75HVD10DR SOIC D 8 2500 340.5 336.1 25.0

SN75HVD11DR SOIC D 8 2500 340.5 336.1 25.0

SN75HVD12DR SOIC D 8 2500 340.5 336.1 25.0

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 2

l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width $ — B - Alignment groove width

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)

SN65HVD10D D SOIC 8 75 507 8 3940 4.32

SN65HVD10DG4 D SOIC 8 75 507 8 3940 4.32

SN65HVD10P P PDIP 8 50 506 13.97 11230 4.32

SN65HVD10QD D SOIC 8 75 507 8 3940 4.32

SN65HVD10QDG4 D SOIC 8 75 507 8 3940 4.32

SN65HVD11D D SOIC 8 75 507 8 3940 4.32

SN65HVD11DG4 D SOIC 8 75 507 8 3940 4.32

SN65HVD11P P PDIP 8 50 506 13.97 11230 4.32

SN65HVD11QD D SOIC 8 75 507 8 3940 4.32

SN65HVD11QDG4 D SOIC 8 75 507 8 3940 4.32

SN65HVD12D D SOIC 8 75 507 8 3940 4.32

SN65HVD12DG4 D SOIC 8 75 507 8 3940 4.32

SN65HVD12P P PDIP 8 50 506 13.97 11230 4.32

SN75HVD10D D SOIC 8 75 507 8 3940 4.32

SN75HVD10DG4 D SOIC 8 75 507 8 3940 4.32

SN75HVD10P P PDIP 8 50 506 13.97 11230 4.32

SN75HVD11D D SOIC 8 75 507 8 3940 4.32

SN75HVD11DG4 D SOIC 8 75 507 8 3940 4.32

SN75HVD12D D SOIC 8 75 507 8 3940 4.32

SN75HVD12P P PDIP 8 50 506 13.97 11230 4.32

SN75HVD12PE4 P PDIP 8 50 506 13.97 11230 4.32

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 3

‘J

www.ti.com

PACKAGE OUTLINE

.228-.244 TYP

[5.80-6.19]

.069 MAX

[1.75]

6X .050

[1.27]

8X .012-.020

[0.31-0.51]

.150

[3.81]

.005-.010 TYP

[0.13-0.25]

0 - 8 .004-.010

[0.11-0.25]

.010

[0.25]

.016-.050

[0.41-1.27]

4X (0 -15 )

.189-.197

[4.81-5.00]

NOTE 3

B .150-.157

[3.81-3.98]

NOTE 4

4X (0 -15 )

(.041)

[1.04]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

.010 [0.25] C A B

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.800

Yl“‘+

www.ti.com

EXAMPLE BOARD LAYOUT

.0028 MAX

[0.07]

ALL AROUND

.0028 MIN

[0.07]

ALL AROUND

(.213)

[5.4]

6X (.050 )

[1.27]

8X (.061 )

[1.55]

8X (.024)

[0.6]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

EXPOSED

METAL

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SYMM

SEE

DETAILS

SYMM

www.ti.com

EXAMPLE STENCIL DESIGN

8X (.061 )

[1.55]

8X (.024)

[0.6]

6X (.050 )

[1.27] (.213)

[5.4]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

SYMM

MECHANICAL DATA P (RiPMPi’E) "LAST‘C >4 >4 7 A V A A M Hnear dw‘ensmns are m inches (miH'nem's) B TH: druwmq is s bje“ :0 change thruut nonce C mus wmhm Juli"; Msiom vanmm BA NUTS DKMLiwi, N¥ PAL’KAC: 4 r ( “ V ‘ 7 v m 31H A H ‘ ‘ M H ‘—’ H w: H J; W“ D u‘ L , ,_ , 40mm: 04/2010 INSI'RUMENTS www.mzam

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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