Texas Instruments 的 TPS25921(A,L) 規格書

V'.‘ ‘F. B X E I TEXAS INSTRUMENTS V ’_H_‘ % i 1 1 i i fl w
V(IN)
V(OUT)
FLTb
I_IN
10 V/div
5 V/div
10 V/div
1 A/div
TIME = 20 s/divm
90mO
IN OUT
ENUV
SS
GND TPS25921x
ILIM
OVP
4.5 to 18 V
V(IN)
FLT
Load
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TPS25921x 4.5V - 18V eFuse with Precise Current Limit and Over Voltage Protection
1 Features 3 Description
The TPS25921 is a compact, feature rich eFuse with
1• 4.5 V – 18 V Operating Voltage, 20 V (Max) a full suite of protection functions. The wide operating
• 90 mΩRDS(ON) (Typical) voltage allows control of many popular DC buses.
• 0.4 A to 1.6 A Adjustable Current Limit The precise ±2% current limit, at room temperature,
provides excellent accuracy making the TPS25921
• ±2% Accurate ILIMIT at 1A at 25°C well suited for many system protection applications.
• ±3% Overvoltage, Undervoltage Threshold Load, source and device protection are provided with
• Programmable dVO/dt Control multiple programmable features including overcurrent,
• Fault Output for Thermal Shutdown, UVLO and overvoltage and undervoltage. 3% threshold accuracy
OVP for UV and OV, ensures tight supervision of bus
• -40°C to 125°C Junction Temperature Range voltages, eliminating the need for supervisor circuitry.
Fault flag output (FLT) is provided for system status
• Auto-Retry and Latch-Off Versions monitoring and down stream load control.
• UL2367 Recognized - File No. E169910 For hot-plug-in boards, TPS25921 provides in-rush
• UL60950 - Safe during Single Point Failure Test current control and programmable output ramp-rate.
Output ramp rate is programmable using a capacitor
2 Applications at soft-start (SS) pin, for maximum design flexibility.
• White Goods, Appliances Device Information(1)
• Set Top Boxes, DVD and Gaming Consoles
PART NUMBER PACKAGE BODY SIZE (NOM)
• HDD and SSD drives TPS25921A
• Smart Meters, Gas Analyzers SOIC 4.90mm x 3.91mm
TPS25921L
• Smart Load Switch (1) For all available packages, see the orderable addendum at
• USB Switch the end of the datasheet.
• Adapter Power Devices
4 Application Schematic
12V Short Circuit Response
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
9.4 Device Functional Modes........................................ 17
1 Features.................................................................. 110 Applications and Implementation...................... 18
2 Applications ........................................................... 110.1 Application Information.......................................... 18
3 Description ............................................................. 110.2 Typical Application ................................................ 18
4 Application Schematic .......................................... 110.3 System Examples ................................................. 25
5 Revision History..................................................... 211 Power Supply Recommendations ..................... 28
6 Pin Configuration and Functions......................... 311.1 Transient Protection.............................................. 28
7 Specifications......................................................... 311.2 Output Short-Circuit Measurements ..................... 29
7.1 Absolute Maximum Ratings ...................................... 312 Layout................................................................... 30
7.2 ESD Ratings ............................................................ 312.1 Layout Guidelines ................................................. 30
7.3 Recommended Operating Conditions....................... 412.2 Layout Example .................................................... 30
7.4 Thermal Characteristics ........................................... 413 Device and Documentation Support ................. 31
7.5 Electrical Characteristics........................................... 513.1 Related Links ........................................................ 31
7.6 Timing Requirements................................................ 613.2 Community Resources.......................................... 31
7.7 Typical Characteristics.............................................. 713.3 Trademarks........................................................... 31
8 Parametric Measurement Information ............... 11 13.4 Electrostatic Discharge Caution............................ 31
9 Detailed Description............................................ 12 13.5 Glossary................................................................ 31
9.1 Overview ................................................................. 12 14 Mechanical, Packaging, and Orderable
9.2 Functional Block Diagram....................................... 12 Information ........................................................... 31
9.3 Feature Description................................................. 13
5 Revision History
Changes from Revision B (August 2015) to Revision C Page
• Changed Equation 2 From: 0.07 To: 70 pF, and added text "where C(ss) is in Farad" ....................................................... 14
• Changed Equation 21 From: (1 + 0.07) To: (1 x10-9 + 70 x 10-12) ....................................................................................... 22
• Changed Equation 26 From: (4.7 + 0.07) To: (4.7 x10-9 + 70 x 10-12) ................................................................................. 22
Changes from Revision A (March 2015) to Revision B Page
• Changed tss in Timing Requirements From: V(OUT) = 11.7 V To V(OUT) = 11 V and C(SS) = 1 nF To: C(SS) = 1.2 nF .............. 6
Changes from Original (August 2014) to Revision A Page
• Changed Features From: UL2367 Recognition Pending To: UL2367 Recognized - File No. E169910 ............................... 1
• Moved the Storage temperature range From: Handling Ratingstable To : Absolute Maximum Ratings .............................. 3
• Changed the Handling Ratings table To: ESD Ratings ......................................................................................................... 3
• Changed Equation 31 From: V(IN) x I(LOAD) To: V(IN) + I(LOAD). ............................................................................................... 28
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GND
SS
ENUV
IN
OVP
ILIM
OUT
1
2
3
4
8
7
6FLT
5
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6 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
Pin Functions
NAME NUMBER DESCRIPTION
GND 1 Ground.
SS 2 A capacitor from this pin to GND sets the ramp rate of output voltage at device turn-on.
Input for setting programmable undervoltage lockout threshold. An undervoltage event will open internal FET and
ENUV 3 assert FLT to indicate power-failure. When pulled to GND, resets the thermal fault latch in TPS25921L.
IN 4 Power Input and supply voltage of the device.
OUT 5 Power Output of the device.
Fault event indicator, goes low to indicate fault condition due to Undervoltage, Overvoltage, and Thermal shutdown
FLT 6 event. A nuisance fast trip does not trigger fault. It is an open drain output.
ILIM 7 A resistor from this pin to GND will set the overload and short circuit limit.
Input for setting programmable overvoltage protection threshold. An overvoltage event will open the internal FET and
OVP 8 assert FLT to indicate overvoltage.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VALUE(2) UNIT
MIN MAX
IN, OUT, ENUV, OVP, FLT –0.3 20 V
Input voltage range IN (10 ms Transient) 22
ILIM, SS –0.3 7
SS 5 mA
Sink current FLT 100 mA
Source current ILIM, SS, FLT Internally Limited
Maximum junction temperature, TJInternally Limited °C
Storage temperature range, Tstg -65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to network ground terminal.
7.2 ESD Ratings
VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification JESD22- ±500
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
IN 4.5 18
OUT, OVP, ENUV, FLT 0 18
Input voltage range V
SS 0 6
ILIM 0 3.3
Resistance ILIM 35.7 95.3 158 kΩ
OUT 0.1 1 µF
External capacitance SS 1 1000 nF
Operating junction temperature range, TJ–40 25 125 °C
7.4 Thermal Characteristics(1)
TPS2592xx
THERMAL METRIC UNIT
SOIC (8) PINS
RθJA Junction-to-ambient thermal resistance 120.8
RθJCtop Junction-to-case (top) thermal resistance 65.5
RθJB Junction-to-board thermal resistance 51.8 °C/W
ψJT Junction-to-top characterization parameter 17.4
ψJB Junction-to-board characterization parameter 61.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Electrical Characteristics
Conditions (unless otherwise noted) are –40°C ≤TJ≤125°C, 4.5 V ≤V(IN) ≤18 V, V(EN UV) = 2 V, V(OVP) = 0 V, R(ILIM) = 95.3
kΩ, CSS = OPEN, FLT = OPEN. Positive current into terminals. All voltages are referenced to GND (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE AND INTERNAL UNDERVOLTAGE LOCKOUT
V(IN) Operating Input Voltage 4.5 18 V
V(UVR) UVLO Threshold, Rising 4.10 4.26 4.40 V
V(UVHys) UVLO Hysteresis 168 224 279 mV
IQ( ON) Supply Current, Enabled V(ENUV) = 2 V, V(IN) = 12 V 0.22 0.41 0.58 mA
IQ( OFF) Supply Current, Disabled V(ENUV) = 0 V, V(IN) = 12 V 0.08 0.132 0.20 mA
OVERVOLTAGE PROTECTION (OVP) INPUT
Overvoltage Threshold Voltage,
V(OVPR) 1.35 1.39 1.43 V
Rising
Overvoltage Threshold Voltage,
V(OVPF) 1.30 1.34 1.37 V
Falling
I(OVP) OVP Input Leakage Current 0V ≤V(OVP) ≤18 V –100 0 100 nA
ENABLE AND UNDERVOLTAGE LOCKOUT (ENUV) INPUT
V(ENR) ENUV Threshold voltage, rising 1.36 1.39 1.42 V
V(ENF) ENUV Threshold voltage, falling 1.30 1.34 1.37 V
ENUV Threshold voltage to reset
V(ENF_RST) 0.5 0.61 0.8 V
thermal fault, falling
IEN EN Input leakage current 0 ≤V(ENUV) ≤18 V –100 0 100 nA
SOFT START: OUTPUT RAMP CONTROL (SS)
I(SS) SS charging current V(SS) = 0 V 0.9 1.04 1.2 µA
R(SS) SS discharging resistance V(ENUV) = 0 V, I(SS) = 10 mA sinking 60 70 85 Ω
V(SSmax) SS maximum capacitor voltage 5.5 V
GAIN(SS) SS to OUT gain ΔV(OUT)/ΔV(SS) 4.81 4.86 4.92 V/V
CURRENT LIMIT PROGRAMMING (ILIM)
I(ILIM) ILIM Bias current 6 10 16 µA
R(ILIM) = 35.7 kΩ, (V(IN) - V(OUT)) = 1 V 0.284 0.368 0.452
R(ILIM) = 45.3 kΩ, (V(IN) - V(OUT)) = 1 V 0.394 0.471 0.547
R(ILIM) = 95.3 kΩ, (V(IN) - V(OUT)) = 1 V, TA= TJ= 25°C 0.98 1.0 1.02
R(ILIM) = 95.3 kΩ, (V(IN) - V(OUT)) = 1 V 0.93 1.0 1.062
ILIMIT Current Limit(1) A
R(ILIM) = 150 kΩ, (V(IN) - V(OUT)) = 1 V 1.43 1.57 1.7
R(ILIM) = SHORT, Shorted resistor current limit
R(ILIM) = OPEN, Open resistor current limit 0.12 0.257 0.406
(Single Point Failure Test: UL60950)
R(ILIM) = 35.7 kΩ, (V(IN) - V(OUT)) = 12 V 0.275 0.356 0.438
R(ILIM) = 45.3 kΩ, (V(IN) - V(OUT)) = 12 V 0.376 0.45 0.522
IOS Short-circuit current limit(1) A
R(ILIM) = 95.3 kΩ, (V(IN) - V(OUT)) = 12 V 0.837 0.9 0.964
R(ILIM) = 150 kΩ, (V(IN) - V(OUT)) = 12 V 1.219 1.34 1.46
0.0142 x
I(FASTRIP) Fast-Trip comparator threshold R(ILIM) in kΩR(ILIM) + A
0.36
V(ILIMopen) ILIM Open resistor detect threshold V(ILIM) Rising, R(ILIM) = OPEN 2.81 3.0 3.25 V
MOSFET – POWER SWITCH
–40°C ≤TJ≤85°C 55 87 120
RDS(on) mΩ
FET ON resistance(2) –40°C ≤TJ≤125°C 55 87 135
PASS FET OUTPUT (OUT)
Ilkg(OUT) V(ENUV) = 0 V, V(OUT) = 0 V (Sourcing) –2 0 1
OUT Bias current in off state µA
Isink(OUT) V(ENUV) = 0V, V(OUT) = 300 mV (Sinking) 5 7 10
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature. Thermal effects must be taken into account
separately.
(2) The limits for these parameters are specified based on design and characterization data, and are not tested during production.
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Electrical Characteristics (continued)
Conditions (unless otherwise noted) are –40°C ≤TJ≤125°C, 4.5 V ≤V(IN) ≤18 V, V(EN UV) = 2 V, V(OVP) = 0 V, R(ILIM) = 95.3
kΩ, CSS = OPEN, FLT = OPEN. Positive current into terminals. All voltages are referenced to GND (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FAULT FLAG (FLT): ACTIVE LOW
R(FLT) FLT Pull down Resistance Device in fault condition, V(ENUV) = 0V, I(FLT) = 100mA 22 26 32 Ω
I(FLT) FLT Input Leakage Current Device not in fault condition, V(FLT) = 0V, 18V –0.5 0 0.5 µA
THERMAL SHUT DOWN (TSD)
T(TSD) TSD Threshold, rising(2) 155 °C
T(TSDhys) TSD Hysteresis(2) 20 °C
TPS25921L LATCHED
Thermal fault: Latched or Auto Retry AUTO-
TPS25921A RETRY
7.6 Timing Requirements
Conditions (unless otherwise noted) are –40°C ≤TJ≤125°C, V(IN)= 12 V, V(EN UV) = 2 V, V(OVP) = 0 V, R(ILIM) = 95.3 kΩ, CSS =
OPEN, FLT = OPEN. Positive current into terminals. All voltages are referenced to GND (unless otherwise noted). Refer to
Figure 26 for the timing diagrams
MIN TYP MAX UNIT
ENABLE AND UNDERVOLTAGE LOCKOUT (ENUV) INPUT
tOFF(dly) Turn Off delay ENUV ↓to V(OUT)↓8 µs
ENUV ↑to V(OUT) = 1V, 96
C(SS) = OPEN
tON(dly) Turn-On delay µs
ENUV ↑to V(OUT) = 1V, 14.5 + 0.5 x
C(SS) > 0.39nF, [C(dVdT) in nF] (70p + C(SS))
OVERVOLTAGE PROTECTION (OVP) INPUT
tOVP(dly) OVP Disable delay OVP↑to V(OUT)↓8 µs
SOFT START: OUTPUT RAMP CONTROL (SS)
ENUV ↑to V(OUT) = 11 V, with C(SS) = open, 0.2 0.26 0.33
C(OUT) = 2.2 µF
tSS Output ramp time ms
ENUV ↑to V(OUT) = 11 V, with C(SS) = 1.2 nF, 2.1 3 3.6
C(OUT) = 2.2 µF
CURRENT LIMIT PROGRAMMING (ILIM)
tFASTRIP(dly) Fast-Trip comparator delay I(OUT) > I(FASTRIP) 3 µs
THERMAL SHUT DOWN (TSD)
TPS25921A Only, V(IN) = 12 V 150 ms
Retry Delay after TSD
tTSD(dly) recovery, TJ< [T(TSD) - 20oC] TPS25921A Only, V(IN) = 4.5 V 100 ms
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Temperature (qC)
EN Threshold Voltage to Reset Fault Latch (V)
-50 -25 0 25 50 75 100 125 150
0.4
0.5
0.6
0.7
0.8
D006
Input Voltage (V)
Supply Current (PA)
0 5 10 15 20
0
50
100
150
200
250
D003
TA = 25qC
TA = 125qC
Temperature (qC)
Internal UVLO Threshold Voltage (V)
-50 -25 0 25 50 75 100 125 150
3.9
4
4.1
4.2
4.3
4.4
D001
V(UVR)
V(UVF)
Input Voltage (V)
Supply Current IQ(ON) (mA)
4 6 8 10 12 14 16 18
0
0.1
0.2
0.3
0.4
0.5
0.6
D002
TA = -40qC
TA = 25qC
TA = 85qC
TA = 125qC
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7.7 Typical Characteristics
Conditions (unless otherwise noted) are –40°C ≤TJ≤125°C, V(IN)= 12 V, V(EN UV) = 2 V, V(OVP) = 0 V, R(ILIM) = 95.3 kΩ, C(OUT)
= 2.2 μF, CSS = OPEN, FLT = OPEN. Positive current into terminals. All voltages referenced to GND (unless otherwise
noted). For all oscilloscope waveforms TA= 25°C.
Figure 1. UVLO Threshold Voltage vs Temperature Figure 2. Input Supply Current vs Supply Voltage During
Normal Operation
Figure 3. Input Supply Current vs Supply Voltage at Figure 4. ENUV and OVP Threshold Voltage vs Temperature
Shutdown
Figure 6. SS Pin Charging Current vs Temperature
Figure 5. EN Threshold Voltage to Reset Fault Latch vs
Temperature
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Current Limit (A)
Accuracy (%) (Process, Voltage, Temperature)
0 0.25 0.5 0.75 1 1.25 1.5 1.75
0
5
10
15
20
25
D012
Temperature (qC)
Current Limit (A)
-50 -25 0 25 50 75 100 125 150
0
0.4
0.8
1.2
1.6
2
2.4
D013
35.7 k:
45.3 k:
95.3 k:
150 k:
Temperature (qC)
Output Ramp Time (ms)
-50 -25 0 25 50 75 100 125 150
0.25
0.255
0.26
0.265
0.27
0.275
D010
R(ILM) Resistor (k:)
Current Limit and Fast Trip Threshold (A)
20 40 60 80 100 120 140 160
0
0.5
1
1.5
2
2.5
D011
ILIMIT
I(FASTRIP)
Soft Start Capacitor (nF)
Output Ramp Time (ms)
1 10 100
1
10
100
1k
D009
TA = -40qC
TA = 25qC
TA = 85qC
TA = 125qC
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Typical Characteristics (continued)
Conditions (unless otherwise noted) are –40°C ≤TJ≤125°C, V(IN)= 12 V, V(EN UV) = 2 V, V(OVP) = 0 V, R(ILIM) = 95.3 kΩ, C(OUT)
= 2.2 μF, CSS = OPEN, FLT = OPEN. Positive current into terminals. All voltages referenced to GND (unless otherwise
noted). For all oscilloscope waveforms TA= 25°C.
Figure 7. GAIN(SS) vs Temperature Figure 8. Output Ramp Time vs C(SS)
C(SS) = Open
Figure 9. Output Ramp Time vs Temperature Figure 10. Current Limit vs Current Limit Resistor
Figure 12. Current Limit vs Temperature Across R(ILIM)
Figure 11. Current Limit Accuracy vs Current Limit
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Temperature (qC)
RDS(ON) (m:)
-50 -25 0 25 50 75 100 125 150
45
60
75
90
105
120
135
D016
0.1
1
10
100
1000
10000
100000
0.1 1 10 100
Thermal Shutdown Time (ms)
Power Dissipation (W)
-40C
25C
85C
125C
C014
TA = -40oC
TA = 25oC
TA = 85oC
TA = 125oC
Power Dissipation (W)
Current Limit Normalized (%)
0 5 10 15 20 25
-25
-20
-15
-10
-5
0
D014
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Typical Characteristics (continued)
Conditions (unless otherwise noted) are –40°C ≤TJ≤125°C, V(IN)= 12 V, V(EN UV) = 2 V, V(OVP) = 0 V, R(ILIM) = 95.3 kΩ, C(OUT)
= 2.2 μF, CSS = OPEN, FLT = OPEN. Positive current into terminals. All voltages referenced to GND (unless otherwise
noted). For all oscilloscope waveforms TA= 25°C.
PD= [V(IN)-
V(OUT)]*ILIMIT Figure 14. Current Limit for R(ILIM) = Open and Short vs
Figure 13. Current Limit Normalized (%) vs Power Temperature
Dissipation in the Device PD
Taken on 1-Layer board, 2oz.(0.08-mm thick) with GND plane
area: 14 cm2 (bottom)
Figure 15. RDS(ON) vs Temperature Figure 16. Thermal Shutdown Time vs Power Dissipation
C(SS) = Open C(OUT) = 4.7 nF C(SS) = 1nF C(OUT) = 4.7 nF
Figure 17. Turn ON with Enable Figure 18. Turn ON with Enable
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Typical Characteristics (continued)
Conditions (unless otherwise noted) are –40°C ≤TJ≤125°C, V(IN)= 12 V, V(EN UV) = 2 V, V(OVP) = 0 V, R(ILIM) = 95.3 kΩ, C(OUT)
= 2.2 μF, CSS = OPEN, FLT = OPEN. Positive current into terminals. All voltages referenced to GND (unless otherwise
noted). For all oscilloscope waveforms TA= 25°C.
R(FLT) = 100 kΩR(FLT) = 100 kΩ
Figure 19. EN Turn ON Delay : EN ↑to Output Ramp ↑Figure 20. EN Turn OFF Delay : EN ↓to Fault ↓
RL= 12 ΩR(FLT) = 100 kΩRL= 12 ΩR(FLT) = 100 kΩ
Figure 21. OVP Turn OFF delay: OVP ↑to Fault ↓Figure 22. OVP Turn ON delay: OVP ↓to Output Ramp ↑
Figure 23. Hot-Short: Fast Trip Response and Current Figure 24. Hot-Short: Fast Trip Response (Zoomed)
Regulation
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tON(dly)
time
90%
1V
VEN
V(OUT)
0
5V
time
I(IN)
0
ILIMIT
I(FASTRIP)
tFASTRIP(dly)
tOVP(dly)
time
V(OVP)
0
5V
V(OUT)
50%
90%
VEN
time
90%
0
10%
tOFF(dly)
V(OUT)
5V
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8 Parametric Measurement Information
Figure 25. Timing Diagrams
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4
IN
3
ENUV
+
+
EN
TSD
1PA
70pF
SWEN
4.8x
70:
7
ILIM
+
+
+
ILIMIT
I(FASTRIP)
10uA
Charge
Pump
5
FLT
6
SWEN 26:
SWEN
Current
Sense
2
SS
1
GND
OUT
Fast Trip
Comp
Retry Timer
(TPS25921A Only)
S
R
Fault
Logic
TPS25921x
UVLO
8
OVP
OVP
+
GATE
CONTROL
90m:
I to V
1.39V
1.34V
1.39V
1.34V
4.26V
4.03V
Thermal
Shutdown
Q
0.61V +
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9 Detailed Description
9.1 Overview
TPS25921 is a smart eFuse with enhanced built-in protection circuitry. It provides robust protection for all
systems and applications powered from 4.5 V to 18 V.
For hot-plug-in boards, the device provides in-rush current control and programmable output ramp-rate.
TPS25921 integrates overcurrent and short circuit protection. The precision overcurrent limit helps to minimize
over design of the input power supply, while the fast response short circuit protection immediately isolates the
load from input when a short circuit is detected. The device allows the user to program the overcurrent limit
threshold between 0.4 A and 1.6 A via an external resistor. The device provides precise monitoring of voltage
bus for brown-out and overvoltage conditions and asserts fault for downstream system. Its threshold accuracy of
3% ensures tight supervision of bus, eliminating the need for a separate supply voltage supervisor chip.
TPS25921 is designed to protect systems such as White Goods, STBs, DTVs, Smart Meters and Gas Analyzers.
The additional features include:
• Over temperature protection to safely shutdown in the event of an overcurrent event
• Fault reporting for brown-out and overvoltage faults
• A choice of latched or automatic restart mode
9.2 Functional Block Diagram
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Product Folder Links: TPS25921A TPS25921L
l TEXAS INSTRUMENTS
R1
R2
R3
IN
ENUV
GND
TPS25921x
OVP
V(IN)
+EN
+OVP
1.39V
1.34V
1.39V
1.34V
TPS25921A
,
TPS25921L
www.ti.com
SLVSCE1C –AUGUST 2014–REVISED NOVEMBER 2015
9.3 Feature Description
9.3.1 Enable and Adjusting Undervoltage Lockout (UVLO)
The ENUV pin controls the ON/OFF state of the internal FET. A voltage V(ENUV) < V(ENF) on this pin turns off the
internal FET, thus disconnecting IN from OUT.
Toggling the ENUV pin below V(ENF_RST) resets the TPS25921L that has latched off due to a fault condition. The
internal de-glitch delay on ENUV falling edge is kept low for quick detection of power failure. For applications
where a higher de-glitch delay on ENUV is desired, or when the supply is particularly noisy, it is recommended to
use an external filter capacitor from the ENUV terminal to GND.
The undervoltage lockout threshold can be programmed by using an external resistor divider from the supply IN
terminal to the ENUV terminal to GND as shown in Figure 26. When an undervoltage or input power fail event is
detected, the internal FET is quickly turned off, and FLT is asserted. If the undervoltage lockout function is not
needed, the ENUV pin should be connected to the IN terminal. The ENUV terminal should not be left floating.
TPS25921 also implements internal undervoltage lockout (UVLO) circuitry on the IN pin. The device gets
disabled when the IN terminal voltage falls below internal UVLO Threshold V(UVF).
Figure 26. UVLO and OVP Thresholds Set By R1, R2and R3
9.3.2 Overvoltage Protection (OVP)
TPS25921 incorporates circuits to protect the system during overvoltage conditions. A resistor divider, connected
from the supply to OVP terminal to GND (as shown in Figure 26), programs the overvoltage threshold. A voltage
more than V(OVPR) on the OVP pin turns off the internal FET and protects the downstream load. This pin should
be tied to GND when not used.
9.3.3 Hot Plug-in and In-Rush Current Control
TPS25921 is designed to control the in-rush current upon insertion of a card into a live backplane or other "hot"
power source. This limits the voltage sag on the backplane’s supply voltage and prevents unintended resets of
the system power. A slew rate controlled startup (SS) also helps to eliminate conductive and radiated
interference. An external capacitor from the SS pin to GND defines the slew rate of the output voltage at power-
on (as shown in Figure 27). The equation governing slew rate at start-up is shown in Equation 1 :
Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: TPS25921A TPS25921L
l TEXAS INSTRUMENTS dV< dl="" i="" 4="" )="" v="" i(="" 7‘="" ss="" ilimit="" '3="" (ilim)="" 8="" \l="" 40.018="" 10.73="" x10="">
LIMIT
(ILIM) -3
I + 0.018
R =
10.73 x 10
-3
LIMIT (ILIM)
I = 10.73 x 10 x R - 0.018
(IN)
(INRUSH) (OUT) SS
V
= C x t
I
( )
4
SS (IN) (SS)
= 20.6 x 10 x V x C + 70 pFt
(OUT)
dV
dt
(SS) (INT) (OUT)
(SS) (SS)
(C + C ) dV
= x
Gain dt
I
GND
TPS25921x
SS
1 PA
SWEN
70 :
C(SS)
C(INT)
TPS25921A
,
TPS25921L
SLVSCE1C –AUGUST 2014–REVISED NOVEMBER 2015
www.ti.com
Feature Description (continued)
Figure 27. Output Ramp Up Time tdVdT is Set by C(dVdT)
(1)
Where:
• I(SS) = 1 µA (typical)
space
• = Desired output slew rate
• GAIN(SS) =ΔV(OUT)/ΔV(SS) gain = 4.85
The total ramp time (tSS) of V(OUT) for 0 to V(IN) can be calculated using Equation 2:
(2)
Where C(ss) is in Farad.
The inrush current, I(INRUSH) can be calculated as
(3)
The SS pin can be left floating to obtain a predetermined slew rate (tSS) on the output. When terminal is left
floating, the device sets an internal ramp rate of ~50V/ms for output (V(OUT)) ramp.
Figure 36 and Figure 37 illustrate the inrush current control behavior of the device. For systems where load is
present during start-up, the current never exceeds the overcurrent limit set by R(ILIM) resistor for the application.
For defining appropriate charging time/rate under different load conditions, refer to the Setting Output Voltage
Ramp time (tSS)section.
9.3.4 Overload and Short Circuit Protection :
At all times load current is monitored by sensing voltage across an internal sense resistor. During overload
events, current is limited to the current limit (ILIMIT) programmed by R(ILIM) resistor
(4)
(5)
• ILIMIT is overload current limit in Ampere
• R(ILIM) is the current limit programming resistor in kΩ
TPS25921 incorporates two distinct overcurrent protection levels: the current limit (ILIMIT) and the fast-trip
threshold (I(FASTRIP)). The fast trip and current limit operations are shown in Figure 28.
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Product Folder Links: TPS25921A TPS25921L
l TEXAS INSTRUMENTS
Current (A)
I(FASTRIP)
ILIMIT
IOS
Thermal Foldback
1-20%
I(FASTRIP) = 1.42 x 10-2 x R(ILIM) + 0.36
-2
(FASTRIP) (ILIM)
I = 1.42 x 10 x R + 0.36
TPS25921A
,
TPS25921L
www.ti.com
SLVSCE1C –AUGUST 2014–REVISED NOVEMBER 2015
Feature Description (continued)
Bias current on ILIM pin directly controls current-limiting behavior of the device, and PCB routing of this node
must be kept away from any noisy (switching) signals.
9.3.4.1 Overload Protection
For overload conditions, the internal current-limit amplifier regulates the output current to ILIMIT. The output
voltage droops during current limit regulation, resulting in increased power dissipation in the device. If the device
junction temperature reaches the thermal shutdown threshold (T(TSD)), the internal FET is turned off. Once in
thermal shutdown, The TPS25921L version stays latched off, whereas TPS25921A commences an auto-retry
cycle tTSD(dly) ms after TJ< [T(TSD) - 20°C]. During thermal shutdown, the fault pin FLT pulls low to signal a fault
condition. Figure 40 and Figure 41 illustrate overload behavior.
9.3.4.2 Short Circuit Protection
During a transient short circuit event, the current through the device increases very rapidly. As current-limit
amplifier cannot respond quickly to this event due to its limited bandwidth, the device incorporates a fast-trip
comparator, with a threshold I(FASTRIP). When the current through the internal FET exceeds I(FASTRIP) (I(OUT) >
I(FASTRIP)), this comparator shuts down the pass device within 3 µs and terminates the rapid short-circuit peak
current. The I(FASTRIP) threshold is dependent on programmed overload current limit and function of R(ILIM). See
Equation 6 for the calculation.
where
• I(FASTRIP) is fast trip current limit in Ampere
• R(ILIM) is the current limit resistor in kΩ(6)
The fast-trip circuit holds the internal FET off for only a few microseconds, after which the device attempts to turn
back on normally, allowing the current-limit loop to regulate the output current to ILIMIT. Then, device behaves
similar to overload condition. Figure 42 through Figure 44 illustrate the behavior of the system when the current
exceeds the fast-trip threshold.
9.3.4.3 Start-Up with Short on Output
During start-up into a short circuit current is limited to ILIMIT.Figure 45 and Figure 46 illustrate start-up with a
short on the output. This feature helps in quick fault isolation and hence ensures stability of the DC bus.
9.3.4.4 Constant Current Limit Behavior during Overcurrent Faults
When power dissipation in the internal FET [PD= (V(IN) - V(OUT)) × I(OUT)] > 2 W, there is a ~1 to 20 % thermal fold
back in the current limit value so that the regulated current drops from ILIMIT to IOS. Eventually, the device shuts
down due to over temperature.
Figure 28. Overcurrent Protection Levels
Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: TPS25921A TPS25921L
l TEXAS INSTRUMENTS
( )
(OUT) (IN) DS(ON) (OUT)
V = V - R x I
TPS25921A
,
TPS25921L
SLVSCE1C –AUGUST 2014–REVISED NOVEMBER 2015
www.ti.com
Feature Description (continued)
9.3.5 FAULT Response
The FLT open-drain output is asserted (active low) during undervoltage, overvoltage and thermal shutdown
conditions. The FLT signal remains asserted until the fault condition is removed and the device resumes normal
operation. During thermal shutdown, TPS25921L version stays latched off, whereas TPS25921A commences an
auto-retry cycle tTSD(dly) millisecond after TJ< [T(TSD) - 20°C]. For TPS25921L, thermal fault latch can be reset by
cycling the ENUV pin below V(ENF_RST) threshold. A nuisance fast trip does not trigger fault.
Connect FLT with a pull up resistor to Input or Output voltage rail. FLT may be left open or tied to ground when
not used.
9.3.6 IN, OUT and GND Pins
The IN pin should be connected to the power source. A ceramic bypass capacitor close to the device from IN to
GND is recommended to alleviate bus transients. The recommended operating voltage range is 4.5 V – 18 V.
The OUT pin should be connected to the load. V(OUT) in the ON condition, is calculated using the Equation 7
(7)
where, RDS(ON) is the ON resistance of the internal FET.
GND terminal is the most negative voltage in the circuit and is used as a reference for all voltage reference
unless otherwise specified.
9.3.7 Thermal Shutdown:
Internal over temperature shutdown disables/turns off the FET when TJ> 155°C (typical). The TPS25921L
version latches off the internal FET, whereas TPS25921A commences an auto-retry cycle tTSD(dly) milliseconds
after TJdrops below [T(TSD) - 20°C]. During the thermal shutdown, the fault pin FLT is pulled low to signal a fault
condition.
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Product Folder Links: TPS25921A TPS25921L
l TEXAS INSTRUMENTS
R1
R2
IN
ENUV
GND
TPS25921x
V(IN)
+EN
1.39V
1.34V
from µC
TPS25921A
,
TPS25921L
www.ti.com
SLVSCE1C –AUGUST 2014–REVISED NOVEMBER 2015
9.4 Device Functional Modes
9.4.1 Shutdown Control
The internal FET and hence the load current can be remotely switched off by taking the ENUV pin below its 1.34
V threshold with an open collector or open drain device as shown in Figure 29. Upon releasing the ENUV pin the
device turns on with soft-start cycle.
Figure 29. Shutdown Control
9.4.2 Operational Overview of Device Functions
The device functionality for various conditions are shown in Table 1.
Table 1. Operational Overview of Device Functions
Device TPS25921
Inrush ramp controlled by capacitor at SS pin
Start Up Inrush limited to ILIMIT level as set by R(ILIM)
If TJ> T(TSD) device shuts off
Current is limited to I(LIM) level as set by R(ILIM)
Power dissipation increases as V(IN) - V(OUT) grows
Overcurrent Response Device turns off when TJ> T(TSD)
‘L' Version remains off
'A' Version will attempt restart tTSD(dly) ms after TJ< [T(TSD) -20°C]
Fast shut off when I(LOAD) > I(FASTRIP)
Short-Circuit Response Quick restart and current limited to ILIMIT, follows standard startup cycle
Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: TPS25921A TPS25921L
CIN
0.1µF COUT
100µF
CSS
1nF
R1
470kO
R2
53kO
R3
47kO
90mO
IN OUT
ENUV
SS
GND TPS25921x
ILIM
OVP
R4
4.5 to 18 V V(OUT)
RILIM
95.3kO
(Note 1)
V(IN)
Fault Monitor
FLT
TPS25921A
,
TPS25921L
SLVSCE1C –AUGUST 2014–REVISED NOVEMBER 2015
www.ti.com
10 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TPS25921x is a smart eFuse. It is typically used for Hot-Swap and Power rail protection applications. It
operates from 4.5 V to 18 V with programmable current limit, overvoltage and undervoltage protection. The
device aids in controlling the in-rush current and provides precise current limiting during overload conditions for
systems such as White Goods, Set-Top-Box, DTVs, Gaming Consoles, SSDs/HDDs and Smart Meters. The
device also provides robust protection for multiple faults on the sub-system rail.
Alternatively, the WEBENCH® software may be used to generate a complete design. The WEBENCH® software
uses an iterative design procedure and accesses a comprehensive database of components when generating a
design. Additionally, a spreadsheet design tool TPS25921 Design Calculator is available on web folder.
10.2 Typical Application
10.2.1 Precision Current Limiting and Protection for White Goods
(1) CIN: Optional and only for noise suppression.
Figure 30. Typical Application Schematics: eFuse for White Goods
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Product Folder Links: TPS25921A TPS25921L
l TEXAS INSTRUMENTS R( 1 + 0.018 Q 10 73 x 10 R V ( 1 2 3 ) R R
2 3
(ENR) (UV)
1 2 3
R R
V x V
R R R
+
=
+ +
3
(OVPR) (OV)
1 2 3
R
V x V
R R R
=
+ +
(ILIM) -3
1 + 0.018
R = = 94.8 k
10.73 x 10
W
TPS25921A
,
TPS25921L
www.ti.com
SLVSCE1C –AUGUST 2014–REVISED NOVEMBER 2015
Typical Application (continued)
10.2.1.1 Design Requirements
For this design example, use the parameters shown in Table 2.
Table 2. Design Parameters
DESIGN PARAMETER EXAMPLE VALUE
Input voltage range, V(IN) 12 V
Undervoltage lockout set point, V(UV) 8 V
Overvoltage protection set point , V(OV) 17 V
Load at Start-Up , RL(SU) 24 Ω
Current limit, ILIMIT 1 A
Load capacitance , C(OUT) 100 µF
Maximum ambient temperatures , TA85°C
10.2.1.2 Detailed Design Procedure
The following design procedure can be used to select component values for the TPS25921A and TPS25921L.
10.2.1.2.1 Step by Step Design Procedure
To begin the design process a few parameters must be decided upon. The designer needs to know the following:
• Normal input operation voltage
• Maximum output capacitance
• Maximum current Limit
• Load during start-up
• Maximum ambient temperature of operation
This design procedure below seeks to control the junction temperature of device under both static and transient
conditions by proper selection of output ramp-up time and associated support components. The designer can
adjust this procedure to fit the application and design criteria.
10.2.1.2.2 Programming the Current-Limit Threshold: R(ILIM) Selection
The R(ILIM) resistor at the ILIM pin sets the over load current limit, this can be set using Equation 5.
(8)
Choose closest standard value: 95.3 kΩ, 1% standard value resistor.
10.2.1.2.3 Undervoltage Lockout and Overvoltage Set Point
The undervoltage lockout (UVLO) and overvoltage trip point are adjusted using the external voltage divider
network of R1, R2and R3as connected between IN, ENUV, OVP and GND pins of the device. The values
required for setting the undervoltage and overvoltage are calculated solving Equation 9 and Equation 10.
(9)
(10)
For minimizing the input current drawn from the power supply {I(R123) = V(IN)/(R1+ R2+ R3)}, it is recommended to
use higher values of resistance for R1, R2and R3.
However, leakage currents due to external active components connected to the resistor string can add error to
these calculations. So, the resistor string current, I(R123) must be chosen to be 20x greater than the leakage
current expected.
Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: TPS25921A TPS25921L
l TEXAS INSTRUMENTS SS PonNRUsH) 0-5 X VuN) x ‘(INRUSH)
D(INRUSH) (IN) (INRUSH)
P 0.5 x V x I=
(IN)
(INRUSH) (OUT) SS
V
dV
I C x I C x
dT t
= => =
0
2
4
6
8
10
12
14
0
1
2
3
4
5
6
7
0 20 40 60 80 100
Output Voltage (V)
Input Current (A), Power Dissipation (W)
Start-Up Time, tSS (%)
Input Current
Power Dissipation
Output Voltage
C013
TPS25921A
,
TPS25921L
SLVSCE1C –AUGUST 2014–REVISED NOVEMBER 2015
www.ti.com
From the device electrical specifications, V(OVPR) = 1.40 V and V(ENR) = 1.40 V. For design requirements, V(OV) is
17 V and V(UV) is 8 V. To solve the equation, first choose the value of R3= 47 kΩand use Equation 9 to solve for
(R1+ R2) = 523.71 kΩ. Use Equation 10 and value of (R1+ R2) to solve for R2= 52.88 kΩand finally R1= 470.83
kΩ.
Using the closest standard 1% resistor values gives R1= 470 kΩ, R2= 53 kΩ, and R3= 47 kΩ.
The power failure threshold is detected on the falling edge of supply. This threshold voltage is 4% lower than the
rising threshold, V(UV). This is calculated using Equation 11.
V(PFAIL) = 0.96 x V(UV) (11)
Power fail threshold set is : 7.68 V
10.2.1.2.4 Setting Output Voltage Ramp time (tSS)
For a successful design, the junction temperature of device should be kept below the absolute-maximum rating
during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of
magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush
current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.
The ramp-up capacitor C(SS) needed is calculated considering the two possible cases:
10.2.1.2.4.1 Case1: Start-up Without Load: Only Output Capacitance C(OUT) Draws Current During Start-up
During start-up, as the output capacitor charges, the voltage difference across the internal FET decreases, and
the power dissipated decreases as well. Typical ramp-up of output voltage V(OUT) with inrush current limit of 0.5A
and power dissipated in the device during start-up is shown in Figure 31. The average power dissipated in the
device during start-up is equal to area of triangular plot (red curve in Figure 32) averaged over tSS.
V(IN) = 12 V C(SS) = 1 nF C(OUT)=100 µF
V(IN) = 12 V C(SS) = 1 nF C(OUT)=100 µF
Figure 32. PD(INRUSH) Due to Inrush Current
Figure 31. Start-up Without Load
For TPS25921 device, the inrush current is determined as,
(12)
Power dissipation during start-up is:
(13)
Equation 13 assumes that load does not draw any current until the output voltage has reached its final value.
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Product Folder Links: TPS25921A TPS25921L
TEXAS INSTRUMENTS PD , PmsTAR'ruP) PouNRUsH) * F’mLoAD) '(STARTUP) ‘(wRusm + IL“!
(LIMIT) (INRUSH)
SS(current-limited) (OUT) L(SU) (IN)
(INRUSH) (LIMIT) L(SU)
I I
t C x R x 1 LN V
IIR
é ù
æ ö
÷
ç
ê ú
÷
ç÷
ç
ê ú
÷
ç÷
ê ú
ç÷
ç÷
= - +
ê ú
÷
ç÷
ç
ê ú
÷
ç÷
ç-
ê ú
÷
ç÷
ê ú
ç÷
ç
è ø
ë û
(STARTUP) (INRUSH) L
I I + I (t)=
D(STARTUP) D(INRUSH) D(LOAD)
P P + P=
2(IN)
D(LOAD) L(SU)
V
1
P x
6 R
æ ö
÷
ç
=÷
ç÷
÷
ç
è ø
0
2
4
6
8
10
12
14
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0 10 20 30 40 50 60 70 80 90 100
Load Current (A), Power Dissipation (W)
Start-Up Time, tSS (%)
Power Dissipation
Load Current
Output Voltage
C013
tss (IN)
t (IN) SS L(SU) SS
0
V
t t
W V x 1 - x x dt
t R t
æ ö
æ ö ÷
ç
÷
ç÷
ç
÷
= ç ÷
ç
÷÷
ç÷ç
÷
ç÷
÷
ç
è ø è ø
ò
(IN)
LL(SU) SS
Vt
I (t) x
R t
æ ö
÷
ç÷
ç
=÷
ç÷
ç÷
÷
ç
è ø
I O (IN) SS
t
(V V )(t) V x 1 t
æ ö
÷
ç÷
- = ç - ÷
ç÷
÷
ç
è ø
TPS25921A
,
TPS25921L
www.ti.com
SLVSCE1C –AUGUST 2014–REVISED NOVEMBER 2015
10.2.1.2.4.2 Case 2: Start-up With Load: Output Capacitance C(OUT) and Load Draws Current During Start-up
When load draws current during the turn-on sequence, there will be additional power dissipated. Considering a
resistive load RL(SU) during start-up, load current ramps up proportionally with increase in output voltage during
tSS time. Typical ramp-up of output voltage, load current and power dissipation in the device is shown in
Figure 33 and power dissipation with respect to time is plotted in Figure 34. The additional power dissipation
during start-up phase is calculated as follows.
(14)
(15)
Where RL(SU) is the load resistance present during start-up. Average energy loss in the internal FET during
charging time due to resistive load is given by:
(16)
V(IN) = 12 V C(SS) = 1 nF RL(SU) = 24 Ω
V(IN) = 12 V C(SS) = 1 nF , RL(SU) = 24 Ω
C(OUT)=100 µF
Figure 34. PD(LOAD) in Device during Start-up with Load
Figure 33. Start-up With Load
On solving Equation 16 the average power loss in the internal FET due to load is:
(17)
Total power dissipated in the device during startup is:
(18)
Total current during startup is given by:
(19)
If I(STARTUP) > ILIMIT, the device limits the current to ILIMIT and the current limited charging time is determined by:
(20)
The power dissipation, with and without load, for selected start-up time should not exceed the shutdown limits as
shown in Figure 35.
Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 21
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l TEXAS INSTRUMENTS IUDOOU I( ( ) [2.5mm J A PD(INRUSH) W PD E 24 W PD(STARTUP) W I ( ¥ ) 5 '< (="">anwa J PD(INRUSH) W PD E 24 PD(STARTUP) W
D(STARTUP) = 0.61 1 = 1.61 WP+
D(LOAD)
1 12 x 12
= x = 1 W
6 24
Pæ ö æ ö
ç ÷ ç ÷
è ø è ø
D(INRUSH) = 0.5 x 12 x 0.102 = 0.61 WP
()
-6
(INRUSH) -3
12
= 100 x 10 x = 0.102 A
11.8 x 10
Iæ ö
ç ÷
è ø
()
4 9 12
SS = 20.6 x 10 x 12 x 4.7 x 10 + 70 x 10 = 11.8 mst- -
D(STARTUP) = 2.72 1 = 3.72 WP+
D(LOAD)
1 12 x 12
= x = 1 W
6 24
Pæ ö æ ö
ç ÷ ç ÷
è ø è ø
D(INRUSH) = 0.5 x 12 x 0.454 = 2.72 WP
()
-6
(INRUSH) -3
12
= 100 x 10 x = 0.454 A
2.64 x 10
Iæ ö
ç ÷
è ø
()
4 9 12
SS = 20.6 x 10 x 12 x 1 x 10 + 70 x 10 2.64 mst- - =
0.1
1
10
100
1000
10000
100000
0.1 1 10 100
Thermal Shutdown Time (ms)
Power Dissipation (W)
-40C
25C
85C
125C
C014
TA= -40oC
TA= 25oC
TA= 85oC
TA= 125oC
TPS25921A
,
TPS25921L
SLVSCE1C –AUGUST 2014–REVISED NOVEMBER 2015
www.ti.com
Figure 35. Thermal Shutdown Limit Plot
For the design example under discussion,
Select ramp-up capacitor C(SS) = 1nF, using Equation 2.
(21)
The inrush current drawn by the load capacitance (C(OUT)) during ramp-up using Equation 3.
(22)
The inrush Power dissipation is calculated, using Equation 13.
(23)
For 2.72 W of power loss, the thermal shut down time of the device should not be less than the ramp-up time tSS
to avoid the false trip at maximum operating temperature. From thermal shutdown limit graph Figure 35 at
TA= 85°C, for 2.72 W of power the shutdown time is ~170 ms. So it is safe to use 2.64 ms as start-up time
without any load on output.
Considering the start-up with load 24 Ω, the additional power dissipation, when load is present during start up is
calculated, using Equation 17.
(24)
The total device power dissipation during start up is:
(25)
From thermal shutdown limit graph at TA= 85°C, the thermal shutdown time for 3.72 W is close to 60 ms. It is
safe to have 30% margin to allow for variation of system parameters such as load, component tolerance, and
input voltage. So it is well within acceptable limits to use the 1 nF capacitor with start-up load of 24 Ω.
If there is a need to decrease the power loss during start-up, it can be done with increase of C(SS) capacitor.
To illustrate, choose C(SS) = 4.7 nF as an option and recalculate:
(26)
(27)
(28)
(29)
(30)
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Product Folder Links: TPS25921A TPS25921L
*9 TEXAS INSTRUMENTS
TPS25921A
,
TPS25921L
www.ti.com
SLVSCE1C –AUGUST 2014–REVISED NOVEMBER 2015
From thermal shutdown limit graph at TA= 85°C, the shutdown time for 1.61 W power dissipation is ~1000 ms,
which increases the margins further for shutdown time and ensures successful operation during start up and
steady state conditions.
The spreadsheet tool available on the web can be used for iterative calculations.
10.2.1.2.5 Support Component Selections - R4and CIN
Reference to application schematics, R4is required only if FLT is used; The resistor serves as pull-up for the
open-drain output driver. The current sunk by this pin should not exceed 100 mA (refer to the Absolute Maximum
Ratings table). CIN is a bypass capacitor to help control transient voltages, unit emissions, and local supply noise.
Where acceptable, a value in the range of 0.001 μF to 0.1 μF is recommended for C(IN).
10.2.1.3 Application Curves
Figure 36. Hot-Plug Start-Up: Output Ramp Without Load Figure 37. Hot-Plug Start-Up: Output Ramp With 24 ΩLoad
on Output at Start Up
Figure 38. Overvoltage Shutdown Figure 39. Overvoltage Recovery
Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: TPS25921A TPS25921L
l TEXAS INSTRUMENTS
TPS25921A
,
TPS25921L
SLVSCE1C –AUGUST 2014–REVISED NOVEMBER 2015
www.ti.com
Figure 40. Over Load: Step Change in Load from 19 Ωto Figure 41. Overload Condition: Auto Retry and Recovery -
TPS25921A
9ΩBack
Figure 42. Hot Short: Fast Trip and Current Regulation Figure 43. Hot Short: Latched - TPS25921L
Figure 44. Hot Short: Auto-Retry and Recovery from Short Figure 45. Hot Plug-in with Short on Output: Latched -
Circuit - TPS25921A TPS25921L
24 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated
Product Folder Links: TPS25921A TPS25921L
l TEXAS INSTRUMENTS
TPS25921A
,
TPS25921L
www.ti.com
SLVSCE1C –AUGUST 2014–REVISED NOVEMBER 2015
Figure 46. Hot Plug-in with Short on Output: Auto-Retry - TPS25921A
10.3 System Examples
The TPS25921 provides a simple solution for current limiting, inrush current control and supervision of power
rails for wide range of applications operating at 4.5 V to 18 V and delivering up to 1.5 A.
10.3.1 Protection and Current Limiting for Primary-Side Regulated Power Supplies
Primary side regulated power supplies and adapters are dominant today in many of the applications such as
Smart-phones, Portable hand-held devices, White Goods, Set-Top-Box and Gaming consoles. These supplies
provide efficient, low cost and low component count solutions for power needs ranging from 5W to 30W. But,
these come with drawbacks of
• No secondary side protection for immediate termination of critical faults such as short circuit and over voltage
• Do not provide precise current limiting for overload transients
• Have poor output voltage regulation for sudden change in AC input voltages - triggering output overvoltage
condition
Many of the above applications require precise output current limiting and secondary side protection, driving the
need for current sensing in the secondary side. This needs additional circuit implementation using precision
operational amplifiers. This increases the complexity of the solution and also results in sensing losses The
TPS25921 with its integrated low-ohmic N-channel FET provides a simple and efficient solution. Figure 47 shows
the typical implementation using TPS25921.
Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: TPS25921A TPS25921L
l TEXAS INSTRUMENTS
Rectifier + Noise
Filter
CB
UCC287xx
Primary Regulated
Fly-back Controller
Rs
CO
R2
R1
RILIM
OVP ILIM
TPS25921
VAC(IN) V(OUT)
VDC
TPS25921A
,
TPS25921L
SLVSCE1C –AUGUST 2014–REVISED NOVEMBER 2015
www.ti.com
System Examples (continued)
Figure 47. Current Limiting and Protection for AC-DC Power Supplies
During short circuit conditions, the internal fast comparator of TPS25921 turns OFF the internal FET in less than
3 µs (typical) as soon as current exceeds I(FASTRIP), set by the current limit R(ILIM) resistor. The OVP comparator
with 3% precision helps in quick isolation of the load from the input when inputs exceeds the set V(OVPR)
Figure 42 and Figure 38 shows short circuit and overvoltage response waveforms of implementation using
TPS25921. In addition to above, the TPS25921 provides inrush current limit when output is hot-plugged into any
of the system loads.
10.3.2 Precision Current Limiting in Intrinsic Safety Applications
Intrinsic safety (IS) is becoming prominent need for safe operation of electrical and electronic equipment in
hazardous areas. Intrinsic safety requires that equipment is designed such that the total amount of energy
available in the apparatus is simply not enough to ignite an explosive atmosphere. The energy can be electrical,
in the form of a spark, or thermal, in the form of a hot surface.
This calls for precise current limiting and precision shutdown of the circuit for over voltage conditions ensuring
that set voltage and current limits are not exceeded for wide operating temperature range and variable
environmental conditions. Applications such as Gas Analyzers, Medical equipment (such as
electrocardiographs), Portal Industrial Equipment, Cabled Power distribution systems and hand-held motor
operated tools need to meet these critical safety standards.
The TPS25921 device can be used as simple protection solution for each of the internal rails. Figure 48 shows
the typical implementation using TPS25921.
26 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated
Product Folder Links: TPS25921A TPS25921L
RILIM
OVP ILIM
TPS25921
R1
R2
V(IN) Load
EN
R1
R2
Q2
CsOver Current
Protection
V(IN) Load
Enable
Disable
Q2
UVLO
OVP
Enable
CB
Sync Buck
DC-DC Converter
CO
R2
R1
RILIM
OVP ILIM
TPS25921
V(IN) V(OUT)
LO
CB
LDO
CO
R2
R1
RILIM
OVP ILIM
TPS25921
V(IN) V(OUT)
TPS25921A
,
TPS25921L
www.ti.com
SLVSCE1C –AUGUST 2014–REVISED NOVEMBER 2015
System Examples (continued)
Figure 48. Precision current Limit and Protection of Internal Rails
10.3.3 Smart Load Switch
A smart load switch is a series FET used for switching of the load (resistive or inductive). It also provides
protection during fault conditions. Typical discrete implementation is shown in Figure 49. Discrete solutions have
higher component count and require complex circuitry to implement each of the protection fault needs.
TPS25921 can be used as a smart power switch for applications ranging from 4.5 V to 18 V. TPS25921 provides
programmable soft start, programmable current limits, over-temperature protection, a fault flag, and under-
voltage lockout.
Figure 49. Smart Load Switch Implementation
Figure 49 shows typical implementation and usage as load switch. This configuration can be used for driving a
solenoid and FAN control. It is recommended to use a freewheeling diode across the load when load is highly
inductive.
Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: TPS25921A TPS25921L
l TEXAS INSTRUMENTS
(IN)
SPIKE(Absolute) (IN) (LOAD) (IN)
L
V V + I x C
=
TPS25921A
,
TPS25921L
SLVSCE1C –AUGUST 2014–REVISED NOVEMBER 2015
www.ti.com
System Examples (continued)
Figure 50 shows load switching waveforms using TPS25921 for 12 V Bus
Figure 50. Smart Load Switch (100 Hz Operation)
11 Power Supply Recommendations
The device is designed for supply voltage range of 4.5 V ≤VIN ≤18 V. If the input supply is located more than a
few inches from the device an input ceramic bypass capacitor higher than 0.1 μF is recommended. Power supply
should be rated higher than the current limit set to avoid voltage droops during over current and short-circuit
conditions.
11.1 Transient Protection
In case of short circuit and over load current limit, when the device interrupts current flow, input inductance
generates a positive voltage spike on the input and output inductance generates a negative voltage spike on the
output. The peak amplitude of voltage spikes (transients) is dependent on value of inductance in series to the
input or output of the device. Such transients can exceed the Absolute Maximum Ratings of the device if steps
are not taken to address the issue.
Typical methods for addressing transients include
• Minimizing lead length and inductance into and out of the device
• Using large PCB GND plane
• Schottky diode across the output to absorb negative spikes
• A low value ceramic capacitor (C(IN) = 0.001 µF to 0.1 µF) to absorb the energy and dampen the transients.
The approximate value of input capacitance can be estimated with Equation 31.
(31)
Where:
• V(IN) is the nominal supply voltage
• I(LOAD) is the load current,
• L(IN) equals the effective inductance seen looking into the source
• C(IN) is the capacitance present at the input
Some applications may require the addition of a Transient Voltage Suppressor (TVS) to prevent transients from
exceeding the Absolute Maximum Ratings of the device.
The circuit implementation with optional protection components (a ceramic capacitor, TVS and schottky diode) is
shown in Figure 51.
28 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated
Product Folder Links: TPS25921A TPS25921L
90mO
IN OUT
ENUV
SS
GND TPS25921x
ILIM
OVP
4.5 to 18 V
IN
FLT
OUT
CIN
(Note 1)
(Note 1)(Note 1)
TPS25921A
,
TPS25921L
www.ti.com
SLVSCE1C –AUGUST 2014–REVISED NOVEMBER 2015
Transient Protection (continued)
(1) Optional components needed for suppression of transients
Figure 51. Circuit Implementation With Optional Protection Components
11.2 Output Short-Circuit Measurements
It is difficult to obtain repeatable and similar short-circuit testing results. Source bypassing, input leads, circuit
layout and component selection, output shorting method, relative location of the short, and instrumentation all
contribute to variation in results. The actual short itself exhibits a certain degree of randomness as it
microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do
not expect to see waveforms exactly like those in the data sheet; every setup differs.
Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Links: TPS25921A TPS25921L
I TFJms INSTRUMENTS
Via to top layer ground plane (only for two layer board)
Top layer
Bottom Layer: GND plane (Optional)
Input
GND
SS
ENUV
IN
OVP
ILIM
OUT
1
2
3
4
8
7
6FLT
5
Output
Ground
(Note 1)
(Note 1)
TPS25921A
,
TPS25921L
SLVSCE1C –AUGUST 2014–REVISED NOVEMBER 2015
www.ti.com
12 Layout
12.1 Layout Guidelines
• For all applications, a 0.01-uF or greater ceramic decoupling capacitor is recommended between IN terminal
and GND. For hot-plug applications, where input power path inductance is negligible, this capacitor can be
eliminated/minimized.
• The optimum placement of decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
GND terminal of the IC. See Figure 52 for a PCB layout example.
• High current carrying power path connections should be as short as possible and should be sized to carry at
least twice the full-load current.
• The GND terminal must be tied to the PCB ground plane at the terminal of the IC. The PCB ground should be
a copper plane or island on the board.
• Locate all TPS25921x support components: R(ILIM), CSS, and resistors for FLT, ENUV and OVP, close to their
connection pin. Connect the other end of the component to the GND pin of the device with shortest trace
length.
• The trace routing for the RILIM and CSS components to the device should be as short as possible to reduce
parasitic effects on the current limit and soft start timing. These traces should not have any coupling to
switching signals on the board.
• OVP and ENUV signal traces should be routed with sufficient spacing from FLT signal trace, to avoid
spurious coupling of FLT switching, during fault conditions.
• Protection devices such as TVS, snubbers, capacitors, or diodes should be placed physically close to the
device they are intended to protect, and routed with short traces to reduce inductance. For example, a
protection Schottky diode is recommended to address negative transients due to switching of inductive loads,
and it should be physically close to the OUT pins.
• Obtaining acceptable performance with alternate layout schemes is possible; however this layout has been
shown to produce good results and is intended as a guideline.
12.2 Layout Example
(1) Optional: Needed only to suppress the transients caused by inductive load switching.
Figure 52. Board Layout
30 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated
Product Folder Links: TPS25921A TPS25921L
l TEXAS INSTRUMENTS
TPS25921A
,
TPS25921L
www.ti.com
SLVSCE1C –AUGUST 2014–REVISED NOVEMBER 2015
13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
TPS25921A Click here Click here Click here Click here Click here
TPS25921L Click here Click here Click here Click here Click here
13.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Links: TPS25921A TPS25921L
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS25921AD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 25921A
TPS25921ADR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 25921A
TPS25921LD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 25921L
TPS25921LDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 25921L
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS ’ I+K0 '«PI» Reel Diame|er AD Dimension deSIgned Io accommodate me componem wIdIh E0 Dimension deSIgned Io eecommodaIe me componenI Iengm KO Dlmenslun desIgned to accommodate me componem Ihlckness 7 w OvereII wmm OHhe earner cape i p1 Pitch between successwe cavIIy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O SprockeIHoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS25921ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS25921LDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS25921ADR SOIC D 8 2500 340.5 336.1 25.0
TPS25921LDR SOIC D 8 2500 340.5 336.1 25.0
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 2
l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width 47 — B - Alignment groove width
TUBE
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TPS25921AD D SOIC 8 75 507 8 3940 4.32
TPS25921LD D SOIC 8 75 507 8 3940 4.32
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 3
‘J
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
Yl“‘+
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
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