This slide shows a high level block diagram for the KSZ8873. The basic configuration is for the KSZ8873MLL, where the M stands for the MII interface at port 3 and the two L’s stand for the two PHYs at port 1 and port 2. At port 1, designers have the option to have the MAC interface output directly (the KSZ8873MML part) instead of through the PHY. Also, instead of the MII interface, Microchip can also provide a configuration which supports the RMII interface (part # KSZ8873RLL). Besides the three ethernet interfaces, these devices also support the SPI and I²C interfaces. The MII management interface and the serial management interface can be supported as well.