i.MX RT500 Crossover MCUs

Product Highlights > i.MX RT500 Crossover MCUs

            i.MX RT500 Crossover MCUs
                    NXP's crossover MCU's battery-saving features and vivid 2D graphics are ideal for portable HMI applications
    

Image of NXP's i.MX RT500 Crossover MCUs NXP's i.MX RT500 crossover MCUs are part of the EdgeVerse™ edge computing platform and are optimized for low-power HMI applications by combining a graphics engine and a streamlined Cadence^® Tensilica^® Fusion F1 DSP core with a next-generation Arm^® Cortex^®-M33 core. The i.MX RT500 family is part of NXP’s EdgeVerse™ edge computing platform. These devices are designed to unlock the potential of display-based applications with a secure, power-optimized embedded processor.

i.MX RT500 MCUs are part of the EdgeLock^® Assurance program, offering on-chip security capabilities and built on a foundation of secure boot, secure debug, and secure life-cycle management designed to resist remote and software local attacks.

The i.MX RT500 family of dual-core microcontrollers is designed for embedded applications featuring an Arm Cortex-M33 CPU combined with a Cadence Xtensa® Fusion F1 audio digital signal processor CPU. The Cortex-M33 includes two hardware coprocessors, providing enhanced performance for an array of complex algorithms along with a 2D vector GPU with LCD interface and MIPI DSI PHY. The family offers a rich set of peripherals and very low power consumption. The device has up to 5 MB SRAM, two FlexSPIs (octal/quad SPI Interfaces) each with 32 KB cache (one with dynamic decryption), high-speed USB device/host + PHY, 12-bit 1 MS/s ADC, analog comparator, audio subsystems supporting up to eight DMIC channels, 2D GPU and LCD controller with MIPI DSI PHY, SDIO/eMMC; FlexIO; AES/SHA/Crypto M33 coprocessor, and PUF key generation

The i.MX RT500 hardware development starts with the i.MX RT595 EVK, which is a six-layer HDI PCB that combines the i.MX RT500 with onboard memory, connectors, and sensors. This board is compatible with Arduino shields and is supported by MCUXpresso software and tools for the Arm CM33 core and Cadence Tensilica Xplorer software and tools for the Fusion F1 DSP. Schematics and design files will be available at nxp.com. The EVK board is compatible with Arduino™ hardware shields. The EVK is also supported by a couple of displays that can be purchased separately.

MIMXRT595-EVK details

Supports i.MX RT595, RT555, and RT533 development
RT595 running at 200 MHz (Arm Cortex-M33) and 200 MHz (Fusion F1 DSP) with 2D Vector GPU
NXP PMIC with battery charger (PCA9420)
NXP 6-axis accelerometer/magnetometer (FXOS8700CQ)
Macronix Octal SPI Flash and AP memory/PSRAM memories
Audio codec with stereo line-in and line-out/headphone jack
Onboard debug probe, with VCOM and CMSIS-DAP or J-link firmware options

DMIC expansion connector supporting up to eight DMICs
Full SD card slot
Micro-A/B USB supporting host or device operation
Arduino and PMOD expansion connectors
10-pin and 20-pin SWD connectors supporting external debug/trace probes
MIPI-DSI connector and FlexIO connector for display support
Dual Knowles DMICs

Features

Rich integration
- Optional 2D GPU with display LCD controller and MIPI DSI support
- Quad/octal SPI Flash and PSRAM memory interface with on-the-fly memory decryption
- USB 2.0 high-speed host and device interface with PHY
- Up to 12 Flexcomms, configurable to SPI/I²C/UART/I²S interfaces; separate I³C and dedicated I²C for PMIC
- Up to two SD/eMMC memory card interfaces
- Digital microphone interface supporting up to eight channels
Advanced security
- Secure boot with immutable hardware root-of-trust
- SRAM physically unclonable function (PUF) based unique key storage
- Acceleration for symmetric (AES-256 and SHA2-256) and asymmetric cryptography (ECC and RSA)
- Optional fuse-based root key storage mechanism

Energy-efficient, real-time processing
- Arm Cortex-M33 running up to 200 MHz with ultra-fast real-time responsiveness
- Optional Cadence Tensilica Fusion F1 DSP running up to 200 MHz with a 32 x 32 MAC
- Cryptography and math accelerators for security and complex algorithms
- Up to 5 MB on-chip SRAM with zero wait-state access for critical code and data
Low power
- 28 nm FD-SOI process, optimized for both active and leakage power
- Low-leakage SRAM for extended battery life