Microsemi IGLOO2 Highly-integrated FPGAs

Microsemi's IGLOO®2 FPGAs, targeted at the cost-optimized FPGA market with up to 150K Logic Elements, integrate fourth generation flash-based FPGA fabric and high performance communications interfaces on a single chip. The IGLOO2 FPGAs offer a cost optimized FPGA with best-in-class feature integration coupled with the lowest power, highest reliability and most advanced security in the industry.

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IGLOO2 Evaluation Kit!

Microsemi's IGLOO2 FPGA Evaluation Kit is the lowest cost FPGA platform for developing cost-optimized FPGA designs using Microsemi's IGLOO2 FPGA, which offers best-in-class feature integration coupled with the lowest power, highest reliability and most advanced security in the industry.

The IGLOO2 Evaluation Kit makes it easy to develop transceiver I/O-based FPGA designs to build PCI Express and Gigabit Ethernet based systems. The board is also small form-factor PCIe compliant which will allow quick prototyping an evaluation using any desktop PC or laptop with a PCIe slot.

The IGLOO2 FPGA Evaluation KitM2GL-EVAL-KIT Product Page

  • Develop and test PCI Express Gen2 x1 lane designs
  • Test signal quality of the FPGA transceiver using full-duplex SERDES SMA Pairs
  • Measure the low power consumption of the IGLOO2 FPGA
  • Quickly create a working PCIe link with included PCIe Control Plane Demo and several more demos coming soon

The board includes an RJ45 interface to 10/100/1000 Ethernet, 512MB of LPDDR, 64MB SPI Flash, USB-UART connections as well as I2C, SPI and GPIO headers. The kit includes a 12V power supply but can also be powered via the PCIe edge connector. Also included is a free Gold License for the Libero SoC software toolset to enable FPGA development and to utilize the reference designs made available with the kit. A FlashPro4 JTAG programmer is also included for programming and debugging.

Kit Contents

Quantity Description
1 IGLOO2 FPGA 12K LE M2GL010T-1FGG484
1 12V Wall-Mounted Power Supply
1 FlashPro4 JTAG programmer for programming and debugging of SmartFusion2
1 USB 2.0 A male to mini-B Y-cable for UART/power interface (up to 1A) to PC
1 Quickstart Guide
1 Libero SoC Gold Software License
1 PCIe Control Plane Demo Design

Order your IGLOO2 FPGA Evaluation Kit

Hardware Feature Overview

  • 12K LE IGLOO2 FPGA in the FGG484 package (M2GL010T-1FGG484)
  • 64 Mb SPI Flash memory
  • 512 MB LPDDR
  • PCI Express Gen2 x1 interface
  • Four SMA connector for testing of full-duplex SERDES channel
  • RJ45 interface for 10/100/1000 Ethernet
  • JTAG/SPI programming interface
  • Headers for I2C, SPI, GPIOs
  • Push-button switches and LEDs for demo purposes
  • Current Measurement Test Points

Best-In-Class: Integration, Power, Reliability & Security

  • Microsemi Leadership in Cost-Optimized FPGAs
    • Highest number of 5G transceivers
    • Highest number of GPIO
    • Highest number of PCI Compliant 3.3V I/O
    • Only FPGA with hardened memory subsystem
    • Only non-volatile and instant-on mainstream FPGA
  • Microsemi Leadership in Low Power FPGAs
    • 10X lower static power with no performance penalties
    • Flash*Freeze real-time power management
  • Microsemi Leadership in Reliable FPGAs
    • Only FPGA with SEU immune fabric and mainstream features
    • Extended temperature support (Up to 125C Tj)
  • Microsemi Leadership in Secure FPGAs
    • Built-in state-of-the-art design security for all devices
    • Easy-to-use!

IGLOO2 Block Diagram

Microsemi's IGLOO2 FPGAs continue the company's focus on addressing the needs of today's cost optimized FPGA markets by providing a LUT based fabric, 5G transceivers, high speed GPIO, block RAM and DSP blocks in a differentiated, cost and power optimized architecture. This next generation IGLOO2 architecture offers up to 5X more logic density and 3X more fabric performance than its predecessors and combines a non-volatile Flash based fabric with the highest number of general purpose I/O, 5G SERDES interfaces and PCI Express end points when compared to other products in its class.

Block Diagram Picture

Acronyms

AES Advanced Encryption Standard
AHB Advanced High-Performance Bus
APB Advanced Peripheral Bus
AXI Advanced eXtensible Interface
DDR Double Data Rate
DPA Differential Power Analysis
ECC Elliptical Curve Cryptography
EDAC Error Detection and Correction
FDDR DDR2/3 controller in FPGA fabric
FIC Fabric Interface Controller		   HPMS High Performance Memory Subsystem
IAP In-Application Programming
MACC Multiply-Accumulate
MDDR DDR2/3 Controller in HPMS
SECDED Single Error Correct Double Error Detect
SEU Single Event Upset
SHA Secure Hashing Algorithm
XAUI 10 Gbps Attachment Unit Interface
XGMII 10 Gigabit Media Independent Interface
XGXS XGMII Extended Sublayer

Product FamilyView all IGLOO2 FPGAs Igloo2 FPGA Product Page

  Features M2GL005 M2GL010 M2GL025 M2GL050 M2GL090 M2GL100 M2GL150
Logic/DSP Maximum Logic Elements (4LUT + DFF)* 6,060 12,084 27,696 56,340 86,316 99,512 146,124
Math Blocks (18x18) 11 22 34 72 84 160 240
PLLs and CCCs 2 6 8
SPI/HPDMA/PDMA 1 each
Security AES256, SHA256, RNG AES256, SHA256, RNG, ECC, PUF
Memory eNVM (K Bytes) 128 256 512
LSRAM 18K Blocks 10 21 31 69 109 160 236
uSRAM1K Blocks 11 22 34 72 112 160 240
eSRAM (K Bytes) 64
Total RAM (K bits) 703 912 1104 1826 2586 3552 5000
High Speed DDR Controllers 1x18 2x36 1x18 2x36
SERDES Lanes 0 4 8 4 8 16
PCIe End Points 0 1 2 4
User I/Os MSIO (3.3V) 115 123 157 139 306 292 292
MSIOD (2.5V) 28 40 40 62 40 106 106
DDRIO (2.5V) 66 70 70 176 66 176 176
Total User I/O 209 233 267 377 412 574 574

* Total logic may vary based on utilization of DSP and memories in your design. Please see the IGLOO2 Fabric UG for details

Packaging and I/Os

Type VF400 FG484 FG676 FG896 FC1152
Pitch (mm) 0.8 1.0 1.0 1.0 1.0
Length x Width (mm) 17x17 23x23 27x27 31x31 35x35
Device I/O Lanes I/O Lanes I/O Lanes I/O Lanes I/O Lanes
M2GL005 169* - 209 -            
M2GL010(T) 195 4 233 4            
M2GL025(T) 195 4 267 4            
M2GL050(T) 207 4 267 4     377 8    
M2GL090(T)     267 4 412* 4*        
M2GL100(T)                 574 8
M2GL150(T)                 574 16

* Preliminary

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