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AD9082 MxFE® Quad 16-Bit 12 GSPS RFDAC
ADI's AD9082 bypass mode allows the full bandwidth capability of the ADC and/or DA cores to bypass the DSP datapaths
ADI's MxFE AD9082 integrates 28 nm RF data converter cores so multi-channel receive and transmit are supported. The AD9172 DAC core will be used to support a maximum of four Tx channels. The low power ADC core, AD9213, has either a 2-channel 6 GSPS observation path support or a 4-channel 4 GSPS receive path support. The data converter performance can support direct RF sampling and RF synthesis up to 4.2 GHz, thus offering an alternative wideband conversion operation for 4G and sub 6 GHz 5G. The reconfigurability aspect can support the common radio platform concept and multi-band configurations.
Features
- Flexible reconfigurable radio common platform design
- 4D2A (4 × 3 GSPS to 12 GSPS DAC and 2 × 3 GSPS to 6 GSPS ADC)
- 4D1A (4 × 3 GSPS to 12 GSPS DAC and 1 × 3 GSPS to 6 GSPS ADC)
- RF DAC/RF ADC output/input -3 dB bandwidth of 5.2 GHz and 7.5 GHz
- Transmit/receive channel bandwidth up to 1.6 GHz/3 GHz (4T2R)
- Transmit/receive channel bandwidth up to 2.4 GHz/3 GHz (2T2R)
- On-chip PLL (6 GHz to 12 GHz) with multichip synchronization; output clock provided
- External RFCLK input option
- AC performance target
- ADC test conditions (6 GSPS, -1 dBFS, fIN < 1.4 GHz)
- NSD = -154 dBFS/Hz; HD2 < -70 dBc; HD3 < -70 dBc; SFDR (excluding HD2, HD3) <-78 dBc; IL < -75 dBc
- DAC test conditions (6 GSPS, -7 dBFS, 1.8 GHz)
- NSD = -158 dBFS/Hz; SFDR < -74 dBc
- Versatile digital features
- Supports real or complex digital data (8-bit, 12-bit, or 16-bit)
- Configurable DDC/DUC
- 8 fine complex DUCs and 4 coarse complex DUCs
- 8 fine complex DDCs and 4 coarse complex DDCs
- 2 independent NCOs per DUC/DDC
- Option to bypass fine and coarse DUC/DDC
- Programmable 192-tap FIR filter
- Auxiliary features
- Fast frequency hopping
- Low latency digital loopback mode (ADC to DAC)
- ADC clock driver with selectable divide ratios
- PA downstream protection circuitry
- On-chip temperature sensor
- Flexible GPIO pins
- ADC clock driver with selectable divide ratios
- Power amplifier downstream protection circuitry
- On-chip temperature sensor
- Programmable GPIO pins
- TDD power savings option
- Serdes JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps
- 8 receive lanes for RF DAC
- 8 transmit lanes for RF AD
- 204B compatible with the maximum 15.5 Gbps lane rate
- 204C compatible with the max 24.75 Gbps lane rate
- 204C compatible with the maximum 24.75 Gbps lane rate
- Sample/bit repeat mode for receive lane rate matching
- Target typical: 6 W to 7 W
- 15 mm × 15 mm BGA with 0.8 mm pitch
- Transmit DPD support
- Fine DUC channel gain control and delay adjust
- Coarse DDC delay adjust for ADC observation path
- RxAGC support
- Fast detect with low latency for fast AGC control
- Signal monitor for slow AGC control
- Dedicated AGC support pins
Applications
- Wireless communications infrastructure
- W-CDMA, LTE, LTE-A, Massive-MIMO
- Microwave point-to-point and E-Band and 5G mmWave
- Broadband communications systems
- DOCSIS 3.0 CMTS
- Phased array radar and electronic warfare
- Electronic test and measurement systems
Evaluation Boards
| Image | Manufacturer Part Number | Description | Available Quantity | Price | View Details | |
|---|---|---|---|---|---|---|
 |  | ADS9-V2EBZ | MOTHERBOARD W/ KINTEX ULTRASCALE | 9 - Immediate | $94,114.89 | View Details |
Published: 2020-11-06
Hong Kong, China