Use Adjustable Low Leakage LDOs to Extend Battery Life in Wearable Designs

By Steven Keeping

Contributed By Digi-Key's North American Editors

Switching voltage regulators have a reputation for high efficiency, making them a popular choice in power supply designs of wearables for extending battery life. But such regulators can be electrically noisy, are complex to design in, take up a lot of space, and are relatively expensive.

In comparison, linear regulators provide a ripple-free output and are simple, compact, and inexpensive. But across a wide load range they are typically less efficient than switching regulators, impacting battery life. However, by employing a low-dropout (LDO) linear regulator (often just referred to as an “LDO”) and optimizing the device’s output to ensure it operates in its most efficient region, engineers can come near to matching the overall efficiency of a switching regulator.

However, a key problem remains: wearables are designed to spend a lot of time in low-power standby modes to preserve battery life. Even in these modes there is an appreciable internal current draw by the LDO. While small, this current draw shortens the end product’s battery life.

A new generation of LDO solutions addresses the problem. Using these devices, engineers can adjust output current and dropout voltage to minimize internal power dissipation when the wearable is in a low-power mode.

This article shows how to select an LDO to power a wearable. It then explains how a new generation of LDOs can be used to maximize efficiency without compromising the user experience.

LDO or switching regulator?

A key decision in the design process for a wearable power supply is the choice of regulator. The engineer faces the choice of a switching regulator or an LDO. Each has advantages and drawbacks, which can make the decision of which to use for a particular application tricky; see, Understanding the Advantages and Disadvantages of Linear Regulators.

Wearables bring a number of design challenges that make the selection process even harder:

  • The use of tiny batteries to aid compact design
  • A requirement for long battery life
  • The need for a stable supply to power sensitive electronics
  • Rapid wake up from a sleep state to enhance the user experience

An efficient switching regulator can address the need for battery life, but a major downside is the relatively high level of electromagnetic interference (EMI) caused by the regulator’s high frequency operation, which could upset the wearable’s sensitive microcontroller and transceiver.

This problem can be resolved by employing a switching regulator for voltage conversion and adding an LDO in series to minimize the voltage and current ripple of the device’s output. However, such a topology adds complexity and cost, and increases the size of the power supply.

An alternative approach is to use an LDO for a stable voltage supply and to maximize efficiency by choosing a device with low internal power dissipation, and by minimizing the difference between the regulator’s input and output voltages.

Calculating LDO efficiency

The efficiency of an LDO is determined by its ground current (IGND) and input and output voltages (VIN and VOUT). The formula for calculating efficiency is:

Efficiency = IOUT/(IOUT + IGND) × VOUT/VIN × 100%

IGND is the current required to operate the LDO’s internal circuits (which is the difference between the input and output currents). A key part of this is the LDO’s quiescent current (IQ), which is the current required to power the LDO’s internal circuits when the external load current is close to zero. It includes such things as the operating current of the error amplifier, output voltage divider, and overcurrent and temperature sensing circuits.

Because of their impact on efficiency, IGND and IQ are key specifications on an LDO’s datasheet. For example, a product suitable for powering a wearable, such as Microchip’s MCP1811BT-028/OT LDO, has figures of IGND = 180 microamps (µA) (at IOUT = 300 milliamps (mA)) and IQ = 250 nanoamps (nA). IQ (and therefore IGND) increases as IOUT rises. This relationship is shown clearly as it pertains to STMicroelectronics’ LDL112 (Figure 1).

Graph of load current and quiescent current for STMicroelectronics’ LDL112 LDOFigure 1: This graph clearly shows the relationship between load current and quiescent current for STMicroelectronics’ LDL112 LDO. (Image source: STMicroelectronics)

For an LDO meeting the loads typical of a wearable that is recording and transmitting data (for example, several hundred milliamps), IGND is relatively insignificant compared with IOUT, so the key factor determining efficiency becomes the voltage difference between input and output.

For example, the efficiency of an LDO with VIN of 5 volts and VOUT of 3.3 volts is 66%. But this rises to as much as 91.7% when the supply is reduced to 3.6 volts. The LDO’s power consumption can be calculated from P = (VIN - VOUT) x IOUT.

However, minimizing the difference between input and output voltage to increase LDO efficiency can only be taken so far because there is a threshold below which the device fails to properly regulate the output voltage. This minimum threshold is known as the dropout voltage (VDROPOUT). For a modern device such as STMicroelectronics’ LDL112, VDROPOUT measures 350 millivolts (at 3.3 volts, 1 A output).

The designer should note that VDROPOUT is the point at which the LDO is no longer able to regulate the supply voltage. To meet its full specification, the LDO typically requires an additional “headroom voltage”, which typically adds another 250 to 500 mV to VDROPOUT, but it can be as much as 1.5 volts for some LDOs. VDROPOUT and the headroom voltage must be taken into account when determining the difference between the input and output voltages.

For more on designing in an LDO for battery-powered devices see, Use Advanced LDOs to Meet IoT Wireless Sensor Power Supply Design Challenges.

Optimizing LDO performance

As demonstrated above, for a power-constrained design, it’s good engineering practice to minimize the voltage difference across the LDO as the resulting power savings can dramatically extend battery life. But there is more that can be done when the power budget is highly constrained.

One area requiring consideration is the power drain that occurs when a wearable is in a low power or “sleep” mode, such as when the device is not using its microcontroller, transceiver, or GPS capability. Although the end product’s current consumption will be low in this mode, the LDO must remain active to minimize latency should a user press an operational button or activate a touchscreen.

When the wearable is in a sleep state, IOUT is small; consequently, IGND has a greater effect on efficiency than during normal operation. Because the load on the device is low, the actual power consumption is not large; nonetheless it is continuous and over an extended period will have a major impact on battery life. It is good design practice to select an LDO that meets the specification while offering the lowest internal current drain to minimize losses when IOUT is low.

Better yet, most modern LDOs offer an option to put the device into a shutdown mode by pulling a selected pin low. The result is to disconnect the device completely from the load, effectively limiting IOUT to just IGND.

For example, Microchip’s MCP1811A incorporates a shutdown (“SHDN”) input that is used to turn the LDO output voltage off and on (Figure 2). The device operates from a 1.8 to 5.5 volt input and offers a choice of nine fixed outputs across a 1 to 4 volt range. The LDO has a VDROPOUT of 400 mV, provides a maximum output of up to 150 mA, and features an IQ of 250 nA and an IGND of 80 µA (at IOUT = 150 mA, VIN = 5 volts, VOUT = 4 volts).

Diagram of Microchip’s MCP1811A features a shutdown modeFigure 2: Microchip’s MCP1811A features a shutdown mode. The response time to the SHDN pin going high and delivery of the regulated voltage varies between 600 and 1400 µs. (Image source: Microchip Technology)

When the SHDN input is high (minimum 70% of VIN), the LDO output voltage is enabled and the device supplies the regulated voltage. When the SHDN input is pulled low (maximum 20% of VIN), the regulated voltage supply is switched off and the LDO enters a low current shutdown state where the typical IQ is 10 nA and IGND is around 2 µA.

The upside of being able to put the MCP1181A into a shutdown mode is the obvious power savings, but the downside is the effect the startup time has on system response. To ensure the LDO doesn’t switch on due to system noise spikes on the SHDN pin and waste battery power, the shutdown circuit features a 400 microsecond (μs) delay on the rising edge of the SHDN input before switching the regulator on. This is a good idea from an operational perspective but has an impact on response. After the preset delay, if the SHDN input remains high, the regulator starts charging the load capacitor as the output rises from 0 volts to its final regulated value. Therefore, the total time from the SHDN input turning on to the output delivering the regulation voltage is the sum of the built-in 400 μs delay time plus the output voltage rise time. This rise time depends on VOUT and can vary from 200 up to 1000 μs.

Likewise, ON Semiconductor’s NCP171 dual-mode XDFN4 package LDO can be put into a shutdown mode by driving its ENA pin low (less than 0.4 volts). The LDO has a fixed output voltage range of 0.6 to 3.3 volts from a 1.7 to 5.5 volt input, and a VDROPOUT of 110 mV. However, the NCP171 offers a more sophisticated system for extending battery life that helps to improve the response when switching from a low-power mode to the regulated voltage output required for normal operation.

In active mode, the LDO is capable of supplying up to 80 mA, but when using the low-power mode, the LDO’s regulated output voltage is not switched off; instead IOUT is limited to a maximum of 5 mA. Because a different part of the LDO is used for regulation, IGND is significantly reduced, extending battery life. The low-power (and active) modes are selectable via the LDO’s ECO pin (Figure 3).

Diagram of ON Semiconductor’s NCP171Figure 3: ON Semiconductor’s NCP171 can be switched from an active to a low-power mode via the ECO pin. In the low-power mode, IOUT is limited to a maximum of 5 mA, while IGND is significantly reduced. (Image source: ON Semiconductor)

When the ECO pin is driven low (to ground) the LDO switches to the low-power mode. IQ is reduced from 55 µA to 50 nA. The impact on IGND is equally significant: in active mode IGND = 420 µA (IOUT = 80 mA), compared with low-power mode where IGND = 2.5 µA (IOUT = 5 mA). The power dissipation in this mode is only marginally higher than that when the device is in a shutdown mode. It is possible to further reduce power consumption in low-power mode by decreasing the nominal active mode output voltage by one of the internally programmed offsets of 50, 100, 150, and 200 millivolts.

The key advantage of the low-power mode is response time to a demand for normal regulated voltage. When pulled high (equal to VOUT) the ECO pin switches the device to active mode and restores the NCP171 LDO to the regulated voltage and a maximum IOUT up to 80 mA in less than 100 µs (Figure 4).

Diagram of switching ON Semiconductor NCP171 from low-power mode to active modeFigure 4: Switching the NCP171 from low-power mode to active mode restores the regulated voltage in less than 100 µs. (Image source: ON Semiconductor)

When starting up, the NCP171 defaults to active mode—regardless of the state of the ECO pin—so it can quickly reach and stabilize at the target output voltage. The duration of this enforced active mode is typically 35 milliseconds (ms) and ensures rapid charging of the output capacitor and rapid rise of IOUT to meet the demand of the load.

There are some downsides when operating in low-power mode: Power supply rejection ratio (PSRR)—a measure of the LDO’s ability to reject input voltage spikes—is lower and electrical noise is slightly increased (Figure 5).

Graphs of ON Semiconductor NCP171 low-power mode compared to when it is in active modeFigure 5: When the NCP171 is in low-power mode, PSRR is generally lower, compared to when it is in active mode. (Image source: ON Semiconductor)

The NCP171 LDO is accompanied by the STR-NCP171-EVK evaluation kit (EVK). The EVK is designed to be used with ON Semiconductor’s Strata Developer Studio integrated development environment (IDE), which runs on a PC. The EVK is connected to the IDE via a USB cable and can then be used to experiment with the capabilities of the LDO—for example, enabling/disabling the LDO and switching between active and low-power modes.

The EVK and IDE also allow the engineer to configure and monitor other operating parameters of the LDO including input and output voltage, power dissipation, and the device’s temperature.


A carefully selected LDO simplifies the power supply design of a wearable, while ensuring a stable voltage and current. By selecting an LDO with a low ground current and minimizing the difference between its input and output voltage, the designer can achieve an efficiency close to that of a switching regulator.

Wearable battery life can be further enhanced by selecting one of a new generation of LDOs offering operational modes, which are selected from a dedicated pin and designed to limit power dissipation while the wearable is in a sleep mode for an extended period. Silicon suppliers typically accompany the LDO with evaluation tools that allow the designer to experiment with the best settings for the device to maximize battery life.

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Steven Keeping

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Digi-Key's North American Editors