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Webinar - Understanding RISC-V Architecture and Implementation on an FPGA
In DigiKey’s upcoming webinar, speaker Sarah L. Harris, Associate Professor of Electrical and Computer Engineering at the University of Nevada, will teach attendees about the RISC-V (pronounced risk five) processor core. Topics covered will include programming, memory hierarchy, and implementation on an FPGA.
Please join us on February 23, 2022 at 2:00 PM CST. Can’t make it? That’s ok! Everyone who registers will receive a recording after it’s over.
Click here to register today: https://event.on24.com/wcc/r/3606359/8C64559CCB740EBD2485729CD7151AE8?partnerref=blog
About this author
Ashley Awalt is a Technical Content Developer that has been with DigiKey since 2011. She earned her Associate of Applied Science degree in Electronics Technology & Automated Systems from Northland Community & Technical College through the DigiKey scholarship program. Her current role is to assist in creating unique technical projects, documenting the process and ultimately participating in the production of video media coverage for the projects. In her spare time, Ashley likes to – oh, wait, is there such a thing as spare time when you’re a mom?
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