F1953 - 6-bit 0.50dB Glitch-Free™ Digital Step Attenuator with Internal DC Blocks

This reference design features the Integrated Device Technology F1953, which is a 6-bit digital step attenuator. In addition, it features internal DC blocking capacitors to reduce the system's bill-of-materials. The silicon design of F1953 has very low insertion loss and low distortion (>+60dBm IP3I). The device has pinpoint accuracy and settles to final attenuation value within 400ns. Most importantly, the F1953 includes IDT's glitch-free technology, which results in less than 0.5dB of overshoot ringing during MSB transitions. The F1953 can be controlled using either serial or parallel modes. The serial mode is selected when VMODE is pulled high (>VIH). Its attenuation setting is programmed via the 3-wire bus (LE, CLK, and DATA). The data in serial mode is clocked in Most Significant Bit (MSB) first. Meanwhile, in parallel mode, the user has the option of running in one or two modes: direct parallel or latched parallel. The direct-parallel mode is selected when VMODE (pin 13) is <VIL and LE (pin 5) is >VIH. In this mode, the device will immediately react to any voltage changes to the parallel control pins (pins 1, 15, 16, 17, 19, 20). The use of direct-parallel mode will lead to the fastest settling time. On the other hand, latched-parallel mode is selected when VMODE (pin 13) is <VIL and LE (pin 5) is toggled from <VIL to >VIH. When the device is powered up in latched parallel mode (VMODE <VIL and LE <VIL), the attenuation setting defaults to the state defined by the six parallel data pins (pins 1, 15, 16, 17, 19, 20).

This circuit is specifically designed for base station 2G, 3G, 4G, TDD radiocards, repeaters, E911 systems, WIMAX receivers and transmitters. It is useful in infrastructures like point-to-point, cable and public safety. It can also be used in military systems, JTRS radios, RFID handheld, and portable readers.