A4988 Datasheet by Allegro MicroSystems

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ENABLE RESET VREF
Features and Benefits
▪ LowRds(on)outputs
▪ Automaticcurrentdecaymodedetection/selection
▪ Mixedandslowcurrentdecaymodes
▪ Synchronousrectificationforlowpowerdissipation
▪ InternalUVLO
▪ Crossover-currentprotection
▪ 3.3and5Vcompatiblelogicsupply
▪ Thermalshutdowncircuitry
▪ Short-to-groundprotection
▪ Shortedloadprotection
▪ Fiveselectablestepmodes:full,1/2,1/4,1/8,and1/16
Package:
Description
TheA4988 is a complete microstepping motor driver with
built-intranslatorforeasyoperation.Itisdesignedtooperate
bipolar stepper motors in full-, half-, quarter-, eighth-, and
sixteenth-stepmodes,withanoutputdrivecapacityofupto
35Vand±2A.TheA4988includesafixedoff-timecurrent
regulatorwhichhastheabilitytooperateinslowormixed
decaymodes.
Thetranslatoris the key totheeasyimplementation of the
A4988.SimplyinputtingonepulseontheSTEPinputdrives
themotoronemicrostep.Therearenophasesequencetables,
high-frequencycontrollines,orcomplexinterfacestoprogram.
TheA4988interfaceisanidealfitforapplicationswherea
complexmicroprocessorisunavailableorisoverburdened.
Duringsteppingoperation,thechoppingcontrolintheA4988
automaticallyselectsthecurrentdecaymode:slowormixed.In
mixeddecaymode,thedeviceissetinitiallytoafastdecayfor
aproportionofthefixedoff-time,thentoaslowdecayforthe
remainderoftheoff-time.Mixeddecaycurrentcontrolresults
inreducedaudiblemotornoise,increasedstepaccuracy,and
reducedpowerdissipation.
DMOS Microstepping Driver with Translator
and Overcurrent Protection
Continued on the next page…
A4988
Microcontroller or
Controller Logic
VDD
VREF GND GND
RESET
ENABLE
SLEEP
DIR
MS2
MS3
MS1
STEP
VBB1
CP1 VCPVREG
VDD
ROSC
5 kΩ
0.22 µF
0.22 µF
0.1 µF 0.1 µF
100 µF
CP2
VBB2
OUT1A
OUT1B
SENSE1
OUT2A
OUT2B
SENSE2
A4988
28-contactQFN
withexposedthermalpad
5mm×5mm×0.90mm
(ETpackage)
Typical Application Diagram
4988-DS, Rev. 6
Not to scale
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4988
2
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Internal synchronous rectification control circuitry is provided
to improve power dissipation during PWM operation. Internal
circuit protection includes: thermal shutdown with hysteresis,
undervoltagelockout(UVLO),andcrossover-currentprotection.
Specialpower-onsequencingisnotrequired.
TheA4988issuppliedinasurface-mountQFNpackage(ET),5mm
×5mm,withanominaloverallpackageheightof0.90mmandan
exposedpadforenhancedthermaldissipation.Itislead(Pb)free
(suffix–T),with100%matte-tin-platedleadframes.
Description (continued)
Absolute Maximum Ratings
Characteristic Symbol Notes Rating Units
Load Supply Voltage VBB 35 V
Output Current IOUT ±2 A
Logic Input Voltage VIN –0.3 to 5.5 V
Logic Supply Voltage VDD –0.3 to 5.5 V
Motor Outputs Voltage –2.0 to 37 V
Sense Voltage VSENSE –0.5 to 0.5 V
Reference Voltage VREF 5.5 V
Operating Ambient Temperature TARange S –20 to 85 ºC
Maximum Junction TJ(max) 150 ºC
Storage Temperature Tstg –55 to 150 ºC
Selection Guide
Part Number Package Packing
A4988SETTR-T 28-contact QFN with exposed thermal pad 1500 pieces per 7-in. reel
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4988
3
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Block Diagram
SENSE1
SENSE2
VREG
VCP
CP2
Control
Logic
DAC
VDD
PWM Latch
Blanking
Mixed Decay
DAC
STEP
DIR
RESET
MS1
PWM Latch
Blanking
Mixed Decay
Current
Regulator
CP1
Charge
Pump
RS2
RS1
VBB1
OUT1A
OUT1B
VBB2
OUT2A
OUT2B
0.1 µF
VREF
Translator
Gate
Drive DMOS Full Bridge
DMOS Full Bridge
0.1 µF
0.22 µF
OSC
ROSC
MS2
REF
ENABLE
SLEEP
MS3
OCP
OCP
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4988
4
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS1 at TA = 25°C, VBB = 35 V (unless otherwise noted)
Characteristics Symbol Test Conditions Min. Typ.2Max. Units
Output Drivers
Load Supply Voltage Range VBB
Operating 8 – 35 V
During Sleep Mode 0 – 35 V
Logic Supply Voltage Range VDD Operating 3 – 5.5 V
Output On-Resistance Rds(on)
Source driver, IOUT = –1.5 A – 320 430 mΩ
Sink driver, IOUT = 1.5 A – 320 430 mΩ
Body Diode Forward Voltage VF
Source diode, IF = –1.5 A – – 1.2 V
Sink diode, IF = 1.5 A – – 1.2 V
Motor Supply Current IBB
fPWM < 50 kHz – – 4 mA
Operating, outputs disabled – – 2 mA
Sleep Mode – – 10 µA
Logic Supply Current IDD
fPWM < 50 kHz – – 8 mA
Outputs off – – 5 mA
Sleep Mode – – 10 µA
Control Logic
Logic Input Voltage VIN(1) VDD × 0.7 – – V
VIN(0) – – VDD × 0.3 V
Logic Input Current IIN(1) VIN = VDD × 0.7 –20 <1.0 20 µA
IIN(0) VIN = VDD × 0.3 –20 <1.0 20 µA
Microstep Select
RMS1 MS1 pin – 100 – kΩ
RMS2 MS2 pin – 50 – kΩ
RMS3 MS3 pin – 100 – kΩ
Logic Input Hysteresis VHYS(IN) As a % of VDD 511 19 %
Blank Time tBLANK 0.7 1 1.3 μs
Fixed Off-Time tOFF
OSC = VDD or GND 20 30 40 μs
ROSC = 25 kΩ 23 30 37 μs
Reference Input Voltage Range VREF 0 – 4 V
Reference Input Current IREF –3 0 3 μA
Current Trip-Level Error3errI
VREF = 2 V, %ITripMAX = 38.27% – – ±15 %
VREF = 2 V, %ITripMAX = 70.71% – – ±5 %
VREF = 2 V, %ITripMAX = 100.00% – – ±5 %
Crossover Dead Time tDT 100 475 800 ns
Protection
Overcurrent Protection Threshold4IOCPST 2.1 – – A
Thermal Shutdown Temperature TTSD – 165 – °C
Thermal Shutdown Hysteresis TTSDHYS – 15 – °C
VDD Undervoltage Lockout VDDUVLO VDD rising 2.7 2.8 2.9 V
VDD Undervoltage Hysteresis VDDUVLOHYS – 90 – mV
1 For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
2 Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual
units, within the specified maximum and minimum limits.
3 VERR = [(VREF/8) – VSENSE] / (VREF/8).
4 Overcurrent protection (OCP) is tested at TA = 25°C in a restricted range and guaranteed by characterization.
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4988
5
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
THERMAL CHARACTERISTICS
Characteristic Symbol Test Conditions* Value Units
Package Thermal Resistance RθJA Four-layer PCB, based on JEDEC standard 32 ºC/W
*Additional thermal information available on Allegro website.
Temperature, T
A
(°C)
Power Dissipation, P
D
(W)
0
0.50
1.50
2.00
2.50
3.00
3.50
4.00
1.00
20 40 60 80 100 120 140 160
Power Dissipation versus Ambient Temperature
R
θJA
= 32 ºC/W
) . l l . l i i 1 STEP I \' l l l ‘ l l . C l D I (—>l(—>| 51, M52 RESET, ‘ Table 1: Microstepping Resolution Truth Table
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4988
6
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Figure 1: Logic Interface Timing Diagram
STEP
t
A
t
D
t
C
MS1, MS2, MS3,
RESET, or DIR
t
B
Table 1: Microstepping Resolution Truth Table
Time Duration Symbol Typ. Unit
STEP minimum, HIGH pulse width tA1μs
STEP minimum, LOW pulse width tB1μs
Setup time, input change to STEP tC200 ns
Hold time, input change to STEP tD200 ns
MS1 MS2 MS3 Microstep Resolution Excitation Mode
L L L Full Step 2 Phase
H L L Half Step 1-2 Phase
L H L Quarter Step W1-2 Phase
H H L Eighth Step 2W1-2 Phase
H H H Sixteenth Step 4W1-2 Phase
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4988
7
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Device Operation. TheA4988isacompletemicrostepping
motordriverwithabuilt-intranslatorforeasyoperationwith
minimalcontrollines.Itisdesignedtooperatebipolarstepper
motorsinfull-,half-,quarter-,eighth,andsixteenth-stepmodes.
Thecurrentsineachofthetwooutputfull-bridgesandallofthe
N-channelDMOSFETsareregulatedwithfixedoff-timePWM
(pulse-widthmodulated)controlcircuitry.Ateachstep,thecur-
rentforeachfull-bridgeissetbythevalueofitsexternalcurrent-
senseresistor(RS1andRS2),areferencevoltage(VREF),andthe
outputvoltageofitsDAC(whichinturniscontrolledbythe
outputofthetranslator).
Atpower-onorreset,thetranslatorsetstheDACsandthephase
currentpolaritytotheinitialHomestate(showninFigures9
through13),andthecurrentregulatortoMixeddecaymodefor
bothphases.WhenastepcommandsignaloccursontheSTEP
input,thetranslatorautomaticallysequencestheDACstothe
nextlevelandcurrentpolarity.(SeeTable2forthecurrent-level
sequence.)Themicrostepresolutionissetbythecombinedeffect
oftheMSxinputs,asshowninTable1.
Whenstepping,ifthenewoutputlevelsoftheDACsarelower
thantheirpreviousoutputlevels,thenthedecaymodeforthe
activefull-bridgeissettoMixed.Ifthenewoutputlevelsofthe
DACsarehigherthanorequaltotheirpreviouslevels,thenthe
decaymodefortheactivefull-bridgeissettoSlow.Thisauto-
maticcurrentdecayselectionimprovesmicrosteppingperfor-
mancebyreducingthedistortionofthecurrentwaveformthat
resultsfromthebackEMFofthemotor.
Microstep Select (MSx).Themicrostepresolutionissetby
thevoltageonlogicinputsMSx,asshowninTable1.TheMS1and
MS3pinshavea100kΩpull-downresistance,andtheMS2pin
hasa50kΩpull-downresistance.Whenchangingthestepmode,
thechangedoesnottakeeffectuntilthenextSTEPrisingedge.
Ifthestepmodeischangedwithoutatranslatorreset,andabso-
lutepositionmustbemaintained,itisimportanttochangethe
stepmodeatasteppositionthatiscommontobothstepmodesin
ordertoavoidmissingsteps.Whenthedeviceispowereddown,
orresetduetoTSDoranovercurrentevent,thetranslatorissetto
thehomepositionwhichisbydefaultcommontoallstepmodes.
Mixed Decay Operation.ThebridgeoperatesinMixed
decaymode,atpower-onandreset,andduringnormalrunning
accordingtotheROSCconfigurationandthestepsequence,as
showninFigures9through13.DuringMixeddecaymode,when
thetrippointisreached,theA4988initiallygoesintoafastdecay
intervalfor31.25%oftheoff-time,tOFF
.Afterthat,itswitches
toslowdecayfortheremainderoftOFF.Atimingdiagramforthis
featureappearsonthenextpage.
Typically,mixeddecayisonlynecessarywhenthecurrentinthe
windingisgoingfromahighervaluetoalowervalueasdetermined
bythestateofthetranslator.Formostloads,automaticallyselected
mixeddecayisconvenientbecauseitminimizesripplewhenthe
currentisrisingandpreventsmissedstepswhenthecurrentisfalling.
Forsomeapplicationswheremicrosteppingatverylowspeedsis
necessary,thelackofbackEMFinthewindingcausesthecurrentto
increaseintheloadquickly,resultinginmissedsteps.Thisisshown
inFigure2.BypullingtheROSCpintoground,mixeddecayisset
tobeactive100%ofthetime,forbothrisingandfallingcurrents,and
preventsmissedstepsasshowninFigure3.Ifthisisnotanissue,it
isrecommendedthatautomaticallyselectedmixeddecaybeused,
becauseitwillproducereducedripplecurrents.RefertotheFixed
Off-Timesectionfordetails.
Low Current Microstepping. Intendedforapplications
wheretheminimumon-timepreventstheoutputcurrentfrom
regulatingtotheprogrammedcurrentlevelatlowcurrentsteps.
Topreventthis,thedevicecanbesettooperateinMixeddecay
modeonbothrisingandfallingportionsofthecurrentwaveform.
ThisfeatureisimplementedbyshortingtheROSCpintoground.
Inthisstate,theoff-timeisinternallysetto30µs.
Reset Input (¯
R
¯
¯
E
¯
¯
S
¯
¯
E
¯
¯
T
¯
).The¯
R
¯
¯
E
¯
¯
S
¯
¯
E
¯
¯
T
¯
inputsetsthetranslator
toapredefinedHomestate(showninFigures9through13),and
turnsoffalloftheFEToutputs.AllSTEPinputsareignoreduntil
the¯
R
¯
¯
E
¯
¯
S
¯
¯
E
¯
¯
T
¯
inputissettohigh.
Step Input (STEP).Alow-to-hightransitionontheSTEP
inputsequencesthetranslatorandadvancesthemotoroneincre-
ment.ThetranslatorcontrolstheinputtotheDACsandthedirec-
Functional Description
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4988
8
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Figure 2: Missed Steps in Low-Speed Microstepping
Figure 3: Continuous Stepping Using Automatically-Selected Mixed Stepping (ROSC pin grounded)
t → , 1 s/div.
Step input 10 V/div.
Mixed Decay
No Missed
Steps
ILOAD 500 mA/div.
t → , 1 s/div.
Step input 10 V/div.
Slow
Decay
Slow
Decay
Slow
Decay
Slow
Decay
Mixed
Decay
Mixed
Decay
Mixed
Decay
Mixed
Decay
Missed
Step
Voltage on ROSC terminal 2 V/div.
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4988
9
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
tionofcurrentflowineachwinding.Thesizeoftheincrementis
determinedbythecombinedstateoftheMSxinputs.
Direction Input (DIR). Thisdeterminesthedirectionofrota-
tionofthemotor.Changestothisinputdonottakeeffectuntilthe
nextSTEPrisingedge.
Internal PWM Current Control. Eachfull-bridgeiscon-
trolledbyafixedoff-timePWMcurrentcontrolcircuitthatlimits
theloadcurrenttoadesiredvalue,ITRIP
.Initially,adiagonalpair
ofsourceandsinkFEToutputsareenabledandcurrentflows
throughthemotorwindingandthecurrentsenseresistor,RSx.
WhenthevoltageacrossRSxequalstheDACoutputvoltage,the
currentsensecomparatorresetsthePWMlatch.Thelatchthen
turnsofftheappropriatesourcedriverandinitiatesafixedoff-
timedecaymode
Themaximumvalueofcurrentlimitingissetbytheselectionof
RSxandthevoltageattheVREFpin.Thetransconductancefunc-
tionisapproximatedbythemaximumvalueofcurrentlimiting,
ITripMAX(A),whichissetby
ITripMAX = VREF / ( 8 × RS)
whereRSistheresistanceofthesenseresistor(Ω)andVREFis
theinputvoltageontheREFpin(V).
TheDACoutputreducestheVREFoutputtothecurrentsense
comparatorinprecisesteps,suchthat
Itrip = (%ITripMAX / 100) × ITripMAX
(SeeTable2for%ITripMAXateachstep.)
Itiscriticalthatthemaximumrating(0.5V)ontheSENSE1and
SENSE2pinsisnotexceeded.
Fixed Off-Time.TheinternalPWMcurrentcontrolcircuitry
usesaone-shotcircuittocontrolthedurationoftimethatthe
DMOSFETsremainoff.Theoff-time,tOFF,isdeterminedbythe
ROSCterminal.TheROSCterminalhasthreesettings:
▪ ROSCtiedtoVDD—off-timeinternallysetto30µs;decay
modeisautomaticMixed,exceptwheninfull-stepwhere
decaymodeissettoSlow.
▪ ROSCtieddirectlytoground—off-timeinternallysetto
30µs;currentdecayissettoMixedforbothincreasingand
decreasingcurrentsforallstepmodes.
▪ ROSCthrougharesistortoground—off-timeisdetermined
bythefollowingformula;thedecaymodeisautomaticMixed
forallstepmodesexceptfull-stepwhichissettoSlow.
tOFF ≈ ROSC ⁄ 825
wheretOFFisinµs.
Blanking.Thisfunctionblankstheoutputofthecurrentsense
comparatorswhentheoutputsareswitchedbytheinternalcurrent
controlcircuitry.Thecomparatoroutputsareblankedtoprevent
falseovercurrentdetectionduetoreverserecoverycurrentsofthe
clampdiodes,andswitchingtransientsrelatedtothecapacitance
oftheload.Theblanktime,tBLANK(µs),isapproximately
tBLANK ≈ 1 µs
Shorted Load and Short-to-Ground Protection.
Ifthemotorleadsareshortedtogether,orifoneoftheleadsis
shortedtoground,thedriverwillprotectitselfbysensingthe
overcurrenteventanddisablingthedriverthatisshorted,protect-
ingthedevicefromdamage.Inthecaseofashort-to-ground,the
devicewillremaindisabled(latched)untiltheS
¯
¯
L
¯
¯
E
¯
¯
E
¯
¯
P
¯
inputgoes
highorVDDpowerisremoved.Ashort-to-groundovercurrent
eventisshowninFigure4.
Whenthetwooutputsareshortedtogether,thecurrentpathis
throughthesenseresistor.Aftertheblankingtime(≈1µs)expires,
thesenseresistorvoltageisexceedingitstripvalue,duetothe
overcurrentconditionthatexists.Thiscausesthedrivertogointo
afixedoff-timecycle.Afterthefixedoff-timeexpires,thedriver
turnsonagainandtheprocessrepeats.Inthiscondition,the
driveriscompletelyprotectedagainstovercurrentevents,butthe
shortisrepetitivewithaperiodequaltothefixedoff-timeofthe
driver.ThisconditionisshowninFigure5.
Duringashortedloadevent,itisnormaltoobservebothaposi-
tiveandnegativecurrentspikeasshowninFigure3,duetothe
directionchangeimplementedbytheMixeddecayfeature.Thisis
showninFigure6.Inbothinstances,theovercurrentcircuitryis
protectingthedriverandpreventsdamagetothedevice.
Charge Pump (CP1 and CP2).Thechargepumpisused
togenerateagatesupplygreaterthanthatofVBBfordrivingthe
source-sideFETgates.A0.1µFceramiccapacitorshouldbe
connectedbetweenCP1andCP2.Inaddition,a0.1µFceramic
capacitorisrequiredbetweenVCPandVBB,toactasareservoir
foroperatingthehigh-sideFETgates.
CapacitorvaluesshouldbeClass2dielectric±15%maximum,
ortoleranceR,accordingtoEIA(ElectronicIndustriesAlliance)
specifications.
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4988
10
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
VREG (VREG).Thisinternallygeneratedvoltageisusedto
operatethesink-sideFEToutputs.Thenominaloutputvoltage
oftheVREGterminalis7V.TheVREGpinmustbedecoupled
witha0.22µFceramiccapacitortoground.VREGisinternally
monitored.Inthecaseofafaultcondition,theFEToutputsofthe
A4988aredisabled.
CapacitorvaluesshouldbeClass2dielectric±15%maximum,
ortoleranceR,accordingtoEIA(ElectronicIndustriesAlliance)
specifications.
Enable Input (¯
E
¯
¯
N
¯
¯
A
¯
¯
B
¯
¯
L
¯
¯
E
¯
).Thisinputturnsonoroffallofthe
FEToutputs.Whensettoalogichigh,theoutputsaredisabled.
Whensettoalogiclow,theinternalcontrolenablestheoutputs
asrequired.ThetranslatorinputsSTEP,DIR,andMSx,aswellas
theinternalsequencinglogic,allremainactive,independentofthe
¯
E
¯

¯
N
¯

¯
A
¯
 ¯
B
¯
¯
L
¯
 ¯
E
¯
inputstate.
Shutdown.Intheeventofafault,overtemperature(excessTJ)
oranundervoltage(onVCP),theFEToutputsoftheA4988are
disableduntilthefaultconditionisremoved.Atpower-on,the
UVLO(undervoltagelockout)circuitdisablestheFEToutputs
andresetsthetranslatortotheHomestate.
Sleep Mode( ¯
S
¯
¯
L
¯
¯
E
¯
¯
E
¯
¯
P
¯
).Tominimizepowerconsumption
whenthemotorisnotinuse,thisinputdisablesmuchofthe
internalcircuitryincludingtheoutputFETs,currentregulator,
andchargepump.AlogiclowontheS
¯
¯
L
¯
¯
E
¯
¯
E
¯
¯
P
¯
pinputstheA4988
intoSleepmode.Alogichighallowsnormaloperation,aswell
asstartup(atwhichtimetheA4988drivesthemotortotheHome
microstepposition).WhenemergingfromSleepmode,inorder
toallowthechargepumptostabilize,provideadelayof1ms
beforeissuingaStepcommand.
Mixed Decay Operation.ThebridgeoperatesinMixed
decaymode,dependingonthestepsequence,asshowninFig-
ures9through13.Asthetrippointisreached,theA4988initially
goesintoafastdecayintervalfor31.25%oftheoff-time,tOFF.
Afterthat,itswitchestoslowdecayfortheremainderoftOFF.A
timingdiagramforthisfeatureappearsinFigure7.
Synchronous Rectification.WhenaPWM-offcycleis
triggeredbyaninternalfixed-offtimecycle,loadcurrentrecircu-
latesaccordingtothedecaymodeselectedbythecontrollogic.
Thissynchronousrectificationfeatureturnsontheappropriate
FETsduringcurrentdecay,andeffectivelyshortsoutthebody
diodeswiththelowFETRds(on).Thisreducespowerdissipation
significantly,andcaneliminatetheneedforexternalSchottky
diodesinmanyapplications.Synchronousrectificationturnsoff
whentheloadcurrentapproacheszero(0A),preventingreversal
oftheloadcurrent.
t →
Fixed off-time
5 A / div.
t →
5 A / div.
Figure 4: Short-to-Ground Event
Figure 5. Shorted Load (OUTxA → OUTxB) in Slow Decay Mode
Figure 6: Shorted Load (OUTxA → OUTxB) in Mixed Decay Mode
Fixed off-time
Fast decay portion
(direction change)
t →
5 A / div. Fault
latched
Enlar emem A
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4988
11
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
VSTEP
IOUT
IOUT
t
See Enlargement A
Enlargement A
t
SD
t
FD
t
off
Slow Decay
Mixed Decay
Fast Decay
I
PEAK
70.71
–70.71
0
100.00
–100.00
Symbol Characteristic
toff Device fixed off-time
IPEAK Maximum output current
tSD Slow decay interval
tFD Fast decay interval
IOUT Device output current
Figure 7: Current Decay Modes Timing Chart
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4988
12
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Application Layout
Layout.Theprintedcircuitboardshoulduseaheavyground-
plane.Foroptimumelectricalandthermalperformance,the
A4988mustbesoldereddirectlyontotheboard.Pins3and18
areinternallyfused,whichprovidesapathforenhancedthermal
dissipation.Thesespinsshouldbesoldereddirectlytoanexposed
surfaceonthePCBthatconnectstothermalviasareusedto
transferheattootherlayersofthePCB.
Inordertominimizetheeffectsofgroundbounceandoffset
issues,itisimportanttohavealow-impedancesingle-point
ground,knownasastar ground,locatedveryclosetothedevice.
Bymakingtheconnectionbetweenthepadandthegroundplane
directlyundertheA4988,thatareabecomesanideallocationfor
astargroundpoint.Alow-impedancegroundwillpreventground
bounceduringhigh-currentoperationandensurethatthesupply
voltageremainsstableattheinputterminal.
Thetwoinputcapacitorsshouldbeplacedinparallel,andas
closetothedevicesupplypinsaspossible.Theceramiccapaci-
tor(CIN1)shouldbeclosertothepinsthanthebulkcapacitor
(CIN2).Thisisnecessarybecausetheceramiccapacitorwillbe
responsiblefordeliveringthehigh-frequencycurrentcomponents.
Thesenseresistors,RSx,shouldhaveaverylow-impedance
pathtoground,becausetheymustcarryalargecurrentwhile
supportingveryaccuratevoltagemeasurementsbythecurrent
sensecomparators.Longgroundtraceswillcauseadditional
voltagedrops,adverselyaffectingtheabilityofthecomparators
toaccuratelymeasurethecurrentinthewindings.TheSENSEx
pinshaveveryshorttracestotheRSxresistorsandverythick,
low-impedancetracesdirectlytothestargroundunderthe
device.Ifpossible,thereshouldbenoothercomponentsonthe
sensecircuits.
V
BB
V
DD
1
PAD
A4988
C3
C6
R1
R2
R3
C1 C8
C2
C9C7
RS2RS1
R6
C4
OUT1B
NC
DIR
REF
STEP
VDD
OUT2B
ENABLE
CP1
CP2
VCP
NC
VREG
MS1
MS2
MS3
RESET
ROSC
SLEEP
VBB2
SENSE2
OUT2A
NC
OUT1A
SENSE1
VBB1
GND
GND
PCB
Thermal Vias
Trace (2 oz.)
Signal (1 oz.)
Ground (1 oz.)
Thermal (2 oz.)
Solder
A4988
Figure 8: Typical Application and Circuit Layout
BEBE
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4988
13
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
VCP
GND
CP2
GND
CP1VBB
8 V
GND
VDD
GND GND
8 V
GND GND
8 V
VBB
VREG
10 V
GND
DMOS
Parasitic
SENSE VREG
GND
VBB
40 V
GND
VBB
OUT
DMOS
Parasitic
DMOS
Parasitic
GND
PGND GND
MS1
MS2
MS3
DIR
VREF
ROSC
SLEEP
Pin Circuit Diagrams
W \ ‘ ‘. \ ‘ ‘ 4 Mixed 4 Slow Slow Slow Mme Mlxe MIXe D _______________ ___ I‘ \ \ ‘ Mixed’ —a —a ‘5‘ ‘ Slow Slow Slow Mlxe MIL; Mixed ‘w‘m Rosa mu m m mm
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4988
14
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Figure 10: Decay Modes for Half-Step IncrementsFigure 9: Decay Mode for Full-Step Increments
*With ROSC pin tied to GND
Mixed*
Phase 2
I
OUT2A
Direction =
H
(%)
Phase 1
I
OUT1A
Direction =
H
(%)
STEP
Home Microstep Position
Home Microstep Position
100.00
70.71
–70.71
0.00
–100.00
100.00
70.71
–70.71
0.00
–100.00
Slow
RESET
*With ROSC pin tied to GND
Home Microstep Position
Home Microstep Position
100.00
70.71
–70.71
0.00
–100.00
100.00
70.71
–70.71
0.00
–100.00
Phase 2
IOUT2B
Direction = H
(%)
Phase 1
IOUT1A
Direction = H
(%)
STEP
Slow
Mixed
Mixed*
Mixed*
Slow
Mixed
Slow
Mixed
Mixed
Slow
Mixed
Slow
Mixed
Slow
Slow
0.00
100.00
92.39
70.71
38.27
–38.27
–70.71
–92.39
–100.00
0.00
100.00
92.39
70.71
38.27
–38.27
–70.71
–92.39
–100.00
Phase 2
IOUT2B
Direction = H
(%)
Phase 1
IOUT1A
Direction = H
(%)
Home Microstep Position
Slow Mixed Slow
Slow Mixed
Slow Mixed Slow MixedMixed
STEP
Slow
Mixed*
Mixed*
Figure 11: Decay Modes for Quarter-Step Increments
DIR= H
DIR= H DIR= H
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4988
15
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Figure 12: Decay Modes for Eighth-Step Increments
Mixed Mixed
Slow Slow
Mixed Slow Mixed Slow
0.00
100.00
92.39
70.71
55.56
–55.56
83.15
–83.15
38.27
19.51
–19.51
–38.27
–70.71
–92.39
–100.00
0.00
100.00
92.39
70.71
55.56
–55.56
83.15
–83.15
38.27
19.51
–19.51
–38.27
–70.71
–92.39
–100.00
Phase 2
I
OUT2B
Direction = H
(%)
Phase 1
I
OUT1A
Direction = H
(%)
Home Microstep Position
STEP
Mixed*
Mixed*
*With ROSC pin tied to GND
DIR= H
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4988
16
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Figure 13: Decay Modes for Sixteenth-Step Increments
MixedSlow
Mixed*
Mixed*
MixedSlow
MixedSlow Slow
Slow
100.00
95.69
88.19
83.15
–83.15
77.30
70.71
63.44
55.56
47.14
38.27
29.03
19.51
9.8
0.00
–100.00
–95.69
–88.19
–77.30
–70.71
–63.44
–55.56
–47.14
–38.27
–29.03
–19.51
–9.8
100.00
95.69
88.19
83.15
–83.15
77.30
70.71
63.44
55.56
47.14
38.27
29.03
19.51
9.8
0.00
–100.00
–95.69
–88.19
–77.30
–70.71
–63.44
–55.56
–47.14
–38.27
–29.03
–19.51
–9.8
Phase 2
I
OUT2B
Direction = H
(%)
Phase 1
I
OUT1A
Direction = H
(%)
Home Microstep Position
Mixed
*With ROSC pin tied to GND
STEP
DIR= H
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4988
17
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Table 2: Step Sequencing Settings
Home microstep position at Step Angle 45º; DIR = H
Full
Step
#
Half
Step
#
1/4
Step
#
1/8
Step
#
1/16
Step
#
Phase 1
Current
[% ItripMax]
(%)
Phase 2
Current
[% ItripMax]
(%)
Step
Angle
(º)
Full
Step
#
Half
Step
#
1/4
Step
#
1/8
Step
#
1/16
Step
#
Phase 1
Current
[% ItripMax]
(%)
Phase 2
Current
[% ItripMax]
(%)
Step
Angle
(º)
1 1 1 1 100.00 0.00 0.0 5 9 17 33 –100.00 0.00 180.0
2 99.52 9.80 5.6 34 –99.52 –9.80 185.6
2 3 98.08 19.51 11.3 18 35 –98.08 –19.51 191.3
4 95.69 29.03 16.9 36 –95.69 –29.03 196.9
2 3 5 92.39 38.27 22.5 10 19 37 –92.39 –38.27 202.5
6 88.19 47.14 28.1 38 –88.19 –47.14 208.1
4 7 83.15 55.56 33.8 20 39 –83.15 –55.56 213.8
8 77.30 63.44 39.4 40 –77.30 –63.44 219.4
1 2 3 5 9 70.71 70.71 45.0 3 6 11 21 41 –70.71 –70.71 225.0
10 63.44 77.30 50.6 42 –63.44 –77.30 230.6
611 55.56 83.15 56.3 22 43 –55.56 –83.15 236.3
12 47.14 88.19 61.9 44 –47.14 –88.19 241.9
4 7 13 38.27 92.39 67.5 12 23 45 –38.27 –92.39 247.5
14 29.03 95.69 73.1 46 –29.03 –95.69 253.1
8 15 19.51 98.08 78.8 24 47 –19.51 –98.08 258.8
16 9.80 99.52 84.4 48 –9.80 –99.52 264.4
3 5 9 17 0.00 100.00 90.0 7 13 25 49 0.00 –100.00 270.0
18 –9.80 99.52 95.6 50 9.80 –99.52 275.6
10 19 –19.51 98.08 101.3 26 51 19.51 –98.08 281.3
20 –29.03 95.69 106.9 52 29.03 –95.69 286.9
611 21 –38.27 92.39 112.5 14 27 53 38.27 –92.39 292.5
22 –47.14 88.19 118.1 54 47.14 –88.19 298.1
12 23 –55.56 83.15 123.8 28 55 55.56 –83.15 303.8
24 –63.44 77.30 129.4 56 63.44 –77.30 309.4
2 4 7 13 25 –70.71 70.71 135.0 4 8 15 29 57 70.71 –70.71 315.0
26 –77.30 63.44 140.6 58 77.30 –63.44 320.6
14 27 –83.15 55.56 146.3 30 59 83.15 –55.56 326.3
28 –88.19 47.14 151.9 60 88.19 –47.14 331.9
8 15 29 –92.39 38.27 157.5 16 31 61 92.39 –38.27 337.5
30 –95.69 29.03 163.1 62 95.69 –29.03 343.1
16 31 –98.08 19.51 168.8 32 63 98.08 –19.51 348.8
32 –99.52 9.80 174.4 64 99.52 –9.80 354.4
Wm r rm Terminal List Table
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4988
18
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Pinout Diagram
Terminal List Table
Name Number Description
CP1 4 Charge pump capacitor terminal
CP2 5 Charge pump capacitor terminal
VCP 6 Reservoir capacitor terminal
VREG 8 Regulator decoupling terminal
MS1 9 Logic input
MS2 10 Logic input
MS3 11 Logic input
¯
R
¯
¯
E
¯
¯
S
¯
¯
E
¯
¯
T
¯ 12 Logic input
ROSC 13 Timing set
¯
S
¯
¯
L
¯
¯
E
¯
¯
E
¯
¯
P
¯ 14 Logic input
VDD 15 Logic supply
STEP 16 Logic input
REF 17 Gm reference voltage input
GND 3, 18 Ground*
DIR 19 Logic input
OUT1B 21 DMOS Full Bridge 1 Output B
VBB1 22 Load supply
SENSE1 23 Sense resistor terminal for Bridge 1
OUT1A 24 DMOS Full Bridge 1 Output A
OUT2A 26 DMOS Full Bridge 2 Output A
SENSE2 27 Sense resistor terminal for Bridge 2
VBB2 28 Load supply
OUT2B 1 DMOS Full Bridge 2 Output B
¯
E
¯
¯
N
¯
¯
A
¯
¯
B
¯
¯
L
¯
¯
E
¯ 2 Logic input
NC 7, 20, 25 No connection
PAD – Exposed pad for enhanced thermal dissipation*
*The GND pins must be tied together externally by connecting to the PAD ground plane
under the device.
PAD
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
VBB2
SENSE2
OUT2A
NC
OUT1A
SENSE1
VBB1
VREG
MS1
MS2
MS3
RESET
ROSC
SLEEP
OUT1B
NC
DIR
GND
REF
STEP
VDD
OUT2B
ENABLE
GND
CP1
CP2
VCP
NC
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DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4988
19
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ET Package, 28-Pin QFN with Exposed Thermal Pad
0.25 +0.05
–0.07
0.50
0.90 ±0.10
C0.08
29X SEATING
PLANE
C
ATerminal #1 mark area
BExposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
For Reference Only; not for tooling use
(reference JEDEC MO-220VHHD-1)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
CReference land pattern layout (reference IPC7351
QFN50P500X500X100-29V1M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
28
2
1
A
28
1
2
PCB Layout Reference View
B
3.15
0.73 MAX
3.15
3.15
3.15
0.30
1
28 0.50
1.15
4.80
4.80
C
5.00 ±0.15
5.00 ±0.15
D
DCoplanarity includes exposed thermal pad and terminals
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4988
20
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
For the latest version of this document, visit our website:
www.allegromicro.com
Revision History
Revision Revision Date Description of Revision
4 January 27, 2012 Updated IOCPST
5 May 7, 2014 Revised text on page 9; revised Figure 8 and Table 2
6 January 14, 2016 Updated VBB, IBB, and IDD in Electrical Characteristics table
Copyright ©2016, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.

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