MPC8541E Datasheet by NXP USA Inc.

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© Freescale Semiconductor, Inc., 2008. All rights reserved.
Freescale Semiconductor
Technical Data
The MPC8541E integrates a PowerPC™ processor core
built on Power Architecture™ technology with system logic
required for networking, telecommunications, and wireless
infrastructure applications. The MPC8541E is a member of
the PowerQUICC™ III family of devices that combine
system-level support for industry-standard interfaces with
processors that implement the embedded category of the
Power Architecture technology. For functional
characteristics of the processor, refer to the MPC8555E
PowerQUICC™ III Integrated Communications Processor
Reference Manual.
To locate any published errata or updates for this document
refer to http://www.freescale.com or contact your Freescale
sales office.
MPC8541EEC
Rev. 4.2, 1/2008
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 7
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12
4. Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6. DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8. Ethernet: Three-Speed, MII Management . . . . . . . . . . 21
9. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10. CPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
12. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
13. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
14. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . . . 54
15. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
16. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
17. System Design Information . . . . . . . . . . . . . . . . . . . . . 76
18. Document Revision History . . . . . . . . . . . . . . . . . . . . 83
19. Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . 84
MPC8541E PowerQUICC™ III
Integrated Communications Processor
Hardware Specification
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
2Freescale Semiconductor
Overview
1Overview
The following section provides a high-level overview of the MPC8541E features. Figure 1 shows the
major functional units within the MPC8541E.
.
Figure 1. MPC8541E Block Diagram
1.1 Key Features
The following lists an overview of the MPC8541E feature set.
Embedded e500 Book E-compatible core
High-performance, 32-bit Book E-enhanced core that implements the PowerPC architecture
Dual-issue superscalar, 7-stage pipeline design
32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection
Lockable L1 caches—entire cache or on a per-line basis
Separate locking for instructions and data
Single-precision floating-point operations
Memory management unit especially designed for embedded applications
Enhanced hardware and software debug support
Dynamic power management
Performance monitor facility
I2C Controller
Local Bus Controller
64/32b PCI Controller
0/32b PCI Controller
DMA Controller
10/100/1000 MAC
10/100/1000 MAC
MII, GMII, TBI,
RTBI, RGMIIs
Serial
DMA
ROM
I-Memory
DPRAM
RISC
Engine
Parallel I/O
Baud Rate
Generators
Timers
FCC
FCC
SPI
I2C
Serial Interfaces
MIIs/RMIIs
I/Os
CPM
DDR SDRAM Controller
CPM
Controller
Interrupt
256 Kbyte
L2 Cache/
SRAM e500 Core
32-Kbyte L1
I Cache
32-Kbyte L1
D Cache
Core Complex
e500
Coherency
Module
OCeaN
IRQs
SDRAM
DDR
GPIO
32b
Programmable
Interrupt Controller
Bus
DUART
Security
Engine
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 3
Overview
Security Engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,
IEEE Std 802.11i™, iSCSI, and IKE processing. The Security Engine contains 4 Crypto-channels,
a Controller, and a set of crypto Execution Units (EUs). The Execution Units are:
Public Key Execution Unit (PKEU) supporting the following:
RSA and Diffie-Hellman
Programmable field size up to 2048-bits
Elliptic curve cryptography
F2m and F(p) modes
Programmable field size up to 511-bits
Data Encryption Standard Execution Unit (DEU)
DES, 3DES
Two key (K1, K2) or Three Key (K1, K2, K3)
ECB and CBC modes for both DES and 3DES
Advanced Encryption Standard Unit (AESU)
Implements the Rinjdael symmetric key cipher
Key lengths of 128, 192, and 256 bits.Two key
ECB, CBC, CCM, and Counter modes
ARC Four execution unit (AFEU)
Implements a stream cipher compatible with the RC4 algorithm
40- to 128-bit programmable key
Message Digest Execution Unit (MDEU)
SHA with 160-bit or 256-bit message digest
MD5 with 128-bit message digest
HMAC with either algorithm
Random Number Generator (RNG)
4 Crypto-channels, each supporting multi-command descriptor chains
Static and/or dynamic assignment of crypto-execution units via an integrated controller
Buffer size of 256 Bytes for each execution unit, with flow control for large data sizes
High-performance RISC CPM
Two full-duplex fast communications controllers (FCCs) that support the following protocol:
IEEE Std 802.3™/Fast Ethernet (10/100)
Serial peripheral interface (SPI) support for master or slave
—I
2C bus controller
General-purpose parallel ports—16 parallel I/O lines with interrupt capability
256 Kbytes of on-chip memory
Can act as a 256-Kbyte level-2 cache
Can act as a 256-Kbyte or two 128-Kbyte memory-mapped SRAM arrays
Can be partitioned into 128-Kbyte L2 cache plus 128-Kbyte SRAM
Full ECC support on 64-bit boundary in both cache and SRAM modes
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
4Freescale Semiconductor
Overview
SRAM operation supports relocation and is byte-accessible
Cache mode supports instruction caching, data caching, or both
External masters can force data to be allocated into the cache through programmed memory
ranges or special transaction types (stashing).
Eight-way set-associative cache organization (1024 sets of 32-byte cache lines)
Supports locking the entire cache or selected lines
Individual line locks set and cleared through Book E instructions or by externally mastered
transactions
Global locking and flash clearing done through writes to L2 configuration registers
Instruction and data locks can be flash cleared separately
Read and write buffering for internal bus accesses
Address translation and mapping unit (ATMU)
Eight local access windows define mapping within local 32-bit address space
Inbound and outbound ATMUs map to larger external address spaces
Three inbound windows plus a configuration window on PCI
Four inbound windows
Four outbound windows plus default translation for PCI
DDR memory controller
Programmable timing supporting first generation DDR SDRAM
64-bit data interface, up to MHz data rate
Four banks of memory supported, each up to 1 Gbyte
DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports
Full ECC support
Page mode support (up to 16 simultaneous open pages)
Contiguous or discontiguous memory mapping
Sleep mode support for self refresh DDR SDRAM
Supports auto refreshing
On-the-fly power management using CKE signal
Registered DIMM support
Fast memory access via JTAG port
2.5-V SSTL2 compatible I/O
Programmable interrupt controller (PIC)
Programming model is compliant with the OpenPIC architecture
Supports 16 programmable interrupt and processor task priority levels
Supports 12 discrete external interrupts
Supports 4 message interrupts with 32-bit messages
Supports connection of an external interrupt controller such as the 8259 programmable
interrupt controller
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 5
Overview
Four global high resolution timers/counters that can generate interrupts
Supports additional internal interrupt sources
Supports fully nested interrupt delivery
Interrupts can be routed to external pin for external processing
Interrupts can be routed to the e500 cores standard or critical interrupt inputs
Interrupt summary registers allow fast identification of interrupt source
•Two I
2C controllers (one is contained within the CPM, the other is a stand-alone controller which
is not part of the CPM)
Two-wire interface
Multiple master support
Master or slave I2C mode support
On-chip digital filtering rejects spikes on the bus
Boot sequencer
Optionally loads configuration data from serial ROM at reset via the stand-alone I2C interface
Can be used to initialize configuration registers and/or memory
Supports extended I2C addressing mode
Data integrity checked with preamble signature and CRC
• DUART
Two 4-wire interfaces (RXD, TXD, RTS, CTS)
Programming model compatible with the original 16450 UART and the PC16550D
Local bus controller (LBC)
Multiplexed 32-bit address and data operating at up to 166 MHz
Eight chip selects support eight external slaves
Up to eight-beat burst transfers
The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller
Three protocol engines available on a per chip select basis:
General purpose chip select machine (GPCM)
Three user programmable machines (UPMs)
Dedicated single data rate SDRAM controller
Parity support
Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)
Two Three-speed (10/100/1000)Ethernet controllers (TSECs)
Dual IEEE 802.3, 802.3u, 802.3x, 802.3z AC compliant controllers
Support for Ethernet physical interfaces:
10/100/1000 Mbps IEEE 802.3 GMII
10/100 Mbps IEEE 802.3 MII
10 Mbps IEEE 802.3 MII
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
6Freescale Semiconductor
Overview
1000 Mbps IEEE 802.3z TBI
10/100/1000 Mbps RGMII/RTBI
Full- and half-duplex support
Buffer descriptors are backwards compatible with MPC8260 and MPC860T 10/100
programming models
9.6-Kbyte jumbo frame support
RMON statistics support
2-Kbyte internal transmit and receive FIFOs
MII management interface for control and status
Programmable CRC generation and checking
OCeaN switch fabric
Three-port crossbar packet switch
Reorders packets from a source based on priorities
Reorders packets to bypass blocked packets
Implements starvation avoidance algorithms
Supports packets with payloads of up to 256 bytes
Integrated DMA controller
Four-channel controller
All channels accessible by both local and remote masters
Extended DMA functions (advanced chaining and striding capability)
Support for scatter and gather transfers
Misaligned transfer capability
Interrupt on completed segment, link, list, and error
Supports transfers to or from any local memory or I/O port
Selectable hardware-enforced coherency (snoop/no-snoop)
Ability to start and flow control each DMA channel from external 3-pin interface
Ability to launch DMA from single write transaction
PCI Controllers
PCI 2.2 compatible
One 64-bit or two 32-bit PCI ports supported at 16 to 66 MHz
Host and agent mode support, 64-bit PCI port can be host or agent, if two 32-bit ports, only one
can be an agent
64-bit dual address cycle (DAC) support
Supports PCI-to-memory and memory-to-PCI streaming
Memory prefetching of PCI read accesses
Supports posting of processor-to-PCI and PCI-to-memory writes
PCI 3.3-V compatible
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 7
Electrical Characteristics
Selectable hardware-enforced coherency
Selectable clock source (SYSCLK or independent PCI_CLK)
Power management
Fully static 1.2-V CMOS design with 3.3- and 2.5-V I/O
Supports power save modes: doze, nap, and sleep
Employs dynamic power management
Selectable clock source (sysclk or independent PCI_CLK)
System performance monitor
Supports eight 32-bit counters that count the occurrence of selected events
Ability to count up to 512 counter specific events
Supports 64 reference events that can be counted on any of the 8 counters
Supports duration and quantity threshold counting
Burstiness feature that permits counting of burst events with a programmable time between
bursts
Triggering and chaining capability
Ability to generate an interrupt on overflow
System access port
Uses JTAG interface and a TAP controller to access entire system memory map
Supports 32-bit accesses to configuration registers
Supports cache-line burst accesses to main memory
Supports large block (4-Kbyte) uploads and downloads
Supports continuous bit streaming of entire block for fast upload and download
IEEE Std 1149.1™-compatible, JTAG boundary scan
783 FC-PBGA package
2 Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the
MPC8541E. The MPC8541E is currently targeted to these specifications. Some of these specifications are
independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer
design specifications.
2.1 Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
8Freescale Semiconductor
Electrical Characteristics
2.1.1 Absolute Maximum Ratings
Table 1 provides the absolute maximum ratings.
2.1.2 Power Sequencing
The MPC8541Erequires its power rails to be applied in a specific sequence in order to ensure proper device
operation. These requirements are as follows for power up:
1. VDD, AVDDn
2. GVDD, LVDD, OVDD (I/O supplies)
Table 1. Absolute Maximum Ratings 1
Characteristic Symbol Max Value Unit Notes
Core supply voltage VDD –0.3 to 1.32
0.3 to 1.43 (for 1 GHz only)
V
PLL supply voltage AVDD –0.3 to 1.32
0.3 to 1.43 (for 1 GHz only)
V
DDR DRAM I/O voltage GVDD –0.3 to 3.63 V
Three-speed Ethernet I/O, MII management voltage LVDD –0.3 to 3.63
–0.3 to 2.75
V
CPM, PCI, local bus, DUART, system control and power
management, I2C, and JTAG I/O voltage
OVDD –0.3 to 3.63 V 3
Input voltage DDR DRAM signals MVIN –0.3 to (GVDD + 0.3) V 2, 5
DDR DRAM reference MVREF –0.3 to (GVDD + 0.3) V 2, 5
Three-speed Ethernet signals LVIN 0.3 to (LVDD + 0.3) V 4, 5
CPM, Local bus, DUART,
SYSCLK, system control and
power management, I2C, and
JTAG signals
OVIN –0.3 to (OVDD + 0.3)1 V 5
PCI OVIN –0.3 to (OVDD + 0.3) V 6
Storage temperature range TSTG –55 to 150 °C
Notes:
1. Functional and tested operating conditions are given in Ta ble 2. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
4. Caution: LVIN must not exceed LVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
5. (M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
6. OVIN on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as
shown in Figure 3.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 9
Electrical Characteristics
Items on the same line have no ordering requirement with respect to one another. Items on separate lines
must be ordered sequentially such that voltage rails on a previous step must reach 90 percent of their value
before the voltage rails on the current step reach ten percent of theirs.
NOTE
If the items on line 2 must precede items on line 1, please ensure that the
delay does not exceed 500 ms and the power sequence is not done greater
than once per day in production environment.
NOTE
From a system standpoint, if the I/O power supplies ramp prior to the VDD
core supply, the I/Os on the MPC8541E may drive a logic one or zero during
power-up.
2.1.3 Recommended Operating Conditions
Table 2 provides the recommended operating conditions for the MPC8541E. Note that the values in
Table 2 are the recommended and tested operating conditions. Proper device operation outside of these
conditions is not guaranteed.
Table 2. Recommended Operating Conditions
Characteristic Symbol Recommended Value Unit
Core supply voltage VDD 1.2 V ± 60 mV
1.3 V± 50 mV (for 1 GHz only)
V
PLL supply voltage AVDD 1.2 V ± 60 mV
1.3 V ± 50 mV (for 1 GHz only)
V
DDR DRAM I/O voltage GVDD 2.5 V ± 125 mV V
Three-speed Ethernet I/O voltage LVDD 3.3 V ± 165 mV
2.5 V ± 125 mV
V
PCI, local bus, DUART, system control and power management,
I2C, and JTAG I/O voltage
OVDD 3.3 V ± 165 mV V
Input voltage DDR DRAM signals MVIN GND to GVDD V
DDR DRAM reference MVREF GND to GVDD V
Three-speed Ethernet signals LVIN GND to LVDD V
PCI, local bus, DUART,
SYSCLK, system control and
power management, I2C, and
JTAG signals
OVIN GND to OVDD V
Die-junction Temperature Tj0 to 105 °C
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
10 Freescale Semiconductor
Electrical Characteristics
Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8541E.
Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD
The MPC8541E core voltage must always be provided at nominal 1.2 V (see Table 2 for actual
recommended core voltage). Voltage to the processor interface I/Os are provided through separate sets of
supply pins and must be provided at the voltages shown in Table 2. The input voltage threshold scales with
respect to the associated I/O supply voltage. OVDD and LVDD based receivers are simple CMOS I/O
circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses a
single-ended differential receiver referenced the externally supplied MVREF signal (nominally set to
GVDD/2) as is appropriate for the SSTL2 electrical signaling standard.
GND
GND – 0.3 V
GND – 0.7 V Not to Exceed 10%
G/L/OVDD + 20%
G/L/OVDD
G/L/OVDD + 5%
of tSYS1
1. Note that tSYS refers to the clock period associated with the SYSCLK signal.
VIH
VIL
Note:
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 11
Electrical Characteristics
Figure 3 shows the undershoot and overshoot voltage of the PCI interface of the MPC8541E for the 3.3-V
signals, respectively.
Figure 3. Maximum AC Waveforms on PCI interface for 3.3-V Signaling
2.1.4 Output Driver Characteristics
Table 3 provides information on the characteristics of the output driver strengths. The values are
preliminary estimates.
Table 3. Output Drive Capability
Driver Type Programmable Output
Impedance (Ω)
Supply
Voltage Notes
Local bus interface utilities signals 25 OVDD = 3.3 V 1
42 (default)
PCI signals 25 2
42 (default)
DDR signal 20 GVDD = 2.5 V
TSEC/10/100 signals 42 LVDD = 2.5/3.3 V
DUART, system control, I2C, JTAG 42 OVDD = 3.3 V
Notes:
1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR.
2. The drive strength of the PCI interface is determined by the setting of the PCI_GNT1 signal at reset.
11 ns
(Min)
Overvoltage
Waveform
Undervoltage
Waveform
4 ns
(Max)
4 ns
(Max)
62.5 ns
–3.5 V
+7.1 V
7.1 V p-to-p
(Min)
7.1 V p-to-p
(Min)
0 V
+3.6 V
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
12 Freescale Semiconductor
Power Characteristics
3 Power Characteristics
The estimated typical power dissipation for this family of PowerQUICC III devices is shown in Table 4.
Table 4. Power Dissipation(1) (2)
Notes:
1.
2.
CCB Frequency (MHz) Core Frequency (MHz) VDD Typical Power(3)(4) (W)
3.
4.
Maximum Power(5) (W)
5.
200 400 1.2 4.4 6.1
500 1.2 4.7 6.5
600 1.2 5.0 6.8
267 533 1.2 4.9 6.7
667 1.2 5.4 7.2
800 1.2 5.8 8.6
333 667 1.2 5.5 7.4
833 1.2 6.0 8.8
1000(6)
6.
1.3 9.0 12.2
Notes:
1. The values do not include I/O supply power (OVDD, LVDD, GVDD) or AVDD.
2. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance. Any customer design must take these considerations into account to ensure the maximum 105 degrees junction
temperature is not exceeded on this device.
3. Typical power is based on a nominal voltage of VDD = 1.2V, a nominal process, a junction temperature of Tj = 105° C, and a
Dhrystone 2.1 benchmark application.
4. Thermal solutions likely need to design to a value higher than Typical Power based on the end application, TA target, and I/O
power
5. Maximum power is based on a nominal voltage of VDD = 1.2V, worst case process, a junction temperature of Tj = 105° C, and
an artificial smoke test.
6. The nominal recommended VDD = 1.3V for this speed grade.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 13
Power Characteristics
Table 5. Typical I/O Power Dissipation
Interface Parameters GVDD
(2.5 V)
OVDD
(3.3 V)
LVDD
(3.3 V)
LVDD
(2.5 V) Unit Comments
DDR I/O CCB = 200 MHz 0.46 W
CCB = 266 MHz 0.59 W
CCB = 300 MHz 0.66 W
CCB = 333 MHz 0.73 W
PCI I/O 64b, 66 MHz 0.14 W
64b, 33 MHz 0.08 W
32b, 66 MHz 0.07 W Multiply by 2 if using two 32b ports
32b, 33 MHz 0.04 W
Local Bus I/O 32b, 167 MHz 0.30 W
32b, 133 MHz 0.24 W
32b, 83 MHz 0.16 W
32b, 66 MHz 0.13 W
32b, 33 MHz 0.07 W
TSEC I/O MII 0.01 W Multiply by number of interfaces
used.
GMII or TBI 0.07 W
RGMII or RTBI 0.04 W
CPM - FCC MII 0.015 W
RMII — 0.013 — W
HDLC 16 Mbps 0.009 W
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
14 Freescale Semiconductor
Clock Timing
4 Clock Timing
4.1 System Clock Timing
Table 6 provides the system clock (SYSCLK) AC timing specifications for the MPC8541E.
4.2 TSEC Gigabit Reference Clock Timing
Table 7 provides the TSEC gigabit reference clock (EC_GTX_CLK125) AC timing specifications for the
MPC8541E.
Table 6. SYSCLK AC Timing Specifications
Parameter/Condition Symbol Min Typical Max Unit Notes
SYSCLK frequency fSYSCLK ——166MHz1
SYSCLK cycle time tSYSCLK 6.0 ns —
SYSCLK rise and fall time tKH, tKL 0.6 1.0 1.2 ns 2
SYSCLK duty cycle tKHK/tSYSCLK 40 60 % 3
SYSCLK jitter +/- 150 ps 4, 5
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies.
2. Rise and fall times for SYSCLK are measured at 0.6 and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. For spread spectrum clocking, guidelines are ±1% of the input frequency with a maximum of 60 kHz of modulation regardless
of the input frequency.
Table 7. EC_GTX_CLK125 AC Timing Specifications
Parameter/Condition Symbol Min Typical Max Unit Notes
EC_GTX_CLK125 frequency fG125 125 MHz —
EC_GTX_CLK125 cycle time tG125 —8—ns
EC_GTX_CLK125 rise time tG125R ——1.0ns1
EC_GTX_CLK125 fall time tG125F ——1.0ns1
EC_GTX_CLK125 duty cycle
GMII, TBI
RGMII, RTBI
tG125H/tG125
45
47
55
53
%1, 2
Notes:
1. Timing is guaranteed by design and characterization.
2. EC_GTX_CLK125 is used to generate GTX clock for TSEC transmitter with 2% degradation. EC_GTX_CLK125 duty cycle
can be loosened from 47/53% as long as PHY device can tolerate the duty cycle generated by GTX_CLK of TSEC.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 15
RESET Initialization
4.3 Real Time Clock Timing
Table 8 provides the real time clock (RTC) AC timing specifications.
5 RESET Initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements of
the MPC8541E. Table 9 provides the RESET initialization AC timing specifications.
Table 10 provides the PLL and DLL lock times.
Table 8. RTC AC Timing Specifications
Parameter/Condition Symbol Min Typical Max Unit Notes
RTC clock high time tRTCH 2 x
tCCB_CLK
——ns
RTC clock low time tRTCL 2 x
tCCB_CLK
——ns
Table 9. RESET Initialization Timing Specifications
Parameter/Condition Min Max Unit Notes
Required assertion time of HRESET 100 — μs—
Minimum assertion time for SRESET 512 SYSCLKs 1
PLL input setup time with stable SYSCLK before HRESET
negation
100 — μs—
Input setup time for POR configs (other than PLL config) with
respect to negation of HRESET
4 SYSCLKs 1
Input hold time for POR configs (including PLL config) with
respect to negation of HRESET
2 SYSCLKs 1
Maximum valid-to-high impedance time for actively driven POR
configs with respect to negation of HRESET
5 SYSCLKs 1
Notes:
1. SYSCLK is identical to the PCI_CLK signal and is the primary clock input for the MPC8541E. See the
MPC8555E
PowerQUICC™ III Integrated Communications Processor Reference Manual
for more details.
Table 10. PLL and DLL Lock Times
Parameter/Condition Min Max Unit Notes
PLL lock times 100 μs—
DLL lock times 7680 122,880 CCB Clocks 1, 2
Notes:
1. DLL lock times are a function of the ratio between the output clock and the platform (or CCB) clock. A 2:1 ratio results in the
minimum and an 8:1 ratio results in the maximum.
2. The CCB clock is determined by the SYSCLK × platform PLL ratio.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
16 Freescale Semiconductor
DDR SDRAM
6 DDR SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the
MPC8541E.
6.1 DDR SDRAM DC Electrical Characteristics
Table 11 provides the recommended operating conditions for the DDR SDRAM component(s) of the
MPC8541E.
Table 12 provides the DDR capacitance.
Table 11. DDR SDRAM DC Electrical Characteristics
Parameter/Condition Symbol Min Max Unit Notes
I/O supply voltage GVDD 2.375 2.625 V 1
I/O reference voltage MVREF 0.49 × GVDD 0.51 × GVDD V2
I/O termination voltage VTT MVREF – 0.04 MVREF + 0.04 V 3
Input high voltage VIH MVREF + 0.18 GVDD + 0.3 V
Input low voltage VIL –0.3 MVREF – 0.18 V
Output leakage current IOZ –10 10 μA4
Output high current (VOUT = 1.95 V) IOH –15.2 mA —
Output low current (VOUT = 0.35 V) IOL 15.2 mA —
MVREF input leakage current IVREF —5μA—
Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF
. This rail should track variations in the DC level of MVREF
.
4. Output leakage is measured with all outputs disabled, 0 V VOUT GVDD.
Table 12. DDR SDRAM Capacitance
Parameter/Condition Symbol Min Max Unit Notes
Input/output capacitance: DQ, DQS, MSYNC_IN CIO 68pF1
Delta input/output capacitance: DQ, DQS CDIO —0.5pF1
Note:
1. This parameter is sampled. GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak to peak) = 0.2 V.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 17
DDR SDRAM
6.2 DDR SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM interface.
6.2.1 DDR SDRAM Input AC Timing Specifications
Table 13 provides the input AC timing specifications for the DDR SDRAM interface.
6.2.2 DDR SDRAM Output AC Timing Specifications
Table 14 and Table 15 provide the output AC timing specifications and measurement conditions for the
DDR SDRAM interface.
Table 13. DDR SDRAM Input AC Timing Specifications
At recommended operating conditions with GVDD of 2.5 V ± 5%.
Parameter Symbol Min Max Unit Notes
AC input low voltage VIL —MV
REF 0.31 V
AC input high voltage VIH MVREF + 0.31 GVDD + 0.3 V
MDQS—MDQ/MECC input skew per
byte
For DDR = 333 MHz
For DDR < 266 MHz
tDISKEW
750
1125
ps 1
Note:
1. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if 0 <= n <=
7) or ECC (MECC[{0...7}] if n = 8).
Table 14. DDR SDRAM Output AC Timing Specifications for Source Synchronous Mode
At recommended operating conditions with GVDD of 2.5 V ± 5%.
Parameter Symbol 1Min Max Unit Notes
MCK[n] cycle time, (MCK[n]/MCK[n] crossing) tMCK 610ns2
Skew between any MCK to ADDR/CMD
333 MHz
266 MHz
200 MHz
tAOSKEW
–1000
–1100
–1200
200
300
400
ps 3
ADDR/CMD output setup with respect to MCK
333 MHz
266 MHz
200 MHz
tDDKHAS
2.8
3.45
4.6
—ns4
ADDR/CMD output hold with respect to MCK
333 MHz
266 MHz
200 MHz
tDDKHAX
2.0
2.65
3.8
—ns4
MCS(n) output setup with respect to MCK
333 MHz
266 MHz
200 MHz
tDDKHCS
2.8
3.45
4.6
—ns4
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
18 Freescale Semiconductor
DDR SDRAM
MCS(n) output hold with respect to MCK
333 MHz
266 MHz
200 MHz
tDDKHCX
2.0
2.65
3.8
—ns4
MCK to MDQS
333 MHz
266 MHz
200 MHz
tDDKHMH
–0.9
–1.1
–1.2
0.3
0.5
0.6
ns 5
MDQ/MECC/MDM output setup with respect to
MDQS
333 MHz
266 MHz
200 MHz
tDDKHDS,
tDDKLDS
900
900
1200
—ps6
MDQ/MECC/MDM output hold with respect to
MDQS
333 MHz
266 MHz
200 MHz
tDDKHDX,
tDDKLDX
900
900
1200
—ps6
MDQS preamble start tDDKHMP –0.5 × tMCK – 0.9 –0.5 × tMCK +0.3 ns 7
MDQS epilogue end tDDKLME –0.9 0.3 ns 7
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until
outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock
reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. In the source synchronous mode, MCK/MCK can be shifted in 1/4 applied cycle increments through the Clock Control
Register. For the skew measurements referenced for tAOSKEW it is assumed that the clock adjustment is set to align the
address/command valid with the rising edge of MCK.
4. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the
ADDR/CMD setup and hold specifications, it is assumed that the Clock Control register is set to adjust the memory clocks
by 1/2 applied cycle. The MCSx pins are separated from the ADDR/CMD (address and command) bus in the HW spec. This
was separated because the MCSx pins typically have different loadings than the rest of the address and command bus,
even though they have the same timings.
5. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing
(DD) from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). In the source synchronous mode,
MDQS can launch later than MCK by 0.3 ns at the maximum. However, MCK may launch later than MDQS by as much as
0.9 ns. tDDKHMH can be modified through control of the DQSS override bits in the TIMING_CFG_2 register. In source
synchronous mode, this typically is set to the same delay as the clock adjust in the CLK_CNTL register. The timing
parameters listed in the table assume that these two parameters have been set to the same adjustment value. See the
MPC8555E PowerQUICC™ III Integrated Communications Processor Reference Manual
for a description and
understanding of the timing modifications enabled by use of these bits.
6. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the MPC8541E.
7. All outputs are referenced to the rising edge of MCK(n) at the pins of the MPC8541E. Note that tDDKHMP follows the symbol
conventions described in note 1.
Table 14. DDR SDRAM Output AC Timing Specifications for Source Synchronous Mode (continued)
At recommended operating conditions with GVDD of 2.5 V ± 5%.
Parameter Symbol 1Min Max Unit Notes
\ x x ‘N x x x x x 4,‘ ‘ x \ ~> Wrile A0
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 19
DDR SDRAM
Figure 4 shows the DDR SDRAM output timing for address skew with respect to any MCK.
Figure 4. Timing Diagram for tAOSKEW Measurement
Figure 5 shows the DDR SDRAM output timing diagram for the source synchronous mode.
Figure 5. DDR SDRAM Output Timing Diagram for Source Synchronous Mode
ADDR/CMD
tDDKHAS ,tDDKHCS
tDDKHMH
tDDKLDS
tDDKHDS
MDQ[x]
MDQS[n]
MCK[n]
MCK[n] tMCK
tDDKLDX
tDDKHDX
D1D0
tDDKHAX ,tDDKHCX
Write A0 NOOP
tDDKLME
tDDKHMP
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
20 Freescale Semiconductor
DUART
Figure 6 provides the AC test load for the DDR bus.
Figure 6. DDR AC Test Load
7DUART
This section describes the DC and AC electrical specifications for the DUART interface of the
MPC8541E.
7.1 DUART DC Electrical Characteristics
Table 16 provides the DC electrical characteristics for the DUART interface of the MPC8541E.
Table 15. DDR SDRAM Measurement Conditions
Symbol DDR Unit Notes
VTH MVREF ± 0.31 V V 1
VOUT 0.5 × GVDD V2
Notes:
1. Data input threshold measurement point.
2. Data output measurement point.
Table 16. DUART DC Electrical Characteristics
Parameter Symbol Test Condition Min Max Unit
High-level input voltage VIH VOUT VOH (min) or 2 OVDD + 0.3 V
Low-level input voltage VIL VOUT VOL (max) –0.3 0.8 V
Input current IIN VIN 1 = 0 V or VIN = VDD —±5 μA
High-level output voltage VOH OVDD = min,
IOH = –100 μA
OVDD – 0.2 V
Low-level output voltage VOL OVDD = min, IOL = 100 μA— 0.2 V
Note:
1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Ta ble 2.
Output Z0 = 50 ΩGVDD/2
RL = 50 Ω
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 21
Ethernet: Three-Speed, MII Management
7.2 DUART AC Electrical Specifications
Table 17 provides the AC timing parameters for the DUART interface of the MPC8541E.
8 Ethernet: Three-Speed, MII Management
This section provides the AC and DC electrical characteristics for three-speed, 10/100/1000, and MII
management.
8.1 Three-Speed Ethernet Controller (TSEC)
(10/100/1000 Mbps)—GMII/MII/TBI/RGMII/RTBI Electrical
Characteristics
The electrical characteristics specified here apply to all GMII (gigabit media independent interface), the
MII (media independent interface), TBI (ten-bit interface), RGMII (reduced gigabit media independent
interface), and RTBI (reduced ten-bit interface) signals except MDIO (management data input/output) and
MDC (management data clock). The RGMII and RTBI interfaces are defined for 2.5 V, while the GMII
and TBI interfaces can be operated at 3.3 V or 2.5 V. Whether the GMII, MII, or TBI interface is operated
at 3.3 or 2.5 V, the timing is compliant with the IEEE 802.3 standard. The RGMII and RTBI interfaces
follow the Hewlett-Packard reduced pin-count interface for Gigabit Ethernet Physical Layer Device
Specification Version 1.2a (9/22/2000). The electrical characteristics for MDIO and MDC are specified in
Section 8.3, “Ethernet Management Interface Electrical Characteristics.”
8.1.1 TSEC DC Electrical Characteristics
All GMII, MII, TBI, RGMII, and RTBI drivers and receivers comply with the DC parametric attributes
specified in Table 18 and Table 19. The potential applied to the input of a GMII, MII, TBI, RGMII, or
RTBI receiver may exceed the potential of the receivers power supply (for example, a GMII driver
powered from a 3.6-V supply driving VOH into a GMII receiver powered from a 2.5-V supply). Tolerance
for dissimilar GMII driver and receiver supply potentials is implicit in these specifications. The RGMII
and RTBI signals are based on a 2.5-V CMOS interface voltage as defined by JEDEC EIA/JESD8-5.
Table 17. DUART AC Timing Specifications
Parameter Value Unit Notes
Minimum baud rate fCCB_CLK / 1048576 baud 3
Maximum baud rate fCCB_CLK / 16 baud 1, 3
Oversample rate 16 2, 3
Notes:
1. Actual attainable baud rate is limited by the latency of interrupt processing.
2. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start
bit. Subsequent bit values are sampled each 16th sample.
3. Guaranteed by design.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
22 Freescale Semiconductor
Ethernet: Three-Speed, MII Management
Table 18. GMII, MII, and TBI DC Electrical Characteristics
Parameter Symbol Conditions Min Max Unit
Supply voltage 3.3 V LVDD 3.13 3.47 V
Output high voltage VOH IOH = –4.0 mA LVDD = Min 2.40 LVDD + 0.3 V
Output low voltage VOL IOL = 4.0 mA LVDD = Min GND 0.50 V
Input high voltage VIH 1.70 LVDD + 0.3 V
Input low voltage VIL –0.3 0.90 V
Input high current IIH VIN 1 = LVDD —40μA
Input low current IIL VIN 1 = GND –600 μA
Note:
1. The symbol VIN, in this case, represents the LVIN symbol referenced in Ta bl e 1 and Ta bl e 2 .
Table 19. GMII, MII, RGMII RTBI, and TBI DC Electrical Characteristics
Parameters Symbol Min Max Unit
Supply voltage 2.5 V LVDD 2.37 2.63 V
Output high voltage (LVDD = Min, IOH = –1.0 mA) VOH 2.00 LVDD + 0.3 V
Output low voltage (LVDD = Min, IOL = 1.0 mA) VOL GND – 0.3 0.40 V
Input high voltage (LVDD = Min) VIH 1.70 LVDD + 0.3 V
Input low voltage (LVDD = Min) VIL –0.3 0.70 V
Input high current (VIN 1 = LVDD)I
IH —10μA
Input low current (VIN 1 = GND) IIL –15 μA
Note:
1. Note that the symbol VIN, in this case, represents the LVIN symbol referenced in Ta b l e 1 and Ta b le 2 .
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 23
Ethernet: Three-Speed, MII Management
8.2 GMII, MII, TBI, RGMII, and RTBI AC Timing Specifications
The AC timing specifications for GMII, MII, TBI, RGMII, and RTBI are presented in this section.
8.2.1 GMII AC Timing Specifications
This section describes the GMII transmit and receive AC timing specifications.
8.2.2 GMII Transmit AC Timing Specifications
Table 20 provides the GMII transmit AC timing specifications.
Figure 7 shows the GMII transmit AC timing diagram.
Figure 7. GMII Transmit AC Timing Diagram
Table 20. GMII Transmit AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V ± 5%.
Parameter/Condition Symbol 1Min Typ Max Unit
GTX_CLK clock period tGTX —8.0— ns
GTX_CLK duty cycle tGTXH/tGTX 40 — 60 %
GMII data TXD[7:0], TX_ER, TX_EN setup time tGTKHDV 2.5——ns
GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay tGTKHDX 0.5 5.0 ns
GTX_CLK data clock rise and fall times tGTXR3, tGTXR2,4 ——1.0ns
Notes:
1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGTKHDV symbolizes GMII
transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input
signals (D) reaching the valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII transmit timing (GT) with respect
to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold
time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a
particular functional. For example, the subscript of tGTX represents the GMII(G) transmit (TX) clock. For rise and fall times,
the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3. Guaranteed by characterization.
4. Guaranteed by design.
GTX_CLK
TXD[7:0]
tGTKHDX
tGTX
tGTXH
tGTXR
tGTXF
tGTKHDV
TX_EN
TX_ER
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
24 Freescale Semiconductor
Ethernet: Three-Speed, MII Management
8.2.2.1 GMII Receive AC Timing Specifications
Table 21 provides the GMII receive AC timing specifications.
Figure 8 provides the AC test load for TSEC.
Figure 8. TSEC AC Test Load
Figure 9 shows the GMII receive AC timing diagram.
Figure 9. GMII Receive AC Timing Diagram
Table 21. GMII Receive AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V ± 5%.
Parameter/Condition Symbol 1Min Typ Max Unit
RX_CLK clock period tGRX —8.0— ns
RX_CLK duty cycle tGRXH/tGRX 40 — 60 %
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK tGRDVKH 2.0 — ns
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK tGRDXKH 0.5 — ns
RX_CLK clock rise and fall time tGRXR, tGRXF 2,3 ——1.0ns
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGRDVKH
symbolizes GMII receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to
the tRX clock reference (K) going to the high state (H) or setup time. Also, tGRDXKL symbolizes GMII receive timing (GR)
with respect to the time data input signals (D) went invalid (X) relative to the tGRX clock reference (K) going to the low (L)
state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing
the clock of a particular functional. For example, the subscript of tGRX represents the GMII (G) receive (RX) clock. For rise
and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3. Guaranteed by design.
Output Z0 = 50 ΩLV DD/2
RL = 50 Ω
RX_CLK
RXD[7:0]
tGRDXKH
tGRX
tGRXH
tGRXR
tGRXF
tGRDVKH
RX_DV
RX_ER
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 25
Ethernet: Three-Speed, MII Management
8.2.3 MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
8.2.3.1 MII Transmit AC Timing Specifications
Table 22 provides the MII transmit AC timing specifications.
Figure 10 shows the MII transmit AC timing diagram.
Figure 10. MII Transmit AC Timing Diagram
Table 22. MII Transmit AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V ± 5%.
Parameter/Condition Symbol 1Min Typ Max Unit
TX_CLK clock period 10 Mbps tMTX2— 400 — ns
TX_CLK clock period 100 Mbps tMTX —40ns
TX_CLK duty cycle tMTXH/tMTX 35 — 65 %
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay tMTKHDX 1515ns
TX_CLK data clock rise and fall time tMTXR, tMTXF 2,3 1.0 — 4.0 ns
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX
symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid
(X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock
of a particular functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3. Guaranteed by design.
TX_CLK
TXD[3:0]
tMTKHDX
tMTX
tMTXH
tMTXR
tMTXF
TX_EN
TX_ER
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
26 Freescale Semiconductor
Ethernet: Three-Speed, MII Management
8.2.3.2 MII Receive AC Timing Specifications
Table 23 provides the MII receive AC timing specifications.
Figure 11 shows the MII receive AC timing diagram.
Figure 11. MII Receive AC Timing Diagram
Table 23. MII Receive AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V ± 5%.
Parameter/Condition Symbol 1Min Typ Max Unit
RX_CLK clock period 10 Mbps tMRX2—400— ns
RX_CLK clock period 100 Mbps tMRX —40—ns
RX_CLK duty cycle tMRXH/tMRX 35 — 65 %
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK tMRDVKH 10.0 — ns
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK tMRDXKH 10.0 — ns
RX_CLK clock rise and fall time tMRXR, tMRXF 2,3 1.0 4.0 ns
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII
receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference
(K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data
input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is
used with the appropriate letter: R (rise) or F (fall).
2. Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3.Guaranteed by design.
RX_CLK
RXD[3:0]
tMRDXKH
tMRX
tMRXH
tMRXR
tMRXF
RX_DV
RX_ER
tMRDVKH
Valid Data
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 27
Ethernet: Three-Speed, MII Management
8.2.4 TBI AC Timing Specifications
This section describes the TBI transmit and receive AC timing specifications.
8.2.4.1 TBI Transmit AC Timing Specifications
Table 24 provides the MII transmit AC timing specifications.
Figure 12 shows the TBI transmit AC timing diagram.
Figure 12. TBI Transmit AC Timing Diagram
Table 24. TBI Transmit AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V ± 5%.
Parameter/Condition Symbol 1Min Typ Max Unit
GTX_CLK clock period tTTX —8.0— ns
GTX_CLK duty cycle tTTXH/tTTX 40 — 60 %
GMII data TCG[9:0], TX_ER, TX_EN setup time
GTX_CLK going high
tTTKHDV 2.0 — ns
GMII data TCG[9:0], TX_ER, TX_EN hold time from
GTX_CLK going high
tTTKHDX 1.0 — ns
GTX_CLK clock rise and fall time tTTXR, tTTXF 2,3 ——1.0ns
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state
)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV
symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data
signals (D) reach the valid state (V) or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to the
time from tTTX (K) going high (H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in
general, the clock reference symbol representation is based on three letters representing the clock of a particular
functional. For example, the subscript of tTTX represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
2. Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3. Guaranteed by design.
GTX_CLK
TCG[9:0]
tTTXR
tTTX
tTTXH
tTTXR
tTTXF
tTTKHDV
tTTKHDX
tTTXF
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
28 Freescale Semiconductor
Ethernet: Three-Speed, MII Management
8.2.4.2 TBI Receive AC Timing Specifications
Table 25 provides the TBI receive AC timing specifications.
Figure 13 shows the TBI receive AC timing diagram.
Figure 13. TBI Receive AC Timing Diagram
Table 25. TBI Receive AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V ± 5%.
Parameter/Condition Symbol 1Min Typ Max Unit
RX_CLK clock period tTRX 16.0 ns
RX_CLK skew tSKTRX 7.5 8.5 ns
RX_CLK duty cycle tTRXH/tTRX 40 — 60 %
RCG[9:0] setup time to rising RX_CLK tTRDVKH 2.5 — ns
RCG[9:0] hold time to rising RX_CLK tTRDXKH 1.5 ns
RX_CLK clock rise time and fall time tTRXR, tTRXF 2,3 0.7 — 2.4 ns
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTRDVKH
symbolizes TBI receive timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the
tTRX clock reference (K) going to the high (H) state or setup time. Also, tTRDXKH symbolizes TBI receive timing (TR) with
respect to the time data input signals (D) went invalid (X) relative to the tTRX clock reference (K) going to the high (H) state.
Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a
particular functional. For example, the subscript of tTRX represents the TBI (T) receive (RX) clock. For rise and fall times,
the latter convention is used with the appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript is
skew (SK) followed by the clock that is being skewed (TRX).
2. Guaranteed by design.
RX_CLK1
RXD[9:0]
tTRX
tTRXH
tTRXR
tTRXF
tTRDVKH
RX_CLK0
tTRDXKH
tTRDVKH
tTRDXKH
tSKTRX
tTRXH
Valid Data Valid Data
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 29
Ethernet: Three-Speed, MII Management
8.2.5 RGMII and RTBI AC Timing Specifications
Table 26 presents the RGMII and RTBI AC timing specifications.
Table 26. RGMII and RTBI AC Timing Specifications
At recommended operating conditions with LVDD of 2.5 V ± 5%.
Parameter/Condition Symbol 1Min Typ Max Unit
Data to clock output skew (at transmitter) tSKRGT5–500 0 500 ps
Data to clock input skew (at receiver) 2tSKRGT 1.0 2.8 ns
Clock cycle duration 3tRGT67.2 8.0 8.8 ns
Duty cycle for 1000Base-T 4tRGTH/tRGT645 50 55 %
Duty cycle for 10BASE-T and 100BASE-TX 3tRGTH/tRGT640 50 60 %
Rise and fall times tRGTR6,7, tRGTF6,7 0.75 ns
Notes:
1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent
RGMII and RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (RX) clock. Note also that the
notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews,
the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. The RGMII specification requires that PC board designer add 1.5 ns or greater in trace delay to the RX_CLK in order to
meet this specification. However, as stated above, this device functions with only 1.0 ns of delay.
3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as
long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed
transitioned between.
5. Guaranteed by characterization.
6. Guaranteed by design.
7. Signal timings are measured at 0.5 and 2.0 V voltage levels.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
30 Freescale Semiconductor
Ethernet: Three-Speed, MII Management
Figure 14 shows the RBMII and RTBI AC timing and multiplexing diagrams.
Figure 14. RGMII and RTBI AC Timing and Multiplexing Diagrams
8.3 Ethernet Management Interface Electrical Characteristics
The electrical characteristics specified here apply to MII management interface signals MDIO
(management data input/output) and MDC (management data clock). The electrical characteristics for
GMII, RGMII, TBI and RTBI are specified in Section 8.1, “Three-Speed Ethernet Controller (TSEC)
(10/100/1000 Mbps)—GMII/MII/TBI/RGMII/RTBI Electrical Characteristics.”
8.3.1 MII Management DC Electrical Characteristics
The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics
for MDIO and MDC are provided in Table 27.
Table 27. MII Management DC Electrical Characteristics
Parameter Symbol Conditions Min Max Unit
Supply voltage (3.3 V) OVDD —3.133.47V
Output high voltage VOH IOH = –1.0 mA LVDD = Min 2.10 LVDD + 0.3 V
Output low voltage VOL IOL = 1.0 mA LVDD = Min GND 0.50 V
Input high voltage VIH —1.70V
Input low voltage VIL 0.90 V
GTX_CLK
tRGT
tRGTH
tSKRGT
TX_CTL
TXD[8:5]
TXD[7:4]
TXD[9]
TXERR
TXD[4]
TXEN
TXD[3:0]
(At Transmitter)
TXD[8:5][3:0]
TXD[7:4][3:0]
TX_CLK
(At PHY)
RX_CTL
RXD[8:5]
RXD[7:4]
RXD[9]
RXERR
RXD[4]
RXDV
RXD[3:0]
RXD[8:5][3:0]
RXD[7:4][3:0]
RX_CLK
(At PHY)
tSKRGT
tSKRGT
tSKRGT
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 31
Ethernet: Three-Speed, MII Management
8.3.2 MII Management AC Electrical Specifications
Table 28 provides the MII management AC timing specifications.
Input high current IIH LVDD = Max VIN 1 = 2.1 V 40 μA
Input low current IIL LVDD = Max VIN = 0.5 V –600 μA
Note:
1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Ta b l e 2 .
Table 28. MII Management AC Timing Specifications
At recommended operating conditions with LVDD is 3.3 V ± 5%.
Parameter/Condition Symbol 1Min Typ Max Unit Notes
MDC frequency fMDC 0.893 10.4 MHz 2
MDC period tMDC 96 1120 ns
MDC clock pulse width high tMDCH 32 — ns
MDC to MDIO valid tMDKHDV 2*[1/(fccb_clk/8)] ns 3
MDC to MDIO delay tMDKHDX 10 — 2*[1/(fccb_clk/8)] ns 3
MDIO to MDC setup time tMDDVKH 5— —ns
MDIO to MDC hold time tMDDXKH 0— —ns
MDC rise time tMDCR 10 ns
MDC fall time tMDHF 10 ns
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX
symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are
invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input
signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For
rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the system clock speed (that is, for a system clock of 267 MHz, the delay is 70 ns and for
a system clock of 333 MHz, the delay is 58 ns).
3. This parameter is dependent on the CCB clock speed (that is, for a CCB clock of 267 MHz, the delay is 60 ns and for a
CCB clock of 333 MHz, the delay is 48 ns).
4. Guaranteed by design.
Table 27. MII Management DC Electrical Characteristics (continued)
Parameter Symbol Conditions Min Max Unit
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
32 Freescale Semiconductor
Local Bus
Figure 15 shows the MII management AC timing diagram.
Figure 15. MII Management Interface Timing Diagram
9 Local Bus
This section describes the DC and AC electrical specifications for the local bus interface of the
MPC8541E.
9.1 Local Bus DC Electrical Characteristics
Table 29 provides the DC electrical characteristics for the local bus interface.
Table 29. Local Bus DC Electrical Characteristics
Parameter Symbol Test Condition Min Max Unit
High-level input voltage VIH VOUT VOH (min) or 2 OVDD + 0.3 V
Low-level input voltage VIL VOUT VOL (max) –0.3 0.8 V
Input current IIN VIN 1 = 0 V or VIN = VDD —±5 μA
High-level output voltage VOH OVDD = min,
IOH = –2mA
OVDD –0.2 V
Low-level output voltage VOL OVDD = min, IOL = 2mA 0.2 V
Note:
1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Ta b l e 1 and Ta bl e 2 .
MDC
tMDDXKH
tMDC
tMDCH
tMDCR
tMDCF
tMDDVKH
tMDKHDX
MDIO
MDIO
(Input)
(Output)
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 33
Local Bus
9.2 Local Bus AC Electrical Specifications
Table 30 describes the general timing parameters of the local bus interface of the MPC8541E with the DLL
enabled.
Table 30. Local Bus General Timing Parameters—DLL Enabled
Parameter Configuration 7Symbol 1Min Max Unit Notes
Local bus cycle time tLBK 6.0 — ns 2
LCLK[n] skew to LCLK[m] or LSYNC_OUT tLBKSKEW 150 ps 7, 9
Input setup to local bus clock (except
LUPWAIT)
tLBIVKH1 1.8 ns 3, 4, 8
LUPWAIT input setup to local bus clock tLBIVKH2 1.7 ns 3, 4
Input hold from local bus clock (except
LUPWAIT)
tLBIXKH1 0.5 ns 3, 4, 8
LUPWAIT input hold from local bus clock tLBIXKH2 1.0 ns 3, 4
LALE output transition to LAD/LDP output
transition (LATCH hold time)
tLBOTOT 1.5 — ns 6
Local bus clock to output valid (except
LAD/LDP and LALE)
LWE[0:1] = 00 tLBKHOV1 2.3 ns 3, 8
LWE[0:1] = 11 (default) 3.8
Local bus clock to data valid for LAD/LDP LWE[0:1] = 00 tLBKHOV2 2.5 ns 3, 8
LWE[0:1] = 11 (default) 4.0
Local bus clock to address valid for LAD LWE[0:1] = 00 tLBKHOV3 2.6 ns 3, 8
LWE[0:1] = 11 (default) 4.1
Output hold from local bus clock (except
LAD/LDP and LALE)
LWE[0:1] = 00 tLBKHOX1 0.7 ns 3, 8
LWE[0:1] = 11 (default) 1.6
Output hold from local bus clock for
LAD/LDP
LWE[0:1] = 00 tLBKHOX2 0.7 ns 3, 8
LWE[0:1] = 11 (default) 1.6
Local bus clock to output high Impedance
(except LAD/LDP and LALE)
LWE[0:1] = 00 tLBKHOZ1 2.8 ns 5, 9
LWE[0:1] = 11 (default) 4.2
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
34 Freescale Semiconductor
Local Bus
Table 31 describes the general timing parameters of the local bus interface of the MPC8541E with the DLL
bypassed.
Local bus clock to output high impedance for
LAD/LDP
LWE[0:1] = 00 tLBKHOZ2 2.8 ns 5, 9
LWE[0:1] = 11 (default) 4.2
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1
symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes
high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go
high (H), with respect to the output (O) going invalid (X) or output hold time.
2. All timings are in reference to LSYNC_IN for DLL enabled mode.
3. All signals are measured from OVDD/2 of the rising edge of LSYNC_IN for DLL enabled to 0.4 ×OVDD of the signal in
question for 3.3-V signaling levels.
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
6. The value of tLBOTOT is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by LBCR[AHD], and the number of
local bus buffer delays used as programmed at power-on reset with configuration pins LWE[0:1].
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at OVDD/2.
8. Guaranteed by characterization.
9. Guaranteed by design.
Table 31. Local Bus General Timing Parameters—DLL Bypassed
Parameter Configuration 7Symbol 1Min Max Unit Notes
Local bus cycle time tLBK 6.0 — ns 2
Internal launch/capture clock to LCLK delay tLBKHKT 1.8 3.4 ns 8
LCLK[n] skew to LCLK[m] or LSYNC_OUT tLBKSKEW 150 ps 7, 9
Input setup to local bus clock (except
LUPWAIT)
—t
LBIVKH1 5.2 ns 3, 4
LUPWAIT input setup to local bus clock tLBIVKH2 5.1 ns 3, 4
Input hold from local bus clock (except
LUPWAIT)
—t
LBIXKH1 –1.3 ns 3, 4
LUPWAIT input hold from local bus clock tLBIXKH2 –0.8 ns 3, 4
LALE output transition to LAD/LDP output
transition (LATCH hold time)
—t
LBOTOT 1.5 — ns 6
Local bus clock to output valid (except
LAD/LDP and LALE)
LWE[0:1] = 00 tLBKLOV1 —0.5ns 3
LWE[0:1] = 11 (default) 2.0
Local bus clock to data valid for LAD/LDP LWE[0:1] = 00 tLBKLOV2 —0.7ns 3
LWE[0:1] = 11 (default) 2.2
Table 30. Local Bus General Timing Parameters—DLL Enabled (continued)
Parameter Configuration 7Symbol 1Min Max Unit Notes
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 35
Local Bus
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus
timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for
clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the
output (O) going invalid (X) or output hold time.
2. All timings are in reference to LSYNC_IN for DLL enabled mode.
3. All signals are measured from OVDD/2 of the rising edge of local bus clock for DLL bypass mode to 0.4 ×OVDD of the signal
in question for 3.3-V signaling levels.
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
6. The value of tLBOTOT is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by LBCR[AHD], and the number of local
bus buffer delays used as programmed at power-on reset with configuration pins LWE[0:1].
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at OVDD/2.
8. Guaranteed by characterization.
9. Guaranteed by design.
Figure 16 provides the AC test load for the local bus.
Figure 16. Local Bus C Test Load
Local bus clock to address valid for LAD LWE[0:1] = 00 tLBKLOV3 —0.8ns 3
LWE[0:1] = 11 (default) 2.3
Output hold from local bus clock (except
LAD/LDP and LALE)
LWE[0:1] = 00 tLBKLOX1 –2.7 — ns 3
LWE[0:1] = 11 (default) –1.8
Output hold from local bus clock for LAD/LDP LWE[0:1] = 00 tLBKLOX2 –2.7 — ns 3
LWE[0:1] = 11 (default) –1.8
Local bus clock to output high Impedance
(except LAD/LDP and LALE)
LWE[0:1] = 00 tLBKLOZ1 —1.0ns 5
LWE[0:1] = 11 (default) 2.4
Local bus clock to output high impedance for
LAD/LDP
LWE[0:1] = 00 tLBKLOZ2 —1.0ns 5
LWE[0:1] = 11 (default) 2.4
Table 31. Local Bus General Timing Parameters—DLL Bypassed (continued)
Parameter Configuration 7Symbol 1Min Max Unit Notes
Output Z0 = 50 ΩOVDD/2
RL = 50 Ω
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
36 Freescale Semiconductor
Local Bus
Figure 17 to Figure 22 show the local bus signals.
Figure 17. Local Bus Signals, Nonspecial Signals Only (DLL Enabled)
Output Signals:
LA[27:31]/LBCTL/LBCKE/LOE/
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
tLBKHOV1
tLBKHOV2
tLBKHOV3
LSYNC_IN
Input Signals:
LAD[0:31]/LDP[0:3]
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
Output (Address) Signal:
LAD[0:31]
LALE
tLBIXKH1
tLBIVKH1
tLBIVKH1
tLBIXKH1
tLBKHOX1
tLBKHOZ1
tLBKHOX2
tLBKHOZ2
Input Signal:
LGTA
tLBOTOT
tLBKHOZ2
tLBKHOX2
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 37
Local Bus
Figure 18. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode)
Output Signals:
LA[27:31]/LBCTL/LBCKE/LOE/
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
tLBKLOV2
LCLK[n]
Input Signals:
LAD[0:31]/LDP[0:3]
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
LALE
tLBIXKH1
Input Signal:
LGTA
Output (Address) Signal:
LAD[0:31]
tLBIVKH1
tLBIXKH2
tLBIVKH2
tLBKLOX1
tLBKLOZ2
tLBOTOT
Internal launch/capture clock
tLBKLOX2
tLBKLOV1
tLBKLOV3
tLBKLOZ1
tLBKHKT
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
38 Freescale Semiconductor
Local Bus
Figure 19. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Enabled)
LSYNC_IN
UPM Mode Input Signal:
LUPWAIT
tLBIXKH2
tLBIVKH2
tLBIVKH1
tLBIXKH1
tLBKHOZ1
T1
T3
Input Signals:
LAD[0:31]/LDP[0:3]
UPM Mode Output Signals:
LCS[0:7]/LBS[0:3]/LGPL[0:5]
GPCM Mode Output Signals:
LCS[0:7]/LWE
tLBKHOV1
tLBKHOV1
tLBKHOZ1
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 39
Local Bus
Figure 20. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Bypass Mode)
Internal launch/capture clock
UPM Mode Input Signal:
LUPWAIT
T1
T3
Input Signals:
LAD[0:31]/LDP[0:3]
UPM Mode Output Signals:
LCS[0:7]/LBS[0:3]/LGPL[0:5]
GPCM Mode Output Signals:
LCS[0:7]/LWE
tLBKLOV1
tLBKLOZ1
(DLL Bypass Mode)
LCLK
tLBKLOX1
tLBIVKH2 tLBIXKH2
tLBIVKH1
tLBIXKH1
tLBKHKT
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
40 Freescale Semiconductor
Local Bus
Figure 21. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 or 8 (DLL Enabled)
LSYNC_IN
UPM Mode Input Signal:
LUPWAIT
tLBIXKH2
tLBIVKH2
tLBIVKH1
tLBKHOZ1
T1
T3
UPM Mode Output Signals:
LCS[0:7]/LBS[0:3]/LGPL[0:5]
GPCM Mode Output Signals:
LCS[0:7]/LWE
tLBKHOV1
tLBKHOV1
tLBKHOZ1
T2
T4
Input Signals:
LAD[0:31]/LDP[0:3]
tLBIXKH1
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 41
Local Bus
Figure 22. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 or 8 (DLL Bypass Mode)
Internal launch/capture clock
UPM Mode Input Signal:
LUPWAIT
T1
T3
UPM Mode Output Signals:
LCS[0:7]/LBS[0:3]/LGPL[0:5]
GPCM Mode Output Signals:
LCS[0:7]/LWE
T2
T4
Input Signals:
LAD[0:31]/LDP[0:3]
(DLL Bypass Mode)
LCLK
tLBKLOV1
tLBKLOZ1
tLBKLOX1
t
LBIVKH2
tLBIXKH2
t
LBIVKH1
tLBIXKH1
tLBKHKT
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
42 Freescale Semiconductor
CPM
10 CPM
This section describes the DC and AC electrical specifications for the CPM of the MPC8541E.
10.1 CPM DC Electrical Characteristics
Table 32 provides the DC electrical characteristics for the CPM.
10.2 CPM AC Timing Specifications
Table 33 and Table 34 provide the CPM input and output AC timing specifications, respectively.
NOTE: Rise/Fall Time on CPM Input Pins
It is recommended that the rise/fall time on CPM input pins should not
exceed 5 ns. This should be enforced especially on clock signals. Rise time
refers to signal transitions from 10% to 90% of VCC; fall time refers to
transitions from 90% to 10% of VCC.
Table 32. CPM DC Electrical Characteristics
Characteristic Symbol Condition Min Max Unit Notes
Input high voltage VIH 2.0 3.465 V 1
Input low voltage VIL GND 0.8 V 1, 2
Output high voltage VOH IOH = –8.0 mA 2.4 V 1
Output low voltage VOL IOL = 8.0 mA 0.5 V 1
Output high voltage VOH IOH = –2.0 mA 2.4 V 1
Output low voltage VOL IOL = 3.2 mA 0.4 V 1
Table 33. CPM Input AC Timing Specifications 1
Characteristic Symbol
2Min3Unit
FCC inputs—internal clock (NMSI) input setup time tFIIVKH 6ns
FCC inputs—internal clock (NMSI) hold time tFIIXKH 0ns
FCC inputs—external clock (NMSI) input setup time tFEIVKH 2.5 ns
FCC inputs—external clock (NMSI) hold time tFEIXKHb2 ns
SPI inputs—internal clock (NMSI) input setup time tNIIVKH 6ns
SPI inputs—internal clock (NMSI) input hold time tNIIXKH 0ns
SPI inputs—external clock (NMSI) input setup time tNEIVKH 4ns
SPI inputs—external clock (NMSI) input hold time tNEIXKH 2ns
PIO inputs—input setup time tPIIVKH 8ns
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 43
CPM
Figure 23 provides the AC test load for the CPM.
Figure 23. CPM AC Test Load
PIO inputs—input hold time tPIIXKH 1ns
COL width high (FCC) tFCCH 1.5 CLK
Notes:
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings
are measured at the pin.
2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFIIVKH
symbolizes the FCC inputs internal timing (FI) with respect to the time the input signals (I) reaching the valid state (V)
relative to the reference clock tFCC (K) going to the high (H) state or setup time.
3. PIO and TIMER inputs and outputs are asynchronous to SYSCLK or any other externally visible clock. PIO/TIMER inputs
are internally synchronized to the CPM internal clock. PIO/TIMER outputs should be treated as asynchronous.
Table 34. CPM Output AC Timing Specifications 1
Characteristic Symbol
2Min Max Unit
FCC outputs—internal clock (NMSI) delay tFIKHOX 15.5ns
FCC outputs—external clock (NMSI) delay tFEKHOX 28ns
SPI outputs—internal clock (NMSI) delay tNIKHOX 0.5 10 ns
SPI outputs—external clock (NMSI) delay tNEKHOX 28ns
PIO outputs delay tPIKHOX 111ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFIKHOX symbolizes the FCC
inputs internal timing (FI) for the time tFCC memory clock reference (K) goes from the high state (H) until outputs (O) are
invalid (X).
Table 33. CPM Input AC Timing Specifications 1 (continued)
Characteristic Symbol
2Min3Unit
Output Z0 = 50 ΩOVDD/2
RL = 50 Ω
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
44 Freescale Semiconductor
CPM
Figure 24 through Figure 29 represent the AC timing from Table 33 and Table 34. Note that although the
specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when
the falling edge is the active edge.
Figure 24 shows the FCC internal clock.
Figure 24. FCC Internal AC Timing Clock Diagram
Figure 25 shows the FCC external clock.
Figure 25. FCC External AC Timing Clock Diagram
Figure 26 shows Ethernet collision timing on FCCs.
Figure 26. Ethernet Collision AC Timing Diagram (FCC)
FCC Output Signals
(When GFMR TCI = 1)
tFIKHOX
BRG_OUT
tFIIXKH
tFIIVKH
FCC Input Signals
FCC Output Signals
(When GFMR TCI = 0)
tFIKHOX
FCC Output Signals
(When GFMR TCI = 1)
tFEKHOX
Serial CLKIN
tFEIXKH
tFEIVKH
FCC Input Signals
FCC Output Signals
(When GFMR TCI = 0)
tFEKHOX
COL
(Input)
tFCCH
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 45
CPM
Figure 27 shows the SPI external clock.
Figure 27. SPI AC Timing External Clock Diagram
Figure 28 shows the SPI internal clock.
Figure 28. SPI AC Timing Internal Clock Diagram
NOTE
1 SPI AC timings are internal mode when it is master because SPICLK is an
output, and external mode when it is slave.
2 SPI AC timings refer always to SPICLK.
Figure 29. PIO Signal Diagram
Serial CLKIN
tNEIXKH
tNEIVKH
tNEKHOX
Input Signals:
(See Note)
Output Signals:
(See Note)
Note:
SPI
SPI
The clock edge is selectable on SPI.
BRG_OUT
tNIIXKH
tNIKHOX
Input Signals:
(See Note)
Output Signals:
(See Note)
Note:
tNIIVKH
SPI
SPI
The clock edge is selectable on SPI.
Sys clk
PIO inputs
PIO outputs
tPIIVKH
tPIIXKH
tPIKHOX
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
46 Freescale Semiconductor
CPM
10.3 CPM I2C AC Specification
Figure 30. CPM I2C Bus Timing Diagram
Table 35. I2C Timing
Characteristic Expression All Frequencies Unit
Min Max
SCL clock frequency (slave) fSCL 0F
MAX(1)
Notes:
1. FMAX = BRGCLK/(min_divider*prescale. Where prescaler=25-I2MODE[PDIV]; and min_divider=12 if digital filter disabled
and 18 if enabled.
Example #1: if I2MODE[PDIV]=11 (prescaler=4) and I2MODE[FLT]=0 (digital filter disabled) then FMAX=BRGCLK/48
Example #2: if I2MODE[PDIV]=00 (prescaler=32) and I2MODE[FLT]=1 (digital filter enabled) then FMAX=BRGCLK/576
Hz
SCL clock frequency (master) fSCL BRGCLK/16512 BRGCLK/48 Hz
Bus free time between transmissions tSDHDL 1/(2.2 * fSCL)—s
Low period of SCL tSCLCH 1/(2.2 * fSCL)—s
High period of SCL tSCHCL 1/(2.2 * fSCL)—s
Start condition setup time2tSCHDL 2/(divider * fSCL) (2)
2. divider = fSCL/prescaler.
In master mode: divider=BRGCLK/(fSCL*prescaler)=2*(I2BRG[DIV]+3)
In slave mode: divider=BRGCLK/(fSCL*prescaler)
s
Start condition hold time2tSDLCL 3/(divider * fSCL)— s
Data hold time 2tSCLDX 2/(divider * fSCL)— s
Data setup time2tSDVCH 3/(divider * fSCL)— s
SDA/SCL rise time tSRISE —1/(10 * f
SCL)s
SDA/SCL fall time tSFALL —1/(33 * f
SCL)s
Stop condition setup time tSCHDH 2/(divider * fSCL) — s
SCL
SDA
tSDHDL tSCLCH tSCHCL
tSCHDL
tSDLCL
tSCLDX tSDVCH
tSRISE tSFALL tSCHDH
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 47
CPM
The following two tables are examples of I2C AC parameters at I2C clock value of 100k and 400k
respectively.
Table 36. CPM I2C Timing (fSCL=100 kHz)
Characteristic Expression
Frequency = 100 kHz
Unit
Min Max
SCL clock frequency (slave) fSCL 100 kHz
SCL clock frequency (master) fSCL 100 kHz
Bus free time between transmissions tSDHDL 4.7 μs
Low period of SCL tSCLCH 4.7 μs
High period of SCL tSCHCL 4—μs
Start condition setup time tSCHDL 2— μs
Start condition hold time tSDLCL 3—μs
Data hold time tSCLDX 2—μs
Data setup time tSDVCH 3—μs
SDA/SCL rise time tSRISE —1μs
SDA/SCL fall time (master) tSFALL 303 ns
Stop condition setup time tSCHDH 2—μs
Table 37. CPM I2C Timing (fSCL=400 kHz)
Characteristic Expression
Frequency = 400 kHz
Unit
Min Max
SCL clock frequency (slave) fSCL 400 kHz
SCL clock frequency (master) fSCL 400 kHz
Bus free time between transmissions tSDHDL 1.2 μs
Low period of SCL tSCLCH 1.2 μs
High period of SCL tSCHCL 1—μs
Start condition setup time tSCHDL 420 — ns
Start condition hold time tSDLCL 630 — ns
Data hold time tSCLDX 420 — ns
Data setup time tSDVCH 630 — ns
SDA/SCL rise time tSRISE 250 ns
SDA/SCL fall time tSFALL —75ns
Stop condition setup time tSCHDH 420 — ns
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
48 Freescale Semiconductor
JTAG
11 JTAG
This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the
MPC8541E.
Table 38 provides the JTAG AC timing specifications as defined in Figure 32 through Figure 35.
Table 38. JTAG AC Timing Specifications (Independent of SYSCLK) 1
At recommended operating conditions (see Ta bl e 2 ).
Parameter Symbol 2Min Max Unit Notes
JTAG external clock frequency of operation fJTG 033.3MHz
JTAG external clock cycle time t JTG 30 ns —
JTAG external clock pulse width measured at 1.4 V tJTKHKL 15 ns —
JTAG external clock rise and fall times tJTGR & tJTGF 02ns
TRST assert time tTRST 25 ns 3
Input setup times:
Boundary-scan data
TMS, TDI
tJTDVKH
tJTIVKH
4
0
ns
4
Input hold times:
Boundary-scan data
TMS, TDI
tJTDXKH
tJTIXKH
20
25
ns
4
Valid times:
Boundary-scan data
TDO
tJTKLDV
tJTKLOV
4
4
20
25
ns
5
Output hold times:
Boundary-scan data
TDO
tJTKLDX
tJTKLOX
ns
5
JTAG external clock to output high impedance:
Boundary-scan data
TDO
tJTKLDZ
tJTKLOZ
3
3
19
9
ns
5, 6
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in
question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see
Figure 31). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH
symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the
tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to
the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that,
in general, the clock reference symbol representation is based on three letters representing the clock of a particular
functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to tTCLK.
5. Non-JTAG signal output timing with respect to tTCLK.
6. Guaranteed by design.
4* » —X7 In t 7—N_< x="" datap\|/jalid=""><>
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 49
JTAG
Figure 31 provides the AC test load for TDO and the boundary-scan outputs of the MPC8541E.
Figure 31. AC Test Load for the JTAG Interface
Figure 32 provides the JTAG clock input timing diagram.
Figure 32. JTAG Clock Input Timing Diagram
Figure 33 provides the TRST timing diagram.
Figure 33. TRST Timing Diagram
Figure 34 provides the boundary-scan timing diagram.
Figure 34. Boundary-Scan Timing Diagram
Output Z0 = 50 ΩOVDD/2
RL = 50 Ω
JTAG
tJTKHKL tJTGR
External Clock VMVMVM
tJTG tJTGF
VM = Midpoint Voltage (OVDD/2)
TRST
VM = Midpoint Voltage (OVDD/2)
VM VM
tTRST
VM = Midpoint Voltage (OVDD/2)
VM VM
tJTDVKH
tJTDXKH
Boundary
Data Outputs
Boundary
Data Outputs
JTAG
External Clock
Boundary
Data Inputs
Output Data Valid
tJTKLDX
tJTKLDZ
tJTKLDV
Input
Data Valid
Output Data Valid
W Inpul Dala Vahd ‘7: SR DD
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
50 Freescale Semiconductor
I2C
Figure 35 provides the test access port timing diagram.
Figure 35. Test Access Port Timing Diagram
12 I2C
This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8541E.
12.1 I2C DC Electrical Characteristics
Table 39 provides the DC electrical characteristics for the I2C interface of the MPC8541E.
Table 39. I2C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V ± 5%.
Parameter Symbol Min Max Unit Notes
Input high voltage level VIH 0.7 × OVDD OVDD+ 0.3 V
Input low voltage level VIL –0.3 0.3 × OVDD V—
Low level output voltage VOL 00.2 × OVDD V1
Output fall time from VIH(min) to VIL(max) with a bus
capacitance from 10 to 400 pF
tI2KLKV 20 + 0.1 × CB250 ns 2
Pulse width of spikes which must be suppressed by the
input filter
tI2KHKL 050ns3
Input current each I/O pin (input voltage is between 0.1 ×
OVDD and 0.9 × OVDD(max)
II–10 10 μA4
Capacitance for each I/O pin CI—10pF
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. CB = capacitance of one bus line in pF.
3. Refer to the
MPC8555E PowerQUICCIII Integrated Communications Processor Reference Manual
for information on the
digital filter used.
4. I/O pins obstruct the SDA and SCL lines if OVDD is switched off.
VM = Midpoint Voltage (OVDD/2)
VM VM
tJTIVKH
tJTIXKH
JTAG
External Clock
Output Data Valid
tJTKLOX
tJTKLOZ
tJTKLOV
Input
Data Valid
Output Data Valid
TDI, TMS
TDO
TDO
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 51
I2C
12.2 I2C AC Electrical Specifications
Table 40 provides the AC timing parameters for the I2C interface of the MPC8541E.
Table 40. I2C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Ta b le 39 ).
Parameter Symbol 1Min Max Unit
SCL clock frequency fI2C 0 400 kHz
Low period of the SCL clock tI2CL61.3 μs
High period of the SCL clock tI2CH60.6 μs
Setup time for a repeated START condition tI2SVKH60.6 μs
Hold time (repeated) START condition (after this period, the first clock
pulse is generated)
tI2SXKL60.6 μs
Data setup time tI2DVKH6100 — ns
Data hold time:
CBUS compatible masters
I2C bus devices
tI2DXKL
0 2
0.9 3
μs
Rise time of both SDA and SCL signals tI2CR 20 + 0.1 Cb 4300 ns
Fall time of both SDA and SCL signals tI2CF 20 + 0.1 Cb 4300 ns
Set-up time for STOP condition tI2PVKH 0.6 μs
Bus free time between a STOP and START condition tI2KHDX 1.3 μs
Noise margin at the LOW level for each connected device (including
hysteresis)
VNL 0.1 × OVDD —V
Noise margin at the HIGH level for each connected device (including
hysteresis)
VNH 0.2 × OVDD —V
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing
(I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the
high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the start
condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH
symbolizes I2C timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative
to the tI2C clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used
with the appropriate letter: R (rise) or F (fall).
2. MPC8541E provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
3. The maximum tI2DVKH has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.
4. CB = capacitance of one bus line in pF.
5. Guaranteed by design.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
52 Freescale Semiconductor
PCI
Figure 16 provides the AC test load for the I2C.
Figure 36. I2C AC Test Load
Figure 37 shows the AC timing diagram for the I2C bus.
Figure 37. I2C Bus AC Timing Diagram
13 PCI
This section describes the DC and AC electrical specifications for the PCI bus of the MPC8541E.
13.1 PCI DC Electrical Characteristics
Table 41 provides the DC electrical characteristics for the PCI interface of the MPC8541E.
Table 41. PCI DC Electrical Characteristics 1
Parameter Symbol Test Condition Min Max Unit
High-level input voltage VIH VOUT VOH (min) or 2 OVDD + 0.3 V
Low-level input voltage VIL VOUT VOL (max) 0.3 0.8 V
Input current IIN VIN 2 = 0 V or VIN = VDD —±5 μA
High-level output voltage VOH OVDD = min,
IOH = –100 μA
OVDD – 0.2 V
Low-level output voltage VOL OVDD = min,
IOL = 100 μA
—0.2V
Notes:
1. Ranges listed do not meet the full range of the DC specifications of the
PCI 2.2 Local Bus Specifications
.
2. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Ta b le 1 and Ta b le 2 .
Output Z0 = 50 ΩOVDD/2
RL = 50 Ω
SrS
SDA
SCL
tI2CF
tI2SXKL
tI2CL
tI2CH
tI2DXKL
tI2DVKH
tI2SXKL
tI2SVKH
tI2KHKL
tI2PVKH
tI2CR
tI2CF
PS
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 53
PCI
13.2 PCI AC Electrical Specifications
This section describes the general AC timing parameters of the PCI bus of the MPC8541E. Note that the
SYSCLK signal is used as the PCI input clock. Table 42 provides the PCI AC timing specifications at 66
MHz.
NOTE
PCI Clock can be PCI1_CLK or SYSCLK based on POR config input.
NOTE
The input setup time does not meet the PCI specification.
Figure 16 provides the AC test load for PCI.
Figure 38. PCI AC Test Load
Table 42. PCI AC Timing Specifications at 66 MHz
Parameter Symbol 1Min Max Unit Notes
Clock to output valid tPCKHOV 6.0 ns 2, 3
Output hold from Clock tPCKHOX 2.0 ns 2, 9
Clock to output high impedance tPCKHOZ 14 ns 2, 3, 10
Input setup to Clock tPCIVKH 3.3 ns 2, 4, 9
Input hold from Clock tPCIXKH 0 ns 2, 4, 9
REQ64 to HRESET 9 setup time tPCRVRH 10 × tSYS clocks 5, 6, 10
HRESET to REQ64 hold time tPCRHRX 050ns6, 10
HRESET high to first FRAME assertion tPCRHFV 10 clocks 7, 10
Notes:
1. Note that the symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH
symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the SYSCLK
clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to
the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the
PCI 2.2 Local Bus Specifications
.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
5. The timing parameter tSYS indicates the minimum and maximum CLK cycle times for the various specified frequencies. The
system clock period must be kept within the minimum and maximum defined ranges. For values see Section 15, “Clocking.”
6. The setup and hold time is with respect to the rising edge of HRESET
.
7. The timing parameter tPCRHFV is a minimum of 10 clocks rather than the minimum of 5 clocks in the
PCI 2.2 Local Bus
Specifications
.
8. The reset assertion timing requirement for HRESET is 100 μs.
9. Guaranteed by characterization.
10.Guaranteed by design.
Output Z0 = 50 ΩOVDD/2
RL = 50 Ω
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
54 Freescale Semiconductor
Package and Pin Listings
Figure 39 shows the PCI input AC timing conditions.
Figure 39. PCI Input AC Timing Measurement Conditions
Figure 40 shows the PCI output AC timing conditions.
Figure 40. PCI Output AC Timing Measurement Condition
14 Package and Pin Listings
This section details package parameters, pin assignments, and dimensions.
14.1 Package Parameters for the MPC8541E FC-PBGA
The package parameters are as provided in the following list. The package type is 29 mm × 29 mm, 783
flip chip plastic ball grid array (FC-PBGA).
Die size 8.7 mm × 9.3 mm × 0.75 mm
Package outline 29 mm × 29 mm
Interconnects 783
Pitch 1 mm
Minimum module height 3.07 mm
Maximum module height 3.75 mm
Solder Balls 62 Sn/36 Pb/2 Ag
Ball diameter (typical) 0.5 mm
tPCIVKH
CLK
Input
tPCIXKH
CLK
Output Delay
tPCKHOV
High-Impedance
tPCKHOZ
Output
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 55
Package and Pin Listings
14.2 Mechanical Dimensions of the FC-PBGA
Figure 41 the mechanical dimensions and bottom surface nomenclature of the MPC8541E 783 FC-PBGA
package.
Figure 41. Mechanical Dimensions and Bottom Surface Nomenclature of the FC-PBGA
Notes:
1. All dimensions are in millimeters.
2. Dimensions and tolerances per ASME Y14.5M-1994.
3. Maximum solder ball diameter measured parallel to datum A.
4. Datum A, the seating plane, is defined by the spherical crowns of the solder balls.
5. Capacitors may not be present on all devices.
6. Caution must be taken not to short capacitors or exposed metal capacitor pads on package top.
7. The socket lid must always be oriented to A1.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
56 Freescale Semiconductor
Package and Pin Listings
14.3 Pinout Listings
Table 43 provides the pin-out listing for the MPC8541E, 783 FC-PBGA package.
Table 43. MPC8541E Pinout Listing
Signal Package Pin Number Pin Type Power
Supply Notes
PCI1 and PCI2 (one 64-bit or two 32-bit)
PCI1_AD[63:32],
PCI2_AD[31:0]
AA14, AB14, AC14, AD14, AE14, AF14, AG14, AH14,
V15, W15, Y15, AA15, AB15, AC15, AD15, AG15,
AH15, V16, W16, AB16, AC16, AD16, AE16, AF16,
V17, W17, Y17, AA17, AB17, AE17, AF17, AF18
I/O OVDD 17
PCI1_AD[31:0] AH6, AD7, AE7, AH7, AB8, AC8, AF8, AG8, AD9,
AE9, AF9, AG9, AH9, W10, Y10, AA10, AE11, AF11,
AG11, AH11, V12, W12, Y12, AB12, AD12, AE12,
AG12, AH12, V13, Y13, AB13, AC13
I/O OVDD 17
PCI_C_BE64[7:4]
PCI2_C_BE[3:0]
AG13, AH13, V14, W14 I/O OVDD 17
PCI_C_BE64[3:0]
PCI1_C_BE[3:0]
AH8, AB10, AD11, AC12 I/O OVDD 17
PCI1_PAR AA11 I/O OVDD
PCI1_PAR64/PCI2_PAR Y14 I/O OVDD
PCI1_FRAME AC10 I/O OVDD 2
PCI1_TRDY AG10 I/O OVDD 2
PCI1_IRDY AD10 I/O OVDD 2
PCI1_STOP V11 I/O OVDD 2
PCI1_DEVSEL AH10 I/O OVDD 2
PCI1_IDSEL AA9 I OVDD
PCI1_REQ64/PCI2_FRAME AE13 I/O OVDD 5, 10
PCI1_ACK64/PCI2_DEVSEL AD13 I/O OVDD 2
PCI1_PERR W11 I/O OVDD 2
PCI1_SERR Y11 I/O OVDD 2, 4
PCI1_REQ[0] AF5 I/O OVDD
PCI1_REQ[1:4] AF3, AE4, AG4, AE5 I OVDD
PCI1_GNT[0] AE6 I/O OVDD
PCI1_GNT[1:4] AG5, AH5, AF6, AG6 O OVDD 5, 9
PCI1_CLK AH25 I OVDD
PCI2_CLK AH27 I OVDD
PCI2_GNT[0] AC18 I/O OVDD
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 57
Package and Pin Listings
PCI2_GNT[1:4] AD18, AE18, AE19, AD19 O OVDD 5, 9
PCI2_IDSEL AC22 I OVDD
PCI2_IRDY AD20 I/O OVDD 2
PCI2_PERR AC20 I/O OVDD 2
PCI2_REQ[0] AD21 I/O OVDD
PCI2_REQ[1:4] AE21, AD22, AE22, AC23 I OVDD
PCI2_SERR AE20 I/O OVDD 2,4
PCI2_STOP AC21 I/O OVDD 2
PCI2_TRDY AC19 I/O OVDD 2
DDR SDRAM Memory Interface
MDQ[0:63] M26, L27, L22, K24, M24, M23, K27, K26, K22, J28,
F26, E27, J26, J23, H26, G26, C26, E25, C24, E23,
D26, C25, A24, D23, B23, F22, J21, G21, G22, D22,
H21, E21, N18, J18, D18, L17, M18, L18, C18, A18,
K17, K16, C16, B16, G17, L16, A16, L15, G15, E15,
C14, K13, C15, D15, E14, D14, D13, E13, D12, A11,
F13, H13, A13, B12
I/O GVDD
MECC[0:7] N20, M20, L19, E19, C21, A21, G19, A19 I/O GVDD
MDM[0:8] L24, H28, F24, L21, E18, E16, G14, B13, M19 O GVDD
MDQS[0:8] L26, J25, D25, A22, H18, F16, F14, C13, C20 I/O GVDD
MBA[0:1] B18, B19 O GVDD
MA[0:14] N19, B21, F21, K21, M21, C23, A23, B24, H23, G24,
K19, B25, D27, J14, J13
OGV
DD
MWE D17 O GVDD
MRAS F17 O GVDD
MCAS J16 O GVDD
MCS[0:3] H16, G16, J15, H15 O GVDD
MCKE[0:1] E26, E28 O GVDD 11
MCK[0:5] J20, H25, A15, D20, F28, K14 O GVDD
MCK[0:5] F20, G27, B15, E20, F27, L14 O GVDD
MSYNC_IN M28 I GVDD 22
MSYNC_OUT N28 O GVDD 22
Local Bus Controller Interface
LA[27] U18 O OVDD 5, 9
Table 43. MPC8541E Pinout Listing (continued)
Signal Package Pin Number Pin Type Power
Supply Notes
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
58 Freescale Semiconductor
Package and Pin Listings
LA[28:31] T18, T19, T20, T21 O OVDD 5, 7, 9
LAD[0:31] AD26, AD27, AD28, AC26, AC27, AC28, AA22,
AA23, AA26, Y21, Y22, Y26, W20, W22, W26, V19,
T22, R24, R23, R22, R21, R18, P26, P25, P20, P19,
P18, N22, N23, N24, N25, N26
I/O OVDD
LALE V21 O OVDD 5, 8, 9
LBCTL V20 O OVDD 9
LCKE U23 O OVDD
LCLK[0:2] U27, U28, V18 O OVDD
LCS[0:4] Y27, Y28, W27, W28, R27 O OVDD
LCS5/DMA_DREQ2 R28 I/O OVDD 1
LCS6/DMA_DACK2 P27 O OVDD 1
LCS7/DMA_DDONE2 P28 O OVDD 1
LDP[0:3] AA27, AA28, T26, P21 I/O OVDD
LGPL0/LSDA10 U19 O OVDD 5, 9
LGPL1/LSDWE U22 O OVDD 5, 9
LGPL2/LOE/LSDRAS V28 O OVDD 5, 8, 9
LGPL3/LSDCAS V27 O OVDD 5, 9
LGPL4/LGTA/LUPWAIT/
LPBSE
V23 I/O OVDD 21
LGPL5 V22 O OVDD 5, 9
LSYNC_IN T27 I OVDD
LSYNC_OUT T28 O OVDD
LWE[0:1]/LSDDQM[0:1]/
LBS[0:1]
AB28, AB27 O OVDD 1, 5, 9
LWE[2:3]/LSDDQM[2:3]/
LBS[2:3]
T23, P24 O OVDD 1, 5, 9
DMA
DMA_DREQ[0:1] H5, G4 I OVDD
DMA_DACK[0:1] H6, G5 O OVDD
DMA_DDONE[0:1] H7, G6 O OVDD
Programmable Interrupt Controller
MCP AG17 I OVDD
UDE AG16 I OVDD
Table 43. MPC8541E Pinout Listing (continued)
Signal Package Pin Number Pin Type Power
Supply Notes
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 59
Package and Pin Listings
IRQ[0:7] AA18, Y18, AB18, AG24, AA21, Y19, AA19, AG25 I OVDD
IRQ8 AB20 I OVDD 9
IRQ9/DMA_DREQ3 Y20 I OVDD 1
IRQ10/DMA_DACK3 AF26 I/O OVDD 1
IRQ11/DMA_DDONE3 AH24 I/O OVDD 1
IRQ_OUT AB21 O OVDD 2, 4
Ethernet Management Interface
EC_MDC F1 O OVDD 5, 9
EC_MDIO E1 I/O OVDD
Gigabit Reference Clock
EC_GTX_CLK125 E2 I LVDD
Three-Speed Ethernet Controller (Gigabit Ethernet 1)
TSEC1_TXD[7:4] A6, F7, D7, C7 O LVDD
TSEC1_TXD[3:0] B7, A7, G8, E8 O LVDD 9, 18
TSEC1_TX_EN C8 O LVDD 11
TSEC1_TX_ER B8 O LVDD
TSEC1_TX_CLK C6 I LVDD
TSEC1_GTX_CLK B6 O LVDD
TSEC1_CRS C3 I LVDD
TSEC1_COL G7 I LVDD
TSEC1_RXD[7:0] D4, B4, D3, D5, B5, A5, F6, E6 I LVDD
TSEC1_RX_DV D2 I LVDD
TSEC1_RX_ER E5 I LVDD
TSEC1_RX_CLK D6 I LVDD
Three-Speed Ethernet Controller (Gigabit Ethernet 2)
TSEC2_TXD[7:4] B10, A10, J10, K11 O LVDD
TSEC2_TXD[3:0] J11, H11, G11, E11 O LVDD 5, 9, 18
TSEC2_TX_EN B11 O LVDD 11
TSEC2_TX_ER D11 O LVDD
TSEC2_TX_CLK D10 I LVDD
TSEC2_GTX_CLK C10 O LVDD
Table 43. MPC8541E Pinout Listing (continued)
Signal Package Pin Number Pin Type Power
Supply Notes
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
60 Freescale Semiconductor
Package and Pin Listings
TSEC2_CRS D9 I LVDD
TSEC2_COL F8 I LVDD
TSEC2_RXD[7:0] F9, E9, C9, B9, A9, H9, G10, F10 I LVDD
TSEC2_RX_DV H8 I LVDD
TSEC2_RX_ER A8 I LVDD
TSEC2_RX_CLK E10 I LVDD
DUART
UART_CTS[0,1] Y2, Y3 I OVDD
UART_RTS[0,1] Y1, AD1 O OVDD
UART_SIN[0,1] P11, AD5 I OVDD
UART_SOUT[0,1] N6, AD2 O OVDD
I2C interface
IIC_SDA AH22 I/O OVDD 4, 19
IIC_SCL AH23 I/O OVDD 4, 19
System Control
HRESET AH16 I OVDD
HRESET_REQ AG20 O OVDD 18
SRESET AF20 I OVDD
CKSTP_IN M11 I OVDD
CKSTP_OUT G1 O OVDD 2, 4
Debug
TRIG_IN N12 I OVDD
TRIG_OUT/READY G2 O OVDD 6, 9, 18
MSRCID[0:1] J9, G3 O OVDD 5, 6, 9
MSRCID[2:3] F3, F5 O OVDD 6
MSRCID4 F2 O OVDD 6
MDVAL F4 O OVDD 6
Clock
SYSCLK AH21 I OVDD
RTC AB23 I OVDD
CLK_OUT AF22 O OVDD
Table 43. MPC8541E Pinout Listing (continued)
Signal Package Pin Number Pin Type Power
Supply Notes
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 61
Package and Pin Listings
JTAG
TCK AF21 I OVDD
TDI AG21 I OVDD 12
TDO AF19 O OVDD 11
TMS AF23 I OVDD 12
TRST AG23 I OVDD 12
DFT
LSSD_MODE AG19 I OVDD 20
L1_TSTCLK AB22 I OVDD 20
L2_TSTCLK AG22 I OVDD 20
TEST_SEL0 AH20 I OVDD 3
TEST_SEL1 AG26 I OVDD 3
Thermal Management
THERM0 AG2 — 14
THERM1 AH3 — 14
Power Management
ASLEEP AG18 9, 18
Power and Ground Signals
AVDD1 AH19 Power for e500
PLL (1.2 V)
AVDD1—
AVDD2 AH18 Power for CCB
PLL (1.2 V)
AVDD2—
AVDD3 AH17 Power for CPM
PLL (1.2 V)
AVDD3—
AVDD4 AF28 Power for PCI1
PLL (1.2 V)
AVDD4—
AVDD5 AE28 Power for PCI2
PLL (1.2 V)
AVDD5—
Table 43. MPC8541E Pinout Listing (continued)
Signal Package Pin Number Pin Type Power
Supply Notes
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
62 Freescale Semiconductor
Package and Pin Listings
GND A12, A17, B3, B14, B20, B26, B27, C2, C4, C11,C17,
C19, C22, C27, D8, E3, E12, E24, F11, F18, F23, G9,
G12, G25, H4, H12, H14, H17, H20, H22, H27, J19,
J24, K5, K9, K18, K23, K28, L6, L20, L25, M4, M12,
M14, M16, M22, M27, N2, N13, N15, N17, P12, P14,
P16, P23, R13, R15, R17, R20, R26, T3, T8, T10,
T12, T14, T16, U6, U13, U15, U16, U17, U21, V7,
V10, V26, W5, W18, W23, Y8, Y16, AA6, AA13, AB4,
AB11, AB19, AC6, AC9, AD3, AD8, AD17, AF2, AF4,
AF10, AF13, AF15, AF27, AG3, AG7
——
GVDD A14, A20, A25, A26, A27, A28, B17, B22, B28, C12,
C28, D16, D19, D21, D24, D28, E17, E22, F12, F15,
F19, F25, G13, G18, G20, G23, G28, H19, H24, J12,
J17, J22, J27, K15, K20, K25, L13, L23, L28, M25,
N21
Power for DDR
DRAM I/O
Voltage
(2.5 V)
GVDD
LV DD A4, C5, E7, H10 Reference
Voltage;
Three-Speed
Ethernet I/O
(2.5 V, 3.3 V)
LVDD
MVREF N27 Reference
Voltage Signal;
DDR
MVREF
No Connects AA24, AA25, AA3, AA4, AA7 AA8, AB24, AB25,
AC24, AC25, AD23, AD24, AD25, AE23, AE24,
AE25, AE26, AE27, AF24, AF25, H1, H2, J1, J2, J3,
J4, J5, J6, M1, N1, N10, N11, N4, N5, N7, N8, N9,
P10, P8, P9, R10, R11, T24, T25, U24, U25, V24,
V25, W24, W25, W9, Y24, Y25, Y5, Y6, Y9, AH26,
AH28, AG28, AH1, AG1, AH2, B1, B2, A2, A3
——16
OVDD D1, E4, H3, K4, K10, L7, M5, N3, P22, R19, R25, T2,
T7, U5, U20, U26, V8, W4, W13, W19, W21, Y7, Y23,
AA5, AA12, AA16, AA20, AB7, AB9, AB26, AC5,
AC11, AC17, AD4, AE1, AE8, AE10, AE15, AF7,
AF12, AG27, AH4
PCI, 10/100
Ethernet, and
other Standard
(3.3 V)
OVDD
RESERVED C1, T11, U11, AF1 15
SENSEVDD L12 Power for Core
(1.2 V)
VDD 13
SENSEVSS K12 — 13
VDD M13, M15, M17, N14, N16, P13, P15, P17, R12, R14,
R16, T13, T15, T17, U12, U14
Power for Core
(1.2 V)
VDD
CPM
PA[8:31] J7, J8, K8, K7, K6, K3, K2, K1, L1, L2, L3, L4, L5, L8,
L9, L10, L11, M10, M9, M8, M7, M6, M3, M2
I/0 OVDD
Table 43. MPC8541E Pinout Listing (continued)
Signal Package Pin Number Pin Type Power
Supply Notes
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 63
Package and Pin Listings
PB[18:31] P7, P6, P5, P4, P3, P2, P1, R1, R2, R3, R4, R5, R6,
R7
I/0 OVDD
PC[0, 1, 4–29] R8, R9, T9, T6, T5, T4, T1, U1, U2, U3, U4, U7, U8,
U9, U10, V9, V6, V5, V4, V3, V2, V1, W1, W2, W3,
W6, W7, W8
I/0 OVDD
PD[7, 14–25, 29–31] Y4, AA2, AA1, AB1, AB2, AB3, AB5, AB6, AC7, AC4,
AC3, AC2, AC1, AD6, AE3, AE2
I/0 OVDD
Notes:
1. All multiplexed signals are listed only once and do not re-occur. For example, LCS5/DMA_REQ2 is listed only once in the
Local Bus Controller Interface section, and is not mentioned in the DMA section even though the pin also functions as
DMA_REQ2.
2. Recommend a weak pull-up resistor (2–10 kΩ) be placed on this pin to OVDD
.
3. This pin must always be pulled down to GND.
4. This pin is an open drain signal.
5. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the MPC8541E is in
the reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ pull-down resistor. If an
external device connected to this pin might pull it down during reset, then a pull-up or active driver is needed if the signal is
intended to be high during reset.
6. Treat these pins as no connects (NC) unless using debug address functionality.
7. The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-kΩ pull-up or
pull-down resistors. See Section 15.2, “Platform/System PLL Ratio.”
8. The value of LALE and LGPL2 at reset set the e500 core clock to CCB Clock PLL ratio. These pins require 4.7-kΩ pull-up
or pull-down resistors. See the Section 15.3, “e500 Core PLL Ratio.”
9. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or
because it has other manufacturing test functions. This pin therefore is described as an I/O for boundary scan.
10. This pin functionally requires a pull-up resistor, but during reset it is a configuration input that controls 32- vs. 64-bit PCI
operation. Therefore, it must be actively driven low during reset by reset logic if the device is to be configured to be a 64-bit
PCI device. Refer to the
PCI Specification
.
11. This output is actively driven during reset rather than being three-stated during reset.
12. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
13. These pins are connected to the VDD/GND planes internally and may be used by the core power supply to improve tracking
and regulation.
14. Internal thermally sensitive resistor.
15. No connections should be made to these pins.
16. These pins are not connected for any functional use.
17. PCI specifications recommend that a weak pull-up resistor (2–10 kΩ) be placed on the higher order pins to OVDD when
using 64-bit buffer mode (pins PCI_AD[63:32] and PCI2_C_BE[7:4]).
18. If this pin is connected to a device that pulls down during reset, an external pull-up is required to that is strong enough to
pull this signal to a logic 1 during reset.
19. Recommend a pull-up resistor (~1 kΩ) be placed on this pin to OVDD.
20. These are test signals for factory use only and must be pulled up (100Ω το 1kΩ) to OVDD for normal machine operation.
21. If this signal is used as both an input and an output, a weak pull-up (~10kΩ) is required on this pin.
22. MSYNC_IN and MSYNC_OUT should be connected together for proper operation.
Table 43. MPC8541E Pinout Listing (continued)
Signal Package Pin Number Pin Type Power
Supply Notes
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
64 Freescale Semiconductor
Clocking
15 Clocking
This section describes the PLL configuration of the MPC8541E. Note that the platform clock is identical
to the CCB clock.
15.1 Clock Ranges
Table 44 provides the clocking specifications for the processor core and Table 44 provides the clocking
specifications for the memory bus.
Table 44. Processor Core Clocking Specifications
Characteristic
Maximum Processor Core Frequency
Unit Notes533 MHz 600 MHz 667 MHz 833 MHz 1000 MHz
Min Max Min Max Min Max Min Max Min Max
e500 core
processor
frequency
400 533 400 600 400 667 400 833 400 1000 MHz 1, 2, 3
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to Section 15.2, “Platform/System PLL Ratio,” and Section 15.3, “e500 Core PLL Ratio,” for ratio settings.
2.)The minimum e500 core frequency is based on the minimum platform frequency of 200 MHz.
3. 1000 MHz frequency supports only a 1.3 V core.
Table 45. Memory Bus Clocking Specifications
Characteristic
Maximum Processor Core
Frequency
Unit Notes
533, 600, 667, 883, 1000 MHz
Min Max
Memory bus frequency 100 166 MHz 1, 2, 3
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that
the resulting SYSCLK frequency, e500 (core) frequency, and CCB frequency do not exceed their
respective maximum or minimum operating frequencies. Refer to Section 15.2, “Platform/System PLL
Ratio,” and Section 15.3, “e500 Core PLL Ratio, for ratio settings.
2. The memory bus speed is half of the DDR data rate, hence, half of the platform clock frequency.
3. 1000 MHz frequency supports only a 1.3 V core.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 65
Clocking
15.2 Platform/System PLL Ratio
The platform clock is the clock that drives the L2 cache, the DDR SDRAM data rate, and the e500 core
complex bus (CCB), and is also called the CCB clock. The values are determined by the binary value on
LA[28:31] at power up, as shown in Table 46.
There is no default for this PLL ratio; these signals must be pulled to the desired values.
For specifications on the PCI_CLK, refer to the PCI 2.2 Specification.
Table 46. CCB Clock Ratio
Binary Value of
LA[28:31] Signals Ratio Description
0000 16:1 ratio CCB clock: SYSCLK (PCI bus)
0001 Reserved
0010 2:1 ratio CCB clock: SYSCLK (PCI bus)
0011 3:1 ratio CCB clock: SYSCLK (PCI bus)
0100 4:1 ratio CCB clock: SYSCLK (PCI bus)
0101 5:1 ratio CCB clock: SYSCLK (PCI bus)
0110 6:1 ratio CCB clock: SYSCLK (PCI bus)
0111 Reserved
1000 8:1 ratio CCB clock: SYSCLK (PCI bus)
1001 9:1 ratio CCB clock: SYSCLK (PCI bus)
1010 10:1 ratio CCB clock: SYSCLK (PCI bus)
1011 Reserved
1100 12:1 ratio CCB clock: SYSCLK (PCI bus)
1101 Reserved
1110 Reserved
1111 Reserved
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
66 Freescale Semiconductor
Clocking
15.3 e500 Core PLL Ratio
Table 47 describes the clock ratio between the e500 core complex bus (CCB) and the e500 core clock. This
ratio is determined by the binary value of LALE and LGPL2 at power up, as shown in Table 47.
15.4 Frequency Options
Table 48 shows the expected frequency values for the platform frequency when using a CCB to SYSCLK
ratio in comparison to the memory bus speed.
Table 47. e500 Core to CCB Ratio
Binary Value of LALE, LGPL2 Signals Ratio Description
00 2:1 e500 core:CCB
01 5:2 e500 core:CCB
10 3:1 e500 core:CCB
11 7:2 e500 core:CCB
Table 48. Frequency Options with Respect to Memory Bus Speeds
CCB to SYSCLK
Ratio SYSCLK (MHz)
17 25 33 42 67 83 100 111 133
Platform/CCB Frequency (MHz)
2200 222 267
3200 250 300 333
4267 333
5208 333
6200 250
8200 267 333
9225 300
10 250 333
12 200 300
16 267
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 67
Thermal
16 Thermal
This section describes the thermal specifications of the MPC8541E.
16.1 Thermal Characteristics
Table 49 provides the package thermal characteristics for the MPC8541E.
16.2 Thermal Management Information
This section provides thermal management information for the flip chip plastic ball grid array (FC-PBGA)
package for air-cooled applications. Proper thermal control design is primarily dependent on the
system-level design—the heat sink, airflow, and thermal interface material. The recommended attachment
method to the heat sink is illustrated in Figure 42. The heat sink should be attached to the printed-circuit
board with the spring force centered over the die. This spring force should not exceed 10 pounds force.
Table 49. Package Thermal Characteristics
Characteristic Symbol Value Unit Notes
Junction-to-ambient Natural Convection on four layer board (2s2p) RθJMA 17 °C/W 1, 2
Junction-to-ambient (@200 ft/min or 1.0 m/s) on four layer board (2s2p) RθJMA 14 °C/W 1, 2
Junction-to-ambient (@400 ft/min or 2.0 m/s) on four layer board (2s2p) RθJMA 13 °C/W 1, 2
Junction-to-board thermal RθJB 10 °C/W 3
Junction-to-case thermal RθJC 0.96 °C/W 4
Notes
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance
2. Per JEDEC JESD51–6 with the board horizontal.
3. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1). Cold plate temperature is used for case temperature; measured value includes the thermal resistance of the
interface layer.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
68 Freescale Semiconductor
Thermal
Figure 42. Package Exploded Cross-Sectional View with Several Heat Sink Options
The system board designer can choose between several types of heat sinks to place on the MPC8541E.
There are several commercially-available heat sinks from the following vendors:
Aavid Thermalloy 603-224-9988
80 Commercial St.
Concord, NH 03301
Internet: www.aavidthermalloy.com
Alpha Novatech 408-749-7601
473 Sapena Ct. #15
Santa Clara, CA 95054
Internet: www.alphanovatech.com
International Electronic Research Corporation (IERC) 818-842-7277
413 North Moss St.
Burbank, CA 91502
Internet: www.ctscorp.com
Millennium Electronics (MEI) 408-436-8770
Loroco Sites
671 East Brokaw Road
San Jose, CA 95112
Internet: www.mei-millennium.com
Tyco Electronics 800-522-6752
Chip Coolers™
P.O. Box 3668
Harrisburg, PA 17105-3668
Internet: www.chipcoolers.com
Wakefield Engineering 603-635-5102
33 Bridge St.
Pelham, NH 03076
Internet: www.wakefield.com
Heat Sink
FC-PBGA Package
Heat Sink
Clip
Printed-Circuit Board
Die
Lid
Thermal Interface Material
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 69
Thermal
Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal
performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. Several
heat sinks offered by Aavid Thermalloy, Alpha Novatech, IERC, Chip Coolers, Millennium Electronics,
and Wakefield Engineering offer different heat sink-to-ambient thermal resistances, that allows the
MPC8541E to function in various environments.
16.2.1 Recommended Thermal Model
For system thermal modeling, the MPC8541E thermal model is shown in Figure 44. Five cuboids are used
to represent this device. To simplify the model, the solder balls and substrate are modeled as a single block
29x29x1.6 mm with the conductivity adjusted accordingly. The die is modeled as 8.7 x 9.3 mm at a
thickness of 0.75 mm. The bump/underfill layer is modeled as a collapsed resistance between the die and
substrate assuming a conductivity of 4.4 W/m•K in the thickness dimension of 0.07 mm. The lid attach
adhesive is also modeled as a collapsed resistance with dimensions of 8.7 x 9.3 x 0.05 mm and the
conductivity of 1.07 W/m•K. The nickel plated copper lid is modeled as 11 x 11 x 1 mm.
Figure 43. MPC8541E Thermal Model
Die
Lid
Substrate and solder balls
Heat Source
Substrate
Side View of Model (Not to Scale)
Top View of Model (Not to Scale)
x
y
z
Conductivity Value Unit
Lid
(11 × 11 × 1 mm)
kx360 W/(m × K)
ky360
kz360
Lid Adhesive—Collapsed resistance
(8.7 × 9.3 × 0.05 mm)
kz1.07
Die
(8.7 × 9.3 × 0.75 mm)
Bump/Underfill—Collapsed resistance
(8.7 × 9.3 × 0.07 mm)
kz4.4
Substrate and Solder Balls
(25 × 25 × 1.6 mm)
kx14.2
ky14.2
kz1.2
Adhesive
Bump/underfill
| R 4* E uh
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
70 Freescale Semiconductor
Thermal
16.2.2 Internal Package Conduction Resistance
For the packaging technology, shown in Table 49, the intrinsic internal conduction thermal resistance paths
are as follows:
The die junction-to-case thermal resistance
The die junction-to-board thermal resistance
Figure 44 depicts the primary heat transfer path for a package with an attached heat sink mounted to a
printed-circuit board.
Figure 44. Package with Heat Sink Mounted to a Printed-Circuit Board
The heat sink removes most of the heat from the device. Heat generated on the active side of the chip is
conducted through the silicon and through the lid, then through the heat sink attach material (or thermal
interface material), and finally to the heat sink. The junction-to-case thermal resistance is low enough that
the heat sink attach material and heat sink thermal resistance are the dominant terms.
16.2.3 Thermal Interface Materials
A thermal interface material is required at the package-to-heat sink interface to minimize the thermal
contact resistance. For those applications where the heat sink is attached by spring clip mechanism,
Figure 45 shows the thermal performance of three thin-sheet thermal-interface materials (silicone,
graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure.
As shown, the performance of these thermal interface materials improves with increasing contact pressure.
The use of thermal grease significantly reduces the interface thermal resistance. The bare joint results in a
thermal resistance approximately six times greater than the thermal grease joint.
Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see
Figure 41). Therefore, the synthetic grease offers the best thermal performance, especially at the low
interface pressure.
When removing the heat sink for re-work, it is preferable to slide the heat sink off slowly until the thermal
interface material loses its grip. If the support fixture around the package prevents sliding off the heat sink,
External Resistance
External Resistance
Internal Resistance
Radiation Convection
Radiation Convection
Heat Sink
Printed-Circuit Board
Thermal Interface Material
Package/Leads
Die Junction
Die/Package
(Note the internal versus external package resistance)
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 71
Thermal
the heat sink should be slowly removed. Heating the heat sink to 40–50°C with an air gun can soften the
interface material and make the removal easier. The use of an adhesive for heat sink attach is not
recommended.
Figure 45. Thermal Performance of Select Thermal Interface Materials
The system board designer can choose between several types of thermal interface. There are several
commercially-available thermal interfaces provided by the following vendors:
Chomerics, Inc. 781-935-4850
77 Dragon Ct.
Woburn, MA 01888-4014
Internet: www.chomerics.com
Dow-Corning Corporation 800-248-2481
Dow-Corning Electronic Materials
2200 W. Salzburg Rd.
Midland, MI 48686-0997
Internet: www.dowcorning.com
Shin-Etsu MicroSi, Inc. 888-642-7674
10028 S. 51st St.
Phoenix, AZ 85044
Internet: www.microsi.com
The Bergquist Company 800-347-4572
18930 West 78th St.
0
0.5
1
1.5
2
0 1020304050607080
Silicone Sheet (0.006 in.)
Bare Joint
Floroether Oil Sheet (0.007 in.)
Graphite/Oil Sheet (0.005 in.)
Synthetic Grease
Contact Pressure (psi)
Specific Thermal Resistance (K-in.2/W)
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
72 Freescale Semiconductor
Thermal
Chanhassen, MN 55317
Internet: www.bergquistcompany.com
Thermagon Inc. 888-246-9050
4707 Detroit Ave.
Cleveland, OH 44102
Internet: www.thermagon.com
16.2.4 Heat Sink Selection Examples
The following section provides a heat sink selection example using one of the commercially available heat
sinks.
16.2.4.1 Case 1
For preliminary heat sink sizing, the die-junction temperature can be expressed as follows:
TJ = TI + TR + (θJC + θINT + θSA)×PD
where
TJ is the die-junction temperature
TI is the inlet cabinet ambient temperature
TR is the air temperature rise within the computer cabinet
θJC is the junction-to-case thermal resistance
θINT is the adhesive or interface material thermal resistance
θSA is the heat sink base-to-ambient thermal resistance
PD is the power dissipated by the device. See Table 4 and Table 5.
During operation the die-junction temperatures (TJ) should be maintained within the range specified in
Table 2. The temperature of air cooling the component greatly depends on the ambient inlet air temperature
and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (TA)
may range from 30° to 40°C. The air temperature rise within a cabinet (TR) may be in the range of 5° to
10°C. The thermal resistance of some thermal interface material (θINT) may be about 1°C/W. For the
purposes of this example, the θJC value given in Table 49 that includes the thermal grease interface and is
documented in note 4 is used. If a thermal pad is used, θINT must be added.
Assuming a TI of 30°C, a TR of 5°C, a FC-PBGA package θJC = 0.96, and a power consumption (PD) of
8.0 W, the following expression for TJ is obtained:
Die-junction temperature: TJ = 30°C + 5°C + (0.96°C/W + θSA)×8.0 W
The heat sink-to-ambient thermal resistance (θSA) versus airflow velocity for a Thermalloy heat sink
#2328B is shown in Figure 46.
Assuming an air velocity of 2 m/s, we have an effective θSA+ of about 3.3°C/W, thus
TJ = 30°C + 5°C + (0.96°C/W + 3.3°C/W) ×8.0 W,
resulting in a die-junction temperature of approximately 69°C which is well within the maximum
operating temperature of the component.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 73
Thermal
Figure 46. Thermalloy #2328B Heat Sink-to-Ambient Thermal Resistance Versus Airflow Velocity
16.2.4.2 Case 2
Every system application has different conditions that the thermal management solution must solve. As an
alternate example, assume that the air reaching the component is 85 °C with an approach velocity of 1
m/sec. For a maximum junction temperature of 105 °C at 8 W, the total thermal resistance of junction to
case thermal resistance plus thermal interface material plus heat sink thermal resistance must be less than
2.5 °C/W. The value of the junction to case thermal resistance in Table 49 includes the thermal interface
resistance of a thin layer of thermal grease as documented in footnote 4 of the table. Assuming that the
heat sink is flat enough to allow a thin layer of grease or phase change material, then the heat sink must be
less than 1.5 °C/W.
Millennium Electronics (MEI) has tooled a heat sink MTHERM-1051 for this requirement assuming a
compactPCI environment at 1 m/sec and a heat sink height of 12 mm. The MEI solution is illustrated in
Figure 47 and Figure 48. This design has several significant advantages:
The heat sink is clipped to a plastic frame attached to the application board with screws or plastic
inserts at the corners away from the primary signal routing areas.
The heat sink clip is designed to apply the force holding the heat sink in place directly above the
die at a maximum force of less than 10 lbs.
For applications with significant vibration requirements, silicone damping material can be applied
between the heat sink and plastic frame.
1
3
5
7
8
00.511.522.533.5
Thermalloy #2328B Pin-fin Heat Sink
Approach Air Velocity (m/s)
Heat Sink Thermal Resistance (°C/W)
(25 ×28 ×15 mm)
2
4
6
Frame Footprint on PCB 78.02 11.10I 7+; ’4 // /// '9' 1035 ? / / f / / / I / fi 96.5u 533le 1 4,5 5 HatchedAIeame j AboveBoald 5 / / 4 ¢ ///// ///// /4> 91m IC Package Lid analinn &Aimnw Direction lc Package Lid (nal Package) Must be Cenlered ____ Relative to Heatsink lFrame Airflow Direction Mus1 Be Parallel lo IIIuslrallve source provlded by Heelsink Fins Millennium Electronics (MEI)
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
74 Freescale Semiconductor
Thermal
The spring mounting should be designed to apply the force only directly above the die. By localizing the
force, rocking of the heat sink is minimized. One suggested mounting method attaches a plastic fence to
the board to provide the structure on which the heat sink spring clips. The plastic fence also provides the
opportunity to minimize the holes in the printed-circuit board and to locate them at the corners of the
package. Figure 47 and provide exploded views of the plastic fence, heat sink, and spring clip.
Figure 47. Exploded Views (1) of a Heat Sink Attachment using a Plastic Fence
Item No QTY MEI PM Description 1 1 MFRAMEQDOO HEATSINK FRAME 2 1 MSNK»1120 EXTRUDED HEATSINK 3 1 MCLIP»1013 CLIP 4 4 MPPINS-1000 FRAME ATTACHMENT PINS Illustrative source provided by Millennium Electronics (MEI)
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 75
Thermal
Figure 48. Exploded Views (2) of a Heat Sink Attachment using a Plastic Force
The die junction-to-ambient and the heat sink-to-ambient thermal resistances are common figure-of-merits
used for comparing the thermal performance of various microelectronic packaging technologies, one
should exercise caution when only using this metric in determining thermal management because no single
parameter can adequately describe three-dimensional heat flow. The final die-junction operating
temperature is not only a function of the component-level thermal resistance, but the system level design
and its operating conditions. In addition to the components power consumption, a number of factors affect
the final operating die-junction temperature: airflow, board population (local heat flux of adjacent
components), system air temperature rise, altitude, etc.
Due to the complexity and the many variations of system-level boundary conditions for today’s
microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation convection
and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models
for the boards, as well as, system-level designs.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
76 Freescale Semiconductor
System Design Information
17 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8541E.
17.1 System Clocking
The MPC8541E includes five PLLs.
1. The platform PLL (AVDD1) generates the platform clock from the externally supplied SYSCLK
input. The frequency ratio between the platform and SYSCLK is selected using the platform PLL
ratio configuration bits as described in Section 15.2, “Platform/System PLL Ratio.”
2. The e500 Core PLL (AVDD2) generates the core clock as a slave to the platform clock. The
frequency ratio between the e500 core clock and the platform clock is selected using the e500
PLL ratio configuration bits as described in Section 15.3, “e500 Core PLL Ratio.”
3. The CPM PLL (AVDD3) is slaved to the platform clock and is used to generate clocks used
internally by the CPM block. The ratio between the CPM PLL and the platform clock is fixed and
not under user control.
4. The PCI1 PLL (AVDD4) generates the clocking for the first PCI bus.
5. The PCI2 PLL (AVDD5) generates the clock for the second PCI bus.
17.2 PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins (AVDD1,
AV DD2, AVDD3, AVDD4, and AVDD5 respectively). The AVDD level should always be equivalent to VDD,
and preferably these voltages are derived directly from VDD through a low frequency filter scheme such
as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide five independent filter circuits as illustrated in Figure 49, one to each of the five AVDD pins. By
providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD
pin, which is on the periphery of the 783 FC-PBGA footprint, without the inductance of vias.
0S1
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 77
System Design Information
Figure 49 shows the PLL power supply filter circuit.
Figure 49. PLL Power Supply Filter Circuit
17.3 Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the MPC8541E can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8541E system, and the
MPC8541E itself requires a clean, tightly regulated source of power. Therefore, it is recommended that
the system designer place at least one decoupling capacitor at each VDD, OVDD, GVDD, and LVDD pins
of the MPC8541E. These decoupling capacitors should receive their power from separate VDD, OVDD,
GVDD, LVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance.
Capacitors may be placed directly under the device using a standard escape pattern. Others may surround
the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the VDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip
capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the
quick response time necessary. They should also be connected to the power and ground planes through two
vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum or Sanyo
OSCON).
17.4 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to OVDD, GVDD, or LVDD as required. Unused active high
inputs should be connected to GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, GVDD, LVDD, OVDD, and GND pins of
the MPC8541E.
17.5 Output Buffer DC Impedance
The MPC8541E drivers are characterized over process, voltage, and temperature. For all buses, the driver
is a push-pull single-ended driver type (open drain for I2C).
To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD
or GND. Then, the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 50). The
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
VDD AVDD (or L2AVDD)
2.2 µF 2.2 µF
GND Low ESL Surface Mount Capacitors
10 Ω
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
78 Freescale Semiconductor
System Design Information
When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals
OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each
other in value. Then, Z0 = (RP + RN)/2.
Figure 50. Driver Impedance Measurement
The value of this resistance and the strength of the drivers current source can be found by making two
measurements. First, the output voltage is measured while driving logic 1 without an external differential
termination resistor. The measured voltage is V1 = Rsource × Isource. Second, the output voltage is measured
while driving logic 1 with an external precision differential termination resistor of value Rterm. The
measured voltage is V2= 1/(1/R1+1/R
2)) × Isource. Solving for the output impedance gives Rsource = Rterm
× (V1/V2– 1). The drive current is then Isource =V
1/Rsource.
Table 50 summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD,
nominal OVDD, 105°C.
Table 50. Impedance Characteristics
Impedance Local Bus, Ethernet, DUART, Control, Configuration, Power
Management PCI DDR DRAM Symbol Unit
RN43 Target 25 Target 20 Target Z0Ω
RP43 Target 25 Target 20 Target Z0Ω
Differential NA NA NA ZDIFF Ω
Note: Nominal supply voltages. See Ta b le 1 , Tj = 105°C.
OVDD
OGND
RP
RN
Pad
Data
SW1
SW2
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 79
System Design Information
17.6 Configuration Pin Multiplexing
The MPC8541E provides the user with power-on configuration options which can be set through the use
of external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible
configuration pins). These pins are generally used as output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins
while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled
and the I/O circuit takes on its normal function. Most of these sampled configuration pins are equipped
with an on-chip gated resistor of approximately 20 kΩ. This value should permit the 4.7-kΩ resistor to pull
the configuration pin to a valid logic low level. The pull-up resistor is enabled only during HRESET (and
for platform/system clocks after HRESET deassertion to ensure capture of the reset value). When the input
receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with
minimal signal quality or delay disruption. The default value for all configuration bits treated this way has
been encoded such that a high voltage level puts the device into the default state and external resistors are
needed only when non-default settings are required by the user.
Careful board layout with stubless connections to these pull-down resistors coupled with the large value
of the pull-down resistor should minimize the disruption of signal quality or speed for output pins thus
configured.
The platform PLL ratio and e500 PLL ratio configuration pins are not equipped with these default pull-up
devices.
17.7 Pull-Up Resistor Requirements
The MPC8541E requires high resistance pull-up resistors (10 kΩ is recommended) on open drain type
pins.
Correct operation of the JTAG interface requires configuration of a group of system control pins as
demonstrated in Figure 52. Care must be taken to ensure that these pins are maintained at a valid deasserted
state under normal operating conditions as most have asynchronous behavior and spurious assertion give
unpredictable results.
TSEC1_TXD[3:0] must not be pulled low during reset. Some PHY chips have internal pulldowns that
could cause this to happen. If such PHY chips are used, then a pullup must be placed on these signals strong
enough to restore these signals to a logical 1 during reset.
Refer to the PCI 2.2 specification for all pull-ups required for PCI.
17.8 JTAG Configuration Signals
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 specification, but is provided on all processors that implement the Power Architecture. The
device requires TRST to be asserted during reset conditions to ensure the JTAG boundary logic does not
interfere with normal chip operation. While it is possible to force the TAP controller to the reset state using
only the TCK and TMS signals, generally systems assert TRST during the power-on reset flow. Simply
tying TRST to HRESET is not practical because the JTAG interface is also used for accessing the common
on-chip processor (COP) function.
SUBBED E Emmmmmmm
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
80 Freescale Semiconductor
System Design Information
The COP function of these processors allow a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
interface connects primarily through the JTAG port of the processor, with some additional status
monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order
to fully control the processor. If the target system has independent reset sources, such as voltage monitors,
watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be
merged into these signals with logic.
The arrangement shown in Figure 51 allows the COP port to independently assert HRESET or TRST,
while ensuring that the target can drive HRESET as well.
The COP interface has a standard header, shown in Figure 51, for connection to the target system, and is
based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The
connector typically has pin 14 removed as a connector key.
The COP header adds many benefits such as breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features. An inexpensive option can be to leave
the COP header unpopulated until needed.
There is no standardized way to number the COP header; consequently, many different pin numbers have
been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while others
use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as
with an IC). Regardless of the numbering, the signal placement recommended in Figure 51 is common to
all known emulators.
Figure 51. COP Connector Physical Pinout
3
13
9
5
1
6
10
15
11
7
16
12
8
4
KEY
No pin
12
COP_TDO
COP_TDI
NC
NC
COP_TRST
COP_VDD_SENSE
COP_CHKSTP_IN
NC
NC
GND
COP_TCK
COP_TMS
COP_SRESET
COP_HRESET
COP_CHKSTP_OUT
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 81
System Design Information
17.8.1 Termination of Unused Signals
If the JTAG interface and COP header are not used, Freescale recommends the following connections:
•TRST
should be tied to HRESET through a 0 kΩ isolation resistor so that it is asserted when the
system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during
the power-on reset flow. Freescale recommends that the COP header be designed into the system
as shown in Figure 52. If this is not possible, the isolation resistor allows future access to TRST in
case a JTAG interface may need to be wired onto the system in future debug situations.
Tie TCK to OVDD through a 10 kΩ resistor. This prevents TCK from changing state and reading
incorrect data into the device.
No connection is required for TDI, TMS, or TDO.
1 k5! $1 CO CO —> DDDDDD _H_ DDDDDDDD .1 f:
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
82 Freescale Semiconductor
System Design Information
Figure 52. JTAG Interface Connection
HRESET
From Target
Board Sources
COP_HRESET
13
COP_SRESET
SRESET
NC
11
COP_VDD_SENSE2
6
5
15
10 Ω
10 kΩ
10 kΩ
COP_CHKSTP_IN CKSTP_IN
8
COP_TMS
COP_TDO
COP_TDI
COP_TCK
TMS
TDO
TDI
9
1
3
4COP_TRST
7
16
2
10
12
(if any)
COP Header
14 3
Notes:
3. The KEY location (pin 14) is not physically present on the COP header.
10 kΩ
TRST1
10 kΩ
10 kΩ
10 kΩ
CKSTP_OUT
COP_CHKSTP_OUT
3
13
9
5
1
6
10
15
11
7
16
12
8
4
KEY
No pin
COP Connector
Physical Pinout
1
2
NC
SRESET
2. Populate this with a 10 Ω resistor for short-circuit/current-limiting protection.
NC
OVDD
10 kΩ
10 kΩHRESET1
in order to fully control the processor as shown here.
4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for
1. The COP port and target board should be able to independently assert HRESET and TRST to the processor
improved signal integrity.
TCK
4
5
5.
This switch is included as a precaution for BSDL testing. The switch should be open during BSDL testing to avoid
accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed or removed.
10 kΩ
6
6.
Asserting SRESET causes a machine check interrupt to the e500 core.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 83
Document Revision History
18 Document Revision History
Table 51 provides a revision history for this hardware specification.
Table 51. Document Revision History
Rev. No. Date Substantive Change(s)
4.2 1/2008 Added “Note: Rise/Fall Time on CPM Input Pins” and following note text to Section 10.2, “CPM AC
Timing Specifications.”
4.1 07/2007 Inserted Figure 3, ““Maximum AC Waveforms on PCI interface for 3.3-V Signaling.
4 12/2006 Updated Section 2.1.2, “Power Sequencing.
Updated back page information.
3.2 11/2006 Updated Section 2.1.2, “Power Sequencing.
Replaced Section 17.8, “JTAG Configuration Signals.
3.1 10/2005 Ta bl e 4 : Added footnote 2 about junction temperature.
Ta b le 4 : Added max. power values for 1000 MHz core frequency.
Removed Figure 3, “Maximum AC Waveforms on PCI Interface for 3.3-V Signaling.
Ta b le 3 0 : Modified note to tLBKSKEW from 8 to 9
Ta b le 3 0 : Changed tLBKHOZ1 and tLBKHOV2 values.
Ta b le 3 0 : Added note 3 to tLBKHOV1.
Ta b le 3 0 and Ta b le 3 1 : Modified note 3.
Ta b le 3 1 : Added note 3 to tLBKLOV1.
Ta b le 3 1 : Modified values for tLBKHKT
, tLBKLOV1, tLBKLOV2, tLBKLOV3, tLBKLOZ1, and tLBKLOZ2.
Figure 21: Changed Input Signals: LAD[0:31]/LDP[0:3].
Ta b le 4 3 : Modified note for signal CLK_OUT.
Ta b le 4 3 : PCI1_CLK and PCI2_CLK changed from I/O to I.
Ta b le 5 2 : Added column for Encryption Acceleration.
3 8/29/2005 Ta bl e 4 : Modified max. power values.
Ta b le 4 3 : Modified notes for signals TSEC1_TXD[3:0], TSEC2_TXD[3:0], TRIG_OUT/READY,
MSRCID4, and MDVAL.
2 8/2005 Previous revision’s history listed incorrect cross references. Table 2 is now correctly listed as
Ta b le 2 7 and Table 31 is now listed as Table 31.
Ta b le 7 : Added note 2.
Ta b le 1 4 : Modified min and max values for tDDKHMP
1 6/2005 Ta bl e 2 7 : Changed LVdd to OVdd for the supply voltage Ethernet management interface.
Ta b le 4 : Modified footnote 4 and changed typical power for the 1000MHz core frequency.
Ta b le 3 1 : Corrected symbols for body rows 9–15, effectively changing them from a high state to a
low state.
0 6/2005 Initial Release.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
84 Freescale Semiconductor
Device Nomenclature
19 Device Nomenclature
Ordering information for the parts fully covered by this specification document is provided in
Section 19.1, “Nomenclature of Parts Fully Addressed by this Document.”
19.1 Nomenclature of Parts Fully Addressed by this Document
Table 52 provides the Freescale part numbering nomenclature for the MPC8541E. Note that the individual
part numbers correspond to a maximum processor core frequency. For available frequencies, contact your
local Freescale sales office. In addition to the processor frequency, the part numbering scheme also
includes an application modifier which may specify special application conditions. Each part number also
contains a revision code which refers to the die mask revision number.
Table 52. Part Numbering Nomenclature
MPC
nnnn tpp aa a r
Product
Code
Part
Identifier
Encryption
Acceleration
Temperature
Range1Package 2Processor
Frequency 3
Platform
Frequency
Revision
Level4
MPC 8541 Blank = not
included
E = included
Blank = 0 to 105°C
C = –40 to 105°C
PX = FC-PBGA
VT = FC-PBGA
(lead free)
AJ = 533 MHz
AK = 600 MHz
AL = 667 MHz
AP = 833 MHz
AQ = 1000 MHZ
D = 266 MHz
E = 300 MHz
F = 333 MHz
Notes:
1. For Temperature Range=C, Processor Frequency is limited to 667 MHz with a Platform Frequency selector of 333 MHz,
Processor Frequency is limited to 533 MHz with a Platform Frequency selector of 266 MHz.
2. See Section 14, “Package and Pin Listings,” for more information on available package types.
3. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this
specification support all core frequencies. Additionally, parts addressed by Part Number Specifications may support other
maximum core frequencies.
4. Contact you local Freescale field applications engineer (FAE).
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor 85
Device Nomenclature
19.2 Part Marking
Parts are marked as the example shown in Figure 53.
Figure 53. Part Marking for FC-PBGA Device
MPC85nn
xPXxxxn
MMMMM
ATWLYYWWA
Notes:
CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States.
MMMMM is the 5-digit mask number.
ATWLYYWWA is the traceability code.
CCCCC
FC-PBGA
MPCnnnn
MMMMM
ATWLYYWWA
85xx
Notes:
CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States.
MMMMM is the 5-digit mask number.
ATWLYYWWA is the traceability code.
CCCCC
tppaaar
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
86 Freescale Sem