TVP7002EVM User Guide Datasheet by Texas Instruments

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TEXAS INSTRUMENTS
TVP7002EVM
User's Guide
Literature Number: SLEU098
May 2008
2 SLEU098 – May 2008
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Contents
1 Introduction ............................................................................................................... 7
1.1 Functional Description....................................................................................................... 7
1.2 Overview ...................................................................................................................... 7
1.3 Board-Level Description .................................................................................................... 8
1.3.1 Analog Inputs ........................................................................................................ 8
1.3.2 External Reference Clock and External Clock Input ........................................................... 8
1.3.3 Test Points and Jumpers .......................................................................................... 9
1.3.4 Common Board Interface .......................................................................................... 9
1.3.5 Component Analog Outputs ....................................................................................... 9
1.4 System Level Description ................................................................................................. 10
2 Hardware and Software Setup .................................................................................... 11
2.1 Required Hardware and Equipment ..................................................................................... 11
2.2 Hardware Setup ............................................................................................................ 11
2.3 Software Installation ....................................................................................................... 12
3 WinVCC4 Quick Start ................................................................................................ 13
4 WinVCC4 in Depth .................................................................................................... 15
4.1 Starting WinVCC4 .......................................................................................................... 15
4.2 WinVCC4 Configuration Dialog Box ..................................................................................... 15
4.3 I
2
C System Test ............................................................................................................ 17
4.4 Main Menu .................................................................................................................. 18
4.4.1 System Initialization ............................................................................................... 18
4.4.2 Register Editing .................................................................................................... 22
4.5 TVP7002 Property Sheets ................................................................................................ 25
4.5.1 Input Mux ........................................................................................................... 25
4.5.2 Clamp ............................................................................................................... 26
4.5.3 PLL .................................................................................................................. 28
4.5.4 Gain and Offset - ALC ............................................................................................ 30
4.5.5 Output ............................................................................................................... 31
4.5.6 Status ............................................................................................................... 32
5 Troubleshooting ....................................................................................................... 35
5.1 Troubleshooting Guide .................................................................................................... 35
5.2 Corrective Action Dialogs ................................................................................................. 37
5.2.1 Setting the PC Parallel Port Mode .............................................................................. 38
5.2.2 General I
2
C Error Report ......................................................................................... 38
6 TVP7002EVM Schematics .......................................................................................... 39
A Recommended PLL Settings ...................................................................................... 53
B Embedded Sync Setups ............................................................................................ 55
C Color Space Converter Coefficients ............................................................................ 57
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D Macrovision™ Support .............................................................................................. 59
Contents 4 SLEU098 – May 2008
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List of Figures
1-1 TVP7002EVM Block Diagram .............................................................................................. 8
1-2 TVP7002EVM System Level Block Diagram ........................................................................... 10
3-1 WinVCC4 – I
2
C Configuration Screen ................................................................................... 13
3-2 WinVCC4 – Main Screen .................................................................................................. 14
3-3 WinVCC4 – System Initialization ......................................................................................... 14
4-1 WinVCC4 Multiple Occurrences Error Message ....................................................................... 15
4-2 WinVCC4 I
2
C Address Configuration .................................................................................... 16
4-3 I
2
C System Failure ......................................................................................................... 17
4-4 WinVCC4 – Main Screen .................................................................................................. 18
4-5 System Initialization ........................................................................................................ 19
4-6 TVP7002 Register Map .................................................................................................... 23
4-7 THS8200 Register Map ................................................................................................... 23
4-8 Generic I
2
C Register Editor ............................................................................................... 24
4-9 Input Mux Property Sheet ................................................................................................. 25
4-10 Clamp and ALC Placement ............................................................................................... 26
4-11 Clamp Control Property Sheet ............................................................................................ 28
4-12 PLL Property Sheet ........................................................................................................ 29
4-13 Gain and Offset Property Sheet .......................................................................................... 30
4-14 Output Property Sheet ..................................................................................................... 31
4-15 Status Property Sheet ..................................................................................................... 33
5-1 I
2
C System Failure Dialog Box ........................................................................................... 36
5-2 Corrective Action Dialog Box ............................................................................................. 37
5-3 Corrective Action Required ............................................................................................... 37
5-4 Corrective Action Required ............................................................................................... 37
5-5 I
2
C Error Report ............................................................................................................ 38
B-1 720p60 Example, Total Line Length = 1650 Pixels .................................................................... 55
SLEU098 – May 2008 List of Figures 5
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List of Tables
1-1 Analog Inputs and Pin Terminals .......................................................................................... 8
1-2 I
2
C Address Selection Jumper (I2C ADDR) .............................................................................. 9
1-3 Power Down Mode Selection Jumper (PWDN) .......................................................................... 9
4-1 Main Menu Summary ...................................................................................................... 18
4-2 Register Map Editor Controls ............................................................................................. 24
4-3 Recommended SOG LPF Settings ...................................................................................... 26
4-4 Typical Clamp Setup for RGB Graphics ................................................................................. 27
4-5 Recommended Clamp LPF Settings ..................................................................................... 28
4-6 Recommended Coast Settings ........................................................................................... 30
4-7 Recommended ALC Settings ............................................................................................. 31
4-8 Use of Property Sheet Controls .......................................................................................... 34
4-9 Property Sheet Button Controls .......................................................................................... 34
5-1 TVP7002EVM Troubleshooting........................................................................................... 35
5-2 I
2
C Troubleshooting ........................................................................................................ 36
A-1 Recommended PLL Settings ............................................................................................. 53
B-1 Embedded Sync Setups ................................................................................................... 55
D-1 Recommended Reg 34h Macrovsion Stripper Width Settings (MAC_EN = 1) ..................................... 59
6List of Tables SLEU098 – May 2008
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1.1 Functional Description
1.2 Overview
Chapter 1SLEU098 – May 2008
Introduction
The TVP7002EVM is composed of the TVP7002 board and the THS8200 board when they are connectedtogether. Both boards share a common interface via a 120-pin connector. This interface provides all data,clocks, I
2
C communication, and 5-V power to each board.
The THS8200 is a Texas Instruments triple digital-to-analog converter (DAC) providing component analogRGB or YPbPr outputs. The THS8200 supports resolutions up to UXGA for PC graphics and up to 1080pfor video. This triple DAC minimizes artifacts commonly associated with backend processing. Its purposeis only to convert the digital data from the TVP7002 triple analog-to-digital converter (ADC) back toanalog. Use of a TV or display capable of supporting both component RGB and YPbPr analog inputs isrecommended.
The TVP7002EVM is powered by a single 5-V universal supply. I
2
C communication is emulated using aPC parallel port configured for the extended capability port (ECP) or bidirectional mode. The parallel portmode can be changed using the PC BIOS setup, available during the reboot process.
The TVP7002 triple ADC converts three channels of analog video input into digital component data. Thisdigital data and the associated clocks from the TVP7002 are sent to the THS8200.
Control of the TVP7002EVM is provided by WinVCC4, a Windows™-based application developed byTexas Instruments and provided free of charge. This application uses the parallel port to provide I
2
Ccommunication to the TVP7002EVM. WinVCC4 provides a graphics user interface (GUI) and a registerlevel interface to program and vary the controls available within the TVP7002 triple ADC and theTHS8200.
Macrovision is a trademark of Macrovision Corporation.Windows is a trademark of Microsoft Corporation.All other trademarks are the property of their respective owners.
SLEU098 – May 2008 Introduction 7
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1.3 Board-Level Description
LED
Test Points
THS8200
R/Pr
B/Pb
G/Y
DB15
120-Pin Header Connector
120-Pin Header Connector
Test Points
DB15
VSYNC
HSYNC
G/Y
R/Pr
B/Pb
TVP7002
EXT
CLK
PWDN
Reset I2C
ADDR
LED
5 V
1.3.1 Analog Inputs
1.3.2 External Reference Clock and External Clock Input
Board-Level Description
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The following sections describe the various features available on the TVP7002EVM. Figure 1-1 shows theTVP7002EVM block diagram.
Figure 1-1. TVP7002EVM Block Diagram
The TVP7002EVM uses all the available inputs on the TVP7002 triple ADC. The following inputs areavailable for use:
•Five BNC connectors (Y/G, Pb/B, Pr/R, HSYNC, and VSYNC)
•One DB15 graphics connector (Y/G, Pb/B, Pr/R, HSYNC, and VSYNC)
Table 1-1 shows the pins used for the inputs described above.
Table 1-1. Analog Inputs and Pin Terminals
Input Type TVP7002 Pins
5-BNC RIN_1, GIN_1, BIN_1, VSYNC_B, HSYNC_B
DB15 RIN_3, GIN_3, BIN_3, VSYNC_A, HSYNC_A
Note: Both the TVP7002 and THS8200 EVMs include PCB footprints for passive (LC) anti-aliasand reconstruction filters. Due to the wide variety of formats that are supported, both boardsare shipped from the factory with these filters bypassed and unpopulated.
The EVM is shipped with a 27-MHz crystal oscillator that can be used as a stable reference clock(REFCLK) for input format detection. The REFCLK output is connected to pin 80 of the TVP7002 and isused by the TVP7002 to report line length and HSYNC width status for input detection (see Section 4.5.6for more detail).
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1.3.3 Test Points and Jumpers
1.3.4 Common Board Interface
1.3.5 Component Analog Outputs
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Board-Level Description
An SMA connector (EXTCLK) for use with an external ADC sample clock is also provided. This input isend-terminated with a 50- Ωresistor for use with a lab clock generator and can be routed to pin 80(EXTCLK) of the TVP7002 with a slight jumper configuration change. An external ADC sample clock canbe used by setting the PCLK SEL bit in I
2
C register 1Ah to 0. Removal of the termination resistor may berequired for some clock sources incapable of driving the 50- Ωload.
Note: The EVM is shipped from the factory with the 27-MHz oscillator connected to pin 80 of theTVP7002. To use the EXTCLK, the 0- Ωresistor installed at J3 can be moved from the OSCposition to the EXT position.
Various test points are available on the TVP7002EVM. This includes DCLK (DATACLK), HS (HSOUT), VS(VSOUT), DE_FID, SOG_OUT, SDA, SCL, power, and GND. Each test point is clearly labeled on theTVP7002EVM silkscreen. The primary test-point headers for the TVP7002 are H2, H3, and H4, whichprovide access to the red, green, and blue data, respectively.
There are two jumpers on the TVP7002 board that configure the power-down mode and I
2
C addressselect. Each jumper is set by default in its preferred state for the TVP7002EVM. Near each jumper on theTVP7002 board is a silkscreen that describes the two states of the jumper configuration.
Table 1-2. I
2
C Address Selection Jumper (I2C ADDR)
I2C ADDR Jumper I
2
C Address
1 - 2 0xB8
2 - 3 0xBA
Table 1-3. Power Down Mode Selection Jumper(PWDN)
PWDN Jumper Operation
1 - 2 Normal operation
2 - 3 Power down
Note: If the I
2
C address is changed on either the TVP7002 board or the THS8200 board while theTVP7002EVM is powered up, then that device does not recognize the new I
2
C address. Thereset button on the TVP7002EVM must be pressed, and WinVCC4 must be reconfigured forthe new I
2
C address.
The TVP7002EVM uses a 120-pin connector to connect the TVP7002 board (P3) to the THS8200 board(P2). This interface shares all common signals including the I
2
C and the 5-V supply. This modularizes theTVP7002 board and allows users to interface it to a variety of other Texas Instruments products includingDVI transmitters, video encoders, or to any other platform that shares the same interface.
This connector shares all digital video data (R[9:0], G[9:0], and B[9:0]), all video clocks (DCLK_OUT,VSYNC, and HSYNC), RESET, I
2
C, and 5 V as mentioned above.
The THS8200 board provides component analog outputs to a display RGB or YPbPr formats. Theconfiguration settings for the TVP7002EVM use the RGB color space for PC graphics and the YPbPr colorspace for video (480i to 1080p).
SLEU098 – May 2008 Introduction 9
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1.4 System Level Description
Y/G
Pb/B
Pr/R
HS
VS
DVI
5-V
Supply
Display
Monitor
PC
(I C
Control)
2
Quantum
Video/Graphic
Source
TVP7002EVM
System Level Description
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The system block diagram in Figure 1-2 gives an example of how the TVP7002EVM may be used forevaluation. Typically, an RGB or YPbPr component analog input is provided by a graphics/video sourcesuch as a pattern generator or a DVD player.
The TVP7002EVM is configured with the provided 5-V supply and the parallel port cable. The output isprovided by the THS8200 triple DAC to convert the digital data from the TVP7002 back to analog. Thisanalog output is then fed into a display monitor.
Figure 1-2. TVP7002EVM System Level Block Diagram
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2.1 Required Hardware and Equipment
2.2 Hardware Setup
Chapter 2SLEU098 – May 2008
Hardware and Software Setup
The required hardware and equipment necessary to use the TVP7002EVM are:
•TVP7002EVM (provided)
•Universal 5-V power supply (provided)
•Parallel cable (provided)
•Windows-based PC
•One cable with five BNC connectors (RGB, HS, VS)
•One cable with three BNC connectors (RGB or YPbPr)
•Two DB15 PC cables
•Video source (multiformat video/graphics signal generator or DVD player)
•Display monitor that supports PC graphics and video up to 1080p
Perform the following steps to set up the hardware for the TVP7002EVM:
1. Connect the TVP7002 board and the THS8200 board using the 120-pin board connector. The twoboards connected together are called the TVP7002EVM.
2. Connect a video or graphics source to the DB15 input connector or the RGB, HSYNC, and VSYNCinput connectors of the TVP7002 EVM. The HSYNC and VSYNC input connections are not required ifcomponent video sources with sync-on-y are used.
3. Depending on the desired output format, connect either a graphics DB15 cable or video BNC cable tothe output of the THS8200 board.
4. Connect the parallel port cable from the TVP7002EVM to the PC.
Note: There are footprints for a dc jack on the THS8200 board, but the default power is providedby the TVP7002 board via the 120-pin connector, P3.
5. Connect the 5-V power supply to the dc jack on the TVP7002 board. A green LED on each boardshould light.
SLEU098 – May 2008 Hardware and Software Setup 11
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2.3 Software Installation
Software Installation
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WinVCC4 is a Windows application that uses the PC parallel port to emulate I
2
C, providing access to eachdevice on the I
2
C bus. WinVCC4 makes use of CMD files, a text editable file that allows preset videosetups to be programmed easily.
This feature allows the user to easily set multiple I
2
C registers with the press of a button. WinVCC4 alsohas property sheets for the TVP7002, which allows the user to control the I
2
C registers with a graphicaluser interface (GUI).
All necessary software for the TVP7002EVM is provided on the enclosed CD. Perform the following stepsto install WinVCC4:
1. Explore the provided TVP7002EVM software CD.
2. Run Port95NT.exe to install the parallel port driver used by WinVCC4.
This driver must be installed, and the PC must be rebooted before WinVCC4 can operate correctly.
3. Run Setup.exe to install WinVCC4.
Click Next at all prompts and click Finish to complete the installation process. No reboot is required.
4. Run WinVCC4.exe
Note: A shortcut to WinVCC4 should now be available on the desktop. Another shortcut toWinVCC4 and additional TVP7002 related documentation can be found atStart>Programs>TVP7002EVM Software.
12 Hardware and Software Setup SLEU098 – May 2008
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Chapter 3SLEU098 – May 2008
WinVCC4 Quick Start
Perform the following steps to enable video output from the TVP7002EVM.
1. Run WinVCC4. When the WinVCC4 Configuration screen appears, use it to configure the I
2
C bus.
2. Next to TVP7002, select the TVP7002 and ensure the I
2
C address is set to 0xB8. The addressselected here must match the address selected by the I2C ADDR jumper on the TVP7002 board.
3. Next to THS8200, select the THS8200 and ensure the I
2
C address is set to 0x40. The addressselected here must match the address selected by the I2C ADDR jumper on the THS8200 board.
Note: If WinVCC4 is running and the TVP7002 or THS8200 board I
2
C address is changed, thenpower must be cycled on the EVM to enable the EVM to use the new address.
Figure 3-1. WinVCC4 – I
2
C Configuration Screen
4. Ensure that all other boxes are selected as "Not Used" and that all program options buttons are set toENABLE. Click OK.
5. If there are no I
2
C communication problems, then the Main Screen window displays next. If there areI
2
C problems, then an I
2
C Test Report box displays. Completely exit out of WinVCC4, double-checkthe parallel port cable connections, cycle power on the TVP7002EVM, and run WinVCC4 again.
SLEU098 – May 2008 WinVCC4 Quick Start 13
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6. Load the provided TVP7002EVM.CMD file into WinVCC4 by clicking onTools>System Initialization>Browse. The default directory is c:\Program Files\TexasInstruments\TVP7002EVM\Initialization.
Figure 3-2. WinVCC4 – Main Screen
7. Click the desired "TVP7002 + THS8200_..." dataset in the window, and then click the Program Datasetbutton to initialize the TVP7002EVM.
Figure 3-3. WinVCC4 – System Initialization
8. With a graphics/video source provided at the BNC or DB15 connectors and with the proper resolutionconfigured, video or graphics should be viewable on the display monitor.
Note: To ensure that the TVP7002 is working properly, go to Status and check the HSYNC andVSYNC detection status. If using the YPbPr inputs with sync-on-y, then the SOG statusshould indicate "DETECTED", and the HSYNC and VSYNC input status should indicate"FROM SOG" and "FROM SYNC SEP", respectively.
14 WinVCC4 Quick Start SLEU098 – May 2008
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4.1 Starting WinVCC4
4.2 WinVCC4 Configuration Dialog Box
Chapter 4SLEU098 – May 2008
WinVCC4 in Depth
This chapter describes in depth how to use WinVCC4. The various features and screens that the usermay encounter while evaluating the TVP7002EVM are described.
The Port95NT parallel port driver must be installed before using WinVCC4. WinVCC4 may be started byclicking on Start>All Programs>TVP7002EVM Software>WinVCC4.
If the dialog box shown in Figure 4-1 is displayed, one of two things is indicated:
1. WinVCC4 did not run to completion the last time it ran. In this case, click OK to exit the program andrestart WinVCC4.
2. There is more than one instance of WinVCC4 running at the same time. In this case:
a. Click OK to exit the program.b. Press CTRL-ALT-DELETE to open the Task Manager.c. Select and click End Task for all occurrences of WinVCC4 or WinVCC4 CONFIGURATION.d. Restart WinVCC4.
Figure 4-1. WinVCC4 Multiple Occurrences Error Message
The WinVCC4 Configuration dialog box (see Figure 4-2 ) should now be visible. This dialog box configuresthe I
2
C bus on the TVP7002EVM. All settings from this dialog box are stored in the Windows registry andare restored the next time the program is started. After initial installation, TVP7000 Video and GraphicsDigitizer drop down box is set to TVP7002.
The I
2
C slave address for each device must match the I
2
C slave address selected by jumpers on theTVP7002EVM. These jumpers are set by the factory to use 0xB8 for the TVP7002 and 0x40 for theTHS8200 transmitter.
It is also important to ensure that only the TVP7002 is selected when using the TVP7002EVM. AllProgram Options must be enabled. Disabling these options is required only if debugging a problem withthe I
2
C bus.
Click OK to begin I
2
C communication with the selected devices.
SLEU098 – May 2008 WinVCC4 in Depth 15
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WinVCC4 Configuration Dialog Box
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Figure 4-2. WinVCC4 I
2
C Address Configuration
WinVCC4 in Depth16 SLEU098 – May 2008
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4.3 I
2
C System Test
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I
2
C System Test
The I
2
C system test of selected registers runs immediately after closing the WinVCC4 Configuration dialogbox by clicking OK (unless the I
2
C system test program options button was disabled).
If the I
2
C system test passes, then only a PASS message appears. If the test failed, then a dialog boxappears (see Figure 4-3 ). See Chapter 5 for details on how to resolve this issue.
The I
2
C system test can be run at anytime by clicking Run System I
2
C Test in the Tools menu.
Figure 4-3. I
2
C System Failure
SLEU098 – May 2008 WinVCC4 in Depth 17
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Tms INSTRUMENTS Windwws Video Control Center (W
4.4 Main Menu
4.4.1 System Initialization
Main Menu
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After configuring the I
2
C, the main menu is displayed as shown in Figure 4-4 . The menus that are used tooperate WinVCC4 are File, Edit, Tools, Window, and Help. The File menu's only function is Exit, whichterminates the program. Table 4-1 summarizes the main menu contents.
Figure 4-4. WinVCC4 – Main Screen
Table 4-1. Main Menu Summary
Menu Contents
File Exit
Edit Register Map
TVP7002PNP
Generic I
2
C Editor
Property Sheets
TVP7002PNP
Tools System Initialization
Real-time Polling
TV Tuner Control (FQ12xx series only)
Multiple-Byte I
2
C Transfers
Set I
2
C Bit Rate
Run System I
2
C Test
Run Continuous I
2
C Test
Read VBI FIFO
Capture Live VBI Data
Window Allows selection of the active window. Multiple windows can be open at the same time.
Help Displays program version
Click System Initialization in the Tools menu to display the dialog box shown in Figure 4-5 . This dialog boxprovides the means for initializing the TVP7002 triple ADC and/or THS8200 for a particular video mode.The details of the initialization are contained in the command file (with a CMD file extension).
The command file is loaded using the Browse …button. Once the command file is opened, a text listdisplays descriptions of the individual datasets contained within the command file.
Click once on the desired dataset description to select it. Click the Program Device(s) Using SelectedDataset button to run the selected dataset, which loads the devices via the I
2
C bus. When the deviceinitialization has completed, the status indicator displays Ready.
Note: If Ready does not display, then the devices are not initialized and the I
2
C bus is notcommunicating. See Chapter 5 for possible solutions.
Click the OK button to close the dialog box. Each time the System Initialization dialog box is closed, theinitialization file pathname and the dataset selection number are saved in the Windows registry to allowthese settings to be retained for the next time WinVCC4 runs.
18 WinVCC4 in Depth SLEU098 – May 2008
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4.4.1.1 Adding a Custom Dataset
4.4.1.2 Command Files
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Main Menu
Figure 4-5. System Initialization
After programming the EVM via the System Initialization tool using the factory-supplied command filethrough the Property Sheets tool, the device register settings can be customized. Perform the followingsteps to save the custom settings:
1. Reopen the System Initialization dialog box via the Tools menu.
2. Click the Append Current Device Settings to Command File button. A dialog box requesting adescription of the new dataset appears.
3. Optionally, click the dropdown box and select one of the existing descriptions.
4. Modify the description text or type a description.
5. Click OK. All nondefault register values from the TVP7002 and THS8200 are appended to the currentcommand file as an additional dataset.
Select the custom dataset and send it by pressing the Program …button.
Note: The command file (.CMD) must be saved as plain text.
The command file is a text file that can be generated using any common editor; however, it must be savedas plain text. Command files are especially useful for quickly switching between the various systemconfigurations. These .CMD files are unrelated to the typical Windows .CMD files.
A default command file has been provided on the CD. This command file contains most of the desiredsetups. This command file is located at:
c:\Program Files\Texas Instruments\TVP7002EVM\Initialization\TVP7002EVM.cmd
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4.4.1.3 Example Command File
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A command file can contain up to 250 datasets. A dataset is a set of register settings to initialize theTVP7002 triple ADC and/or THS8200 for a particular video mode. Each dataset includes a description thatis displayed in one row of the dataset descriptions list. The register settings may be located in thecommand file itself and/or may be stored in separate include file(s) (with an .INC file extension) and beincluded into the command file using the INCLUDE statement.
The following is an example of one dataset within a command file.
////////////////////////////////////////////////////////////////////////////////
BEGIN_DATASET //
DATASET_NAME,"TVP7002+THS8200_720p-60Hz- 45khz - 74.25Mhz"
//TVP7002
WR_REG,TVP7000,0x01,0x01,0x67 // PLL DIVMSB 1650
WR_REG,TVP7000,0x01,0x02,0x20 // PLL DIVLSB
WR_REG,TVP7000,0x01,0x03,0xA0 // VCO2_CP3_RR_CP_R
WR_REG,TVP7000,0x01,0x04,0x80 // PHASE SEL(5) CKDI CKDI DIV2
WR_REG,TVP7000,0x01,0x05,0x32 // CLAMP START
WR_REG,TVP7000,0x01,0x06,0x20 // CLAMP WIDTH
WR_REG,TVP7000,0x01,0x07,0x28 // HSYNC OUTPUT WIDTH - 40
WR_REG,TVP7000,0x01,0x08,0x3C // Blue Fine Gain
WR_REG,TVP7000,0x01,0x09,0x3C // Green Fine Gain
WR_REG,TVP7000,0x01,0x0A,0x3C // Red Fine Gain
WR_REG,TVP7000,0x01,0x0B,0x80 // Blue Fine Offset
WR_REG,TVP7000,0x01,0x0C,0x80 // Green Fine Offset
WR_REG,TVP7000,0x01,0x0D,0x80 // Red Fine Offset
WR_REG,TVP7000,0x01,0x0E,0x24 // SYNC CONTROL HSout+ VSout+
WR_REG,TVP7000,0x01,0x0F,0x2E // PLL and CLAMP CONTROL
WR_REG,TVP7000,0x01,0x10,0x5D // SOG Threshold-(YPbPr Clamp)
WR_REG,TVP7000,0x01,0x11,0x40 // SYNC SEPERATOR THRESHOLD
WR_REG,TVP7000,0x01,0x12,0x01 // PRE_COAST
WR_REG,TVP7000,0x01,0x13,0x00 // POST_COAST
WR_REG,TVP7000,0x01,0x15,0x04 // Output Formatter
WR_REG,TVP7000,0x01,0x17,0x00 // MISC Control 2 FID out, Enable Outputs
WR_REG,TVP7000,0x01,0x18,0x01 // MISC Control 3 Clock polarity
WR_REG,TVP7000,0x01,0x19,0x00 // INPUT MUX SELECT CH1 selected (BNC )
WR_REG,TVP7000,0x01,0x1A,0xC7 // INPUT MUX SELECT2,SOG/Clamp filter, HSYNC_B and
VSYNC_B
WR_REG,TVP7000,0x01,0x1B,0x77 // Default Blue and Green coarse analog gain
WR_REG,TVP7000,0x01,0x1C,0x07 // Default Red coarse analog gain
WR_REG,TVP7000,0x01,0x21,0x35 // HSOUT START (13+40)
WR_REG,TVP7000,0x01,0x22,0x00 // MACEN=0
WR_REG,TVP7000,0x01,0x26,0x80 // ALC Enable
WR_REG,TVP7000,0x01,0x28,0x53 // Default ALC FILTER Control
WR_REG,TVP7000,0x01,0x2A,0x87 // CM Offset, Enable FINE CLAMP CONTROL
WR_REG,TVP7000,0x01,0x2B,0x00 // POWER CONTROL-SOG ON
WR_REG,TVP7000,0x01,0x2C,0x50 // ADC Setup
WR_REG,TVP7000,0x01,0x2D,0x00 // Coarse Clamp OFF
WR_REG,TVP7000,0x01,0x2E,0x80 // SOG Clamp ON
WR_REG,TVP7000,0x01,0x31,0x5A // ALC PLACEMENT
WR_REG,TVP7000,0x01,0x34,0x07 // Macrovision Stripper Width
WR_REG,TVP7000,0x01,0x35,0x00 // VSout Align
WR_REG,TVP7000,0x01,0x36,0x00 // Sync Bypass
WR_REG,TVP7000,0x01,0x3D,0x06 // Line Length Tolerance
WR_REG,TVP7000,0x01,0x3F,0x0F //Video B/W control
WR_REG,TVP7000,0x01,0x40,0x39 // AVID Start 313 (300+13)
WR_REG,TVP7000,0x01,0x41,0x01 // AVID Start
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WR_REG,TVP7000,0x01,0x42,0x39 // AVID Stop 1593 (313 + 1280)
WR_REG,TVP7000,0x01,0x43,0x06 // AVID Stop
WR_REG,TVP7000,0x01,0x44,0x05 // VBLK F0 Offset
WR_REG,TVP7000,0x01,0x45,0x05 // VBLK F1 Offset
WR_REG,TVP7000,0x01,0x46,0x1E // VBLK F0 Duration 30 lines
WR_REG,TVP7000,0x01,0x47,0x1E // VBLK F1 Duration
//THS8200 720p-60Hz
WR_REG,THS8200,0x01,0x03,0x01 // chip_ctl
// CSC not used
WR_REG,THS8200,0x01,0x19,0x03 // csc_offset3 - CSC bypassed
WR_REG,THS8200,0x01,0x1C,0x60 // dman_cntl - 30 bit input format
// composite sync amplitude control
WR_REG,THS8200,0x01,0x1D,0x00 // dtg_y_sync1
WR_REG,THS8200,0x01,0x1E,0x49 // dtg_y_sync2
WR_REG,THS8200,0x01,0x1F,0xB6 // dtg_y_sync3
WR_REG,THS8200,0x01,0x20,0x00 // dtg_cbcr_sync1
WR_REG,THS8200,0x01,0x21,0x00 // dtg_cbcr_sync2
WR_REG,THS8200,0x01,0x22,0x00 // dtg_cbcr_sync3
WR_REG,THS8200,0x01,0x23,0x23 // dtg_y_sync_upper
WR_REG,THS8200,0x01,0x24,0x2A // dtg_cbcr_sync_upper
// horizontal timing setup
WR_REG,THS8200,0x01,0x25,0x28 // dtg_spec_a
WR_REG,THS8200,0x01,0x26,0x6E // dtg_spec_b
WR_REG,THS8200,0x01,0x27,0x28 // dtg_spec_c
WR_REG,THS8200,0x01,0x28,0x04 // dtg_spec_d
WR_REG,THS8200,0x01,0x29,0x00 // dtg_spec_d1
WR_REG,THS8200,0x01,0x2A,0x04 // dtg_spec_e
WR_REG,THS8200,0x01,0x2B,0xC0 // dtg_spec_h_msb
WR_REG,THS8200,0x01,0x2C,0x00 // dtg_spec_h_lsb
WR_REG,THS8200,0x01,0x2D,0x00 // dtg_spec_i_msb
WR_REG,THS8200,0x01,0x2E,0x00 // dtg_spec_i_lsb
WR_REG,THS8200,0x01,0x2F,0x6E // dtg_spec_k_lsb
WR_REG,THS8200,0x01,0x30,0x00 // dtg_spec_k_msb
WR_REG,THS8200,0x01,0x31,0x00 // dtg_spec_k1
WR_REG,THS8200,0x01,0x32,0x00 // dtg_speg_g_lsb
WR_REG,THS8200,0x01,0x33,0x00 // dtg_speg_g_msb
WR_REG,THS8200,0x01,0x34,0x06 // dtg_total_pixel_msb
WR_REG,THS8200,0x01,0x35,0x72 // dtg_total_pixel_lsb
WR_REG,THS8200,0x01,0x36,0x80 // dtg_linecnt_msb
WR_REG,THS8200,0x01,0x37,0x02 // dtg_linecnt_lsb
WR_REG,THS8200,0x01,0x38,0x82 // dtg_mode - 720p
WR_REG,THS8200,0x01,0x39,0x27 // dtg_frame_field_msb
WR_REG,THS8200,0x01,0x3A,0xEE // dtg_frame_size_lsb
WR_REG,THS8200,0x01,0x3B,0xFF // dtg_field_size_lsb
// CSM setup not required if full-scale range is used
WR_REG,THS8200,0x01,0x4F,0x00 // csm_mode disabled
//discrete output sync control
WR_REG,THS8200,0x01,0x70,0x18 // dtg_hlength_lsb
WR_REG,THS8200,0x01,0x71,0x06 // dtg_hdly_msb
WR_REG,THS8200,0x01,0x72,0x49 // dtg_hdly_lsb
WR_REG,THS8200,0x01,0x73,0x1A // dtg_vlength_lsb
WR_REG,THS8200,0x01,0x74,0x00 // dtg_vdly_msb
WR_REG,THS8200,0x01,0x75,0x01 // dtg_vdly_lsb
WR_REG,THS8200,0x01,0x76,0x00 // dtg_vlength2_lsb
WR_REG,THS8200,0x01,0x77,0xC7 // dtg_vdly2_msb
WR_REG,THS8200,0x01,0x78,0x07 // dtg_vdly2_lsb
// discrete input sync control - use to align picture
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4.4.2 Register Editing
4.4.2.1 Register Map Editor
Main Menu
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WR_REG,THS8200,0x01,0x79,0x00 // dtg_hs_in_dly_msb
WR_REG,THS8200,0x01,0x7A,0x0F // dtg_hs_in_dly_lsb - adjust horizontal position
WR_REG,THS8200,0x01,0x7B,0x00 // dtg_vs_in_dly_msb
WR_REG,THS8200,0x01,0x7C,0x01 // dtg_vs_in_dly_lsb - adjust vertical position
WR_REG,THS8200,0x01,0x82,0x1B // pol_cntl,external FID
END_DATASET
////////////////////////////////////////////////////////////////////////////////
Each command file may contain individual write-to-register (WR_REG) commands.
1. The comment indicator is the double-slash //.
2. The command file is not case-sensitive and ignores all white-space characters.
3. All numbers can be entered as hexadecimal (beginning with 0x) or as decimal.
4. Every dataset in a command file begins with BEGIN_DATASET and ends with END_DATASET. Themaximum number of datasets is 250.
5. The dataset text description is entered between double quotes using the DATASET_NAME command.The enclosed text can be up to 128 characters in length. This text appears in the System Initializationdialog box when the command file is opened.
6. The INCLUDE command inserts the contents of an include file (with an .INC file extension) in-line inplace of the INCLUDE command. Therefore, the include file must not contain the BEGIN_DATASET,END_DATASET, and DATASET_NAME commands.
Note: All included files must be located in the same directory as the command (CMD) file.
7. The write-to-register command is written as follows:
WR_REG, <DeviceFamily>, <Number of data bytes (N)>, <subaddress>, <Data1>, …, <DataN>
or
WR_REG, <Literal slave address>, <Number of data bytes (N)>, <subaddress>, <Data1>, …, <DataN>
The valid device family mnemonics are:
VID_DEC for the video decoders
VID_ENC for the video encoders
THS8200 for the THS8200 device
WinVCC4 translates the device family mnemonic to the slave address that was selected in theWinVCC4 Configuration dialog box upon program startup. This eliminates having to edit command filesif the alternate slave address must be used.
If the literal slave address method is used, then the slave address entered is used directly. Thismethod is normally used for programming the video encoder.
8. A delay may be inserted between commands using the WAIT command, which is written as follows:
WAIT,<# milliseconds>
The following sections describe the available modes of register editing: Register Map Editor, EncoderModule Editor, Generic I
2
C Register Editor, and Property Sheets. Each of these functions can be selectedfrom the Edit menu.
The register map editor (see Figure 4-6 and Figure 4-7 ) allows the display and editing of the entire usedregister space of the device within a simple scrolling text box. To open this window, click on Edit RegisterMap in the Edit menu, and click on the device type to edit. If the intended device type is not shown, thenuse the Windows menu to activate the existing window.
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Main Menu
Figure 4-6. TVP7002 Register Map
Figure 4-7. THS8200 Register Map
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Dams INSTRUMENTS Genelir m Regine! Map AfimleIH/WINM [Dm‘wm I» 00 - RM 01 - RM 02 - RM 03 ~ RM 04 - RIW US - RM 06 ~ RM 07 - RIW UH - HM V Izcsum Addlss: |_| |' Ussfi and Stan we Add.” w: [w ”WNW.“ Radx [—A —'°' andFlead buttons. Dee F —'1 [1-8991 He, 6 "M1 Hiflngan on Loop Com! Beads nud- \ | [ FEM $53!? S"_°“'l Elmel
4.4.2.2 Generic I
2
C Register Editor
Main Menu
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Table 4-2. Register Map Editor Controls
Control Definition
Register Window Scrolling text box that displays the address and data for the I
2
C registers that are defined for the device.
Address Field This contains the I
2
C subaddress that is accessed using the Write and Read buttons. Clicking on a rowselects an address, which then appears in the address field.Note: After clicking on a row, the Data field contains the data that was in the register window. The devicehas not yet been read.The address up/down arrows are used to jump to the next/previous subaddress that is defined for thedevice. If an address is not defined for the device, then it can still be accessed by typing the subaddressin the Address field.
Data Field This contains the data that is written to or was read from the I
2
C subaddress.The data up/down arrows increment/decrement the data value by 1.
Write Button Writes the byte in the Data field to the address in the Address field.
The I
2
C register is written to whether or not the data is different from the last time the register was read.
Read Button Reads the data from the address in the Address field into the Data field and the register window.
Read All Button Reads all defined readable registers from the device and updates the register window.
Hex Button Converts all values in the register window and address and data fields to hexadecimal.
Dec Button Converts all values in the register window and address and data fields to decimal.
Close Button Closes the dialog.Note: Multiple edit register map windows can be open at the same time (one for each device). Use theWindow menu to navigate.
Loop Count Causes subsequent write or read operations to be performed N times. N is entered as a decimal numberfrom 1 to 999.
Edit Indirect Registers Opens the indirect register editor of the TVP7002.
The Generic I
2
C Register Editor (see Figure 4-8 ) allows the display and editing of any device on the I
2
Cbus. This editor works like the Register Map Editor, except that the I
2
C slave address must be entered andthe Read All button is disabled.
To open this window, click on Edit Register Map in the Edit menu and then click on Generic I
2
C.
Figure 4-8. Generic I
2
C Register Editor
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Tms INSTRUMENTS TVP7007 (mas) Pmpmly Sheets Inw Mux | clamp comm} H-PLL | Sam and um} Dl‘nul] Slalusl Inpu Salecuon HSYNC Seleclion HSYNC Inna Polarly VSYNE Selection F HSYNC F Active Low r‘ VSYNC r‘ sun r‘ Active High r‘ Sync 529 r: Auln Damn (-‘ Auto Dame: I: Auln Data-:1 SDG Low Pass File! SUE Thleshnfl F 2 5 MH Sm: Swain! Tl'leshuld - z 11 ‘ e4 ‘ [n 31]:i r WM": [u 255]:1 (" 33 MHI F Bwas: LPF Rsad Al 0K Cami Apply
4.5 TVP7002 Property Sheets
4.5.1 Input Mux
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TVP7002 Property Sheets
The property sheets represent the register data in a user-friendly format. The data is organized byfunction, with each function having its own page and being selectable via tabs at the top.
To open a property sheet, click Edit Property Sheets in the Edit menu and select the device type to edit.
When the property sheet function is started or when tabbing to a different page, all readable registers inthe device are read from hardware to initialize the dialog pages. Values on the page are changed bymanipulating the various dialog controls.
There are OK, Cancel, and Apply buttons at the bottom of each property page.
With the TVP7002, there are six different tabs available within its property sheets. The tabs are organizedby the TVP7002 functions. The following sections describe the additional details and recommendations ofthe controls within each tab.
The Input Mux Property Sheet provides controls for configuring the input connections and sync options.For most applications, auto detect is recommended for HSYNC/VSYNC selection and HSYNC inputpolarity. The TVP7002 automatically senses the presence of SOG and discrete HSYNC/VSYNC inputs. IfSOG and discrete syncs are both present, then the TVP7002 automatically selects and uses the discretesyncs. Input sync status is available in the sync detect status I
2
C register (14h) and can be viewed usingthe status property sheet. The BNC connectors on the TVP7002 EVM inputs must be used forsync-on-green (SOG) or sync-on-y operation.
Figure 4-9. Input Mux Property Sheet
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4.5.2 Clamp
Typical Settings Clamp Start Clamp Width ALC Placement
HDTV (tri-level) 50 (32h) 32 (20h) 90 (5Ah)
SDTV (bi-level) 6 (06h) 16 (10h)
24 (18h)
PC graphics 6 (06h) 16 (10h) 24 (18h)
Bi-Level Sync
Tri-level Sync
Fine Clamp Start (Register 05h)
Clamp Start + Clamp Width (Register 06h)
ALC Placement (Register 05h)
ALC Horizontal Filter (Register 05h)
1 to 1/128 (1/N, where N = number of pixels averaged)
Internal
Clamp
TVP7002 Property Sheets
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The SOG threshold (I
2
C register 10h[7:3]) sets the voltage level threshold of the SOG comparator/slicer.Each step represents an 11-mV change in slice level. The default setting of 0Bh can be used for mostapplications.
The Sync Separator Threshold setting defines the sync separator count interval in internal REFCLK cyclesand is used for VSYNC high/low detection and generation. A setting of 64 (40h) should be suitable for allnominal input formats.
A programmable SOG low-pass filter (I
2
C register 1Ah[7:6]) is provided to filter glitches or noise that couldbe present on the SOG input. Recommended settings are shown in Table 4-3 .
Table 4-3. Recommended SOG LPF Settings
SDTV Formats 10 MHz
HDTV and PC Graphics 33 MHz or Bypass
Note: Excessive filtering of high frequency SOG inputs can result in sync tip attenuation and syncprocessing issues.
Note: SOG filter settings affect SOG analog delay resulting in a slight HSOUT alignment shift.When discrete output syncs are used, the HSOUT start setting on the Output Property Sheetcan be used to compensate for this horizontal alignment shift.
Most ac-coupled video applications use the internally generated clamp pulse for dc restoration prior to theADCs. The fine clamp start (I
2
C register 05h) is relative to HSYNC trailing or leading edge depending onthe Clamp REF bit setting in I
2
C register 15h. In most cases, the trailing edge of the negative sync tip isused to avoid clamping during the sync pulse.
The fine clamps must be enabled in I
2
C Register 2Ah and correctly positioned during the horizontalblanking interval. See Figure 4-10 for recommended clamp placement settings for various input formats.HDTV formats having tri-level syncs require additional delay to avoid clamping during the tri-level syncinterval.
Figure 4-10. Clamp and ALC Placement
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TVP7002 Property Sheets
Both clamp and auto-level control (ALC) placement are relative on the HSYNC reference edge selected bythe clamp REF bit in I
2
C register 15h. Most applications set up the TVP7002 to use the trailing edge of thenegative sync tip for placement of the fine clamp and ALC. The maximum ALC horizontal filter setting maybe limited by the back porch duration for some formats.
Either bottom-level or middle-level clamping can be selected. These must be set according to the videoinput format. Bottom-level clamping must be used for Y and RGB inputs. Middle-level clamping must beused for Pb and Pr inputs. Coarse clamp must be left disabled for most applications. A typical clamp setupfor RGB graphics is shown in Table 4-4 and Figure 4-11 .
Most applications use the internal fine clamp pulse that is automatically generated from the HSYNC input.Clamp polarity is only effective when an external clamp is used.
Note: The maximum ALC horizontal filter setting that can be used with some formats may belimited by the back porch duration.
Table 4-4. Typical Clamp Setup for RGB Graphics
I
2
C Address Setting Description
05h 06h Clamp start
06h 10h Clamp width
0Fh 0Eh Internal clamp enabled
10h 80h Bottom-level clamping for RGB
15h 00h Clamp pulse relative to HSYN trailing edge
2Ah 87h Enable fine clamps
2Dh 00h Coarse clamp disabled
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l INSTRUMENTS TVP7002 (0x53) Pmpclty Sheets EwaUuIv Endiasi EVE '— GN I' am: I‘ mum tie-mammal IH-PLL] ammnml um| Slams] l7 melamzm mmmmi r: HSYNETnaiIuEdw r HSYNCLeatthdga DUDLWFauFRM' r 0.5MH1 (‘1‘7MH2 (‘4.8MH2 OK Cancel Apply
4.5.3 PLL
TVP7002 Property Sheets
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Figure 4-11. Clamp Control Property Sheet
Note: Bottom-level clamping is required for YGBR inputs, while middle-level clamping is requiredfor PbPr inputs.
A programmable coarse clamp low-pass filter is provided (see I
2
C register 1Ah) primarily for use with theSOG inputs that utilize a coarse bottom level sync tip clamp only. Recommended filter settings are shownin Table 4-5 .
Table 4-5. Recommended Clamp LPF Settings
SDTV Formats 0.5 MHz
HDTV and PC Graphics 4.8 MHz
Note: Excessive clamp filtering can lead to SOG clamp level and sync processing issues.
A PLL setup calculator is integrated into the H-PLL Property Sheet. The H-PLL Feedback Divider, VCOrange, and Charge Pump settings can be automatically calculated by entering the HSYNC and Pixelfrequencies and pressing the Calculate>> button. The new settings are not written to the TVP7002 untilthe Program>> button is pressed.
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Dams INSTRUMENTS wpmm (mas) Pmpcrly Sheets Iwm|mmu HPLL sawnmlum|sxm| 5mm 5mm aw Emy HSYNCFIaq A] as KHz [Lu-mm mm L] 74 25 MHz [Lo-1550] n 130 Jan Sm J_' 130 on [dog] NOTES: 1‘ M'5)"WWMWIWQJHWNCFM[WWHSYNCFVWI 2 TmmrmluM->>"musemmm1 3 mmmmmummm l. fickfioguntnwngunmeHPLLw OK Cancel Apply
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TVP7002 Property Sheets
Typically the Preferred Post Divider will be set to 1, and the feedback divider will be set to the totalnumber of pixels per line. For lower frequency SDTV video formats, a 2x feedback divider value can beused with a Post Divider of 2 to improve jitter performance. In this case, the PLL operates at twice thedesired frequency, but the output pixel rate will be at the PLL frequency divided by 2.
Note: When a Post Divider of 2 is used, only 16 of the 32 ADC clock phase control settings areavailable for use in the H-PLL Phase Select Register. ADC clock phase adjustments aretypically required for PC graphics for precise alignment of the sample clock with the inputpixel.
Figure 4-12. PLL Property Sheet
The Frame Rate, Horiz Freq, and Pixel Freq information reported in the Current Status frame arecalculated values based on the current H-PLL Feedback Divider and the Lines/Frame and Clocks/LineStatus read from the TVP7002 registers. The precision of these calculated values will depend on whetherthe internal reference clock or the 27-MHz external reference clock is selected. Current settings and statuscan be read at any time by pressing the Read All button.
An internally or externally generated coast signal can be used to put the PLL in coast or free-run mode toavoid disruptions in HSYNC during vertical blanking. When the internal coast is in use, the pre-coast andpost-coast settings specify the coast interval range relative to the internally-detected VSYNC. Pre-coastspecifies the number of lines before detecting VSYNC, and post-coast specifies the number of lines afterVSYNC that are used for the coast interval.
SLEU098 – May 2008 WinVCC4 in Depth 29
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4.5.4 Gain and Offset - ALC
TVP7002 Property Sheets
www.ti.com
Table 4-6. Recommended Coast Settings
Format Pre-Coast Post-Coast
480i/p 03h 03h
576i/p 03h 03h
1080i 01h 00h
1080p 01h 00h
720p 01h 00h
PC graphics with SOG 01h 00h
The Gain and Offset property sheet provides controls for both analog and digital gain/offset adjustment.The coarse gain and offset are analog in nature and are applied prior to the ADCs. Fine gain, fine offset,and automatic level correction (ALC) are applied in the digital domain after the ADCs. Coarse gainprovides an analog gain range of 0.5 to 2.0, while Fine gain provides a digital gain range of 1 to 2.
Figure 4-13. Gain and Offset Property Sheet
Stable output offset levels are maintained by use of the ALC feedback level control in the TVP7002. Twosets of filter coefficients are available that define the level of filtering applied on each line (horizontal) andthe amount of feedback correction that is applied per line update (vertical). The horizontal coefficient (I
2
Cregister 28h, NSH[2:0]) specifies the number of pixels that are used in the horizontal filter. The ALC filtermust be applied during the horizontal blank interval following the clamp pulse, so it must be correctlypositioned using the ALC placement register (register 31h). The amount of horizontal filtering that canused depends on the ALC placement and the horizontal blanking interval of the input video format. SeeTable 4-7 for recommended ALC placement settings.
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4.5.5 Output
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TVP7002 Property Sheets
The vertical coefficient (I
2
C register 28h, NSV[3:0]) specifies the amount of feedback error correctionderived from the horizontal filter that is applied to each line update. The NSV coefficient can range from 1(maximum error applied) to 1/1024 (minimum error applied). The TVP7002 default filter coefficients shouldbe adequate for most applications.
In the ALC operating mode, the fine offset registers are used to position the final digital output levels. Toprevent bottom-level clipping at the ADCs, a coarse offset setting of 16 (10h) is recommended. Anyclipping that occurs at the ADC input cannot be recovered by the ALC.
Table 4-7. Recommended ALC Settings
Format Register 31h ALC Placement Register 28h ALC Filter
SDTV and PC graphics 24 (18h) 53h
HDTV 90 (5Ah) 53h
The Output property sheet provides controls for enabling outputs, selecting the output format, settingHSOUT polarity/position/width, and specifying embedded sync or Data Enable (DE) output timing. Atpower-up, the RGB data, DATACLK, and syncs are in a high-impedance state until enabled in I
2
C register17h or until programming the TVP7002EVM with one of the datasets include in the initialization file. TheDATACLK output polarity is selectable in I
2
C register 18h.
Figure 4-14. Output Property Sheet
The TVP7002 provides support for a 30-bit 4:4:4 or a 20-bit 4:2:2 output format. The 20-bit 4:2:2 output
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TEXAS INSTRUMENTS
4.5.6 Status
TVP7002 Property Sheets
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format must be used when either the color space converter or embedded digital syncs are used.Additionally, when embedded syncs are used, the ITU-R BT.601 or the extended (4-1019) output coderange must be used instead of the full (0 to 1023) RGB output code range. When the ITU-R BT.601reduced code range (YRGB range = 64-940) is used, the YRGB fine digital offset settings should be set to64 to avoid clipping of active video below code 64.
The AVID Start/Stop, VBLNK Offset/Length, and F-Bit Start settings define the position of the embeddedsync code transitions and also the position of the Field ID (FID) and Data Enable (DE) when these outputsare used. When embedded syncs are enabled, the SAV embedded sync position can be adjusted with theAVID Start setting, and the EAV code can be adjusted with the AVID Stop setting. The lines where theembedded V-bit and F-bit transitions occur can be adjusted with the VBLK and F-Bit settings. SeeAppendix B for more information on embedded sync settings.
The TVP7002 color space converter (CSC) can be used to convert an RGB input to 20-bit YCbCr. TheTVP7002 should default to CSC coefficients required for conversion of RGB to HDTV YCbCr. The CSCcoefficients are fully programmable in I
2
C registers 4Ah to 5Bh. See Appendix C for coefficients requiredfor conversion to both HDTV and SDTV YCbCr color spaces.
Note: FID and DE output support is provided through use of the multi-function FIDOUT pin 22. SeeI
2
C register 17h for more information.
The Status property sheet reports input sync status from I
2
C register 14h and line and frame rateinformation available in I
2
C registers 37h to 39h. Lines per Frame and REFCLKs per Line are read directlyfrom the I
2
C registers, while the calculated status is derived from the measured values and the currentH-PLL feedback divider.
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Dams INSTRUMENTS TVP7007 (mas) Pmpcrly Sheets Imam-(I mm| H-PLLI ammnml um Slams| fumclwsmi *VSYNElmSmi NDT DETECTED NOT nETEcIEn % ACINE HIGH ACTIVE HIGH 1|:an N am] FROM see man SYNC SEP HEFELK Flu: 2mm isna Inpu Sinai iEEIAST mu SW7 [MHz] DEIECIED Acnv: HIGH I7 Em REF“ mam 02 Read” OK Cancel
4.5.6.1 Reading the Register Map
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TVP7002 Property Sheets
Figure 4-15. Status Property Sheet
Either an internal REFCLK (~6.5 MHz) or an external 27-MHz REFCLK can be used for REFCLKS perLine and HSYNC Width detection. The external 27-MHz REFCLK is recommended for a more stable andprecise read back. The TVP7002 EVM is shipped with a 27-MHz oscillator connected to the EXTCLK input(pin 80).
Note: The internal REFCLK is not a precise clock source. Some part to part variation in clockfrequency and status read back should be expected.
The property sheets were designed so that the data displayed is always current. Certain actions cause theentire register map to be read from the device and to update the property sheets. This happens when:
1. Property sheets are initially opened.
2. Tabbing from one page to another.
3. Read All is clicked.
4. Making the Property Sheets window the active window (by clicking on it).
5. Making a Register Map Editor window the active window (by clicking on it).
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TEXAS INSTRUMENTS
4.5.6.2 Auto-Update from Device
TVP7002 Property Sheets
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Items 4 and 5 above are referred to as the Auto-Update feature. Auto-Update can be disabled by settingits program option button to DISABLED. This button is located on the initial dialog box (WinVCC4Configuration).
With Auto-Update enabled (default), the user can open both the Property Sheets and the Register MapEditor at the same time. Changes made to the Property Sheets (and applied) are updated in the registermap window as soon as the Register Map window is clicked on. It also works the other way; changesmade in the Register Map Editor are updated in the Property Sheets as soon as the Property Sheetswindow is clicked on.
Table 4-8. Use of Property Sheet Controls
Property Sheet Dialog Control What Do I Do With It? When is Hardware Updated?
Read-only field Read status information N/A
Check box Toggle a single bit After Apply
Drop-down list Select from a text list After Apply
Edit box Type a number After Apply
Up/down arrows: ImmediatelyEdit box with up/down arrows Use up/down arrows or type a number
Type a number: After Apply
Slider Slide a lever Immediately
Pushbutton Initiate an action Immediately
Table 4-9. Property Sheet Button Controls
Button
DefinitionControl
OK Writes to all writeable registers whose data has changed. A register is flagged as changed if the value to bewritten is different from the value last read from that address.Closes the dialog.
Cancel Causes all changes made to the property page since the last Apply to be discarded. Changes made to dialogcontrols with 'immediate hardware update' are not discarded, because they have already been changed inhardware.
Does not write to hardware.Closes the dialog.
Apply Writes to all writeable registers whose data has changed. A register is flagged as changed if the value to bewritten is different from the value last read from that address.
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l TEXAS INSTRUMENTS
5.1 Troubleshooting Guide
Chapter 5SLEU098 – May 2008
Troubleshooting
This chapter describes ways to troubleshoot the TVP7002EVM.
If there are problems with the TVP7002EVM hardware or the WinVCC4 software, see Table 5-1 andTable 5-2 for possible solutions.
Table 5-1. TVP7002EVM Troubleshooting
Symptom Cause Solution
At startup, the error message "Cannot The parallel port driver supplied with Run Port95NT.EXE on the CD to install the driver.find DLL file DLPORTIO.DLL" the EVM has not been installed.appears.
Blank screen Wrong analog input is selected. Go to Edit->Property Sheets->TVP7002, AnalogVideo page, select the correct video input(s) andclick Apply.
The Composite Video 1 input is default.
Source is connected to the wrong Connect source to the correct input connector.input connector.
Vertical stability or flashing display Mode detect issue due to Adjust HSYNC output delayHSYNC/VSYNC alignment
Line noise present with PLL phase setting is not set correctly Adjust PLL phase settinghigh-frequency vertical line input for the input sourcepattern
Line noise present with flat field Excessive noise on the input source Filter the inputs or try a different source
Picture too dark Clamp or ALC not set correctly Reposition Clamp or ALC. Reduce ALC horizontalfilter coefficient
SOG/Y does not work SOG clamp disabled Set SOG_CE bit in register 2Eh to 1.
SOG does not work when using the The VGA input is not connected to an The BNC connectors must be used for SOGVGA connector SOG input pin operation
SLEU098 – May 2008 Troubleshooting 35
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Tms INSTRUMENTS Izc Test Repor THSEZEIU FAILED » Read, Dev=UMUAddv=Ux05 Dalafixm A Miscompav: [Wrote DxU‘] TVP7E|D2 FA‘LED , Read, Dev=DxBA,Add|=Ele|4, Dala=DxDD , Miscnmpale [Wrote M3]
Troubleshooting Guide
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Table 5-2. I
2
C Troubleshooting
Symptom Cause Solution
No I
2
C communication I
2
C slave address is wrong. Close and restart WinVCC4. Choose the alternate slaveaddress in the WinVCC4 Configuration dialog.
Parallel cable is not connected from PC Connect cable.parallel port to the EVM DB25 connector.
EVM is not powered on. The power supply must be plugged into a 100-V to 240-V/47-Hz to 63-Hz power source and the cord must be pluggedinto the power connector on the EVM.
Wrong type of parallel cable Some parallel cables are not wired straight throughpin-for-pin. Use the cable supplied with the EVM.
PC parallel port mode is not set correctly. Reboot PC, enter BIOS setup program, set parallel port LPT1mode (address 378h) to ECP mode or bidirectional mode(sometimes called PS/2 mode or byte mode). If already set toone of these two modes, switch to the other setting (seeSection 5.2.1 ).
Device was placed in power-down mode. Press the reset button on the TVP7002EVM.
EVM was configured for an external I
2
C Reinstall 0- Ωresistors R5 and R6. Control EVM using the PCmaster. parallel port.
Still no I
2
C communication The PC may not be capable of operating in the requiredparallel port mode. This is true of some laptop computers.Use a different computer, preferably a desktop PC.
When WinVCC4 is started and the WinVCC4 Configuration dialog box is closed with OK, the I
2
C systemtest is performed (unless the I
2
C System Test program options button was disabled).
If the I
2
C system test fails, a dialog box appears. Figure 5-1 reports that a read from TVP7002 failed,using slave address 0xB8, subaddress 0x05. The data read was 0x00.
After noting which device had a problem, click OK to continue. Next, the Corrective Action Dialog boxappears to help fix the problem.
Figure 5-1. I
2
C System Failure Dialog Box
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5.2 Corrective Action Dialogs
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Corrective Action Dialogs
After closing the I
2
C system test report dialog box, the dialog box in Figure 5-2 appears.
Figure 5-2. Corrective Action Dialog Box
1. If the parallel port cable is NOT connected between to PC and the TVP7002EVM or if the EVM poweris not on, then:
a. Click NO.b. The dialog box shown in Figure 5-3 appears with instructions on how to correct the problem.c. Correct the problem.d. Click OK to continue
Figure 5-3. Corrective Action Required
2. If the cable is connected from the PC parallel port to the TVP7002EVM and the EVM power is on:
a. Click Yes.b. The dialog box shown in Figure 5-4 appears. This dialog box appears if the PC parallel port modesetting may need to be changed.
Note: Run the PC BIOS setup program only if the I
2
C communication problem cannot beresolved in another way (correct slave address settings, reset or power cycle the EVM,and/or check that the device type selected was TVP7002).
c. Click OK to continue.d. Click OK to close it and get to the main menu.e. Click Exit in the File menu to exit the program.f. See troubleshooting guide above.
Figure 5-4. Corrective Action Required
SLEU098 – May 2008 Troubleshooting 37
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INSTRUMENTS m [not Repon Bud, Dov-06AM“, BM - NU AM: HDIDEV I— IMIIWEHW
5.2.1 Setting the PC Parallel Port Mode
5.2.2 General I
2
C Error Report
Corrective Action Dialogs
www.ti.com
Note: Run the PC BIOS setup program only if the I
2
C communication problem cannot be resolvedin another way (correct slave address settings, reset or power cycle the EVM, and/or checkthat the device type selected was TVP7002).
1. Restart the PC.
2. During the boot process, enter the BIOS setup program by pressing the required key (the initial textscreen usually indicates which key to press).
3. Find where the parallel port settings are made.
4. Set the parallel port LPT1 at address 378h to ECP mode or bidirectional mode (sometimes called PS/2mode or byte mode). If one of these two modes is already selected, then change to the opposite mode.
5. Exit and save changes.
The error report shown in Figure 5-5 appears when an I
2
C error occurs at any time other than after the I
2
Csystem test. In this example, there was an acknowledge error at slave address 0x54 (the video triple ADCmodule). The error occurred on Read Cycle Phase 1 on the device (slave) address byte.
Figure 5-5. I
2
C Error Report
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l TEXAS INSTRUMENTS
Chapter 6SLEU098 – May 2008
TVP7002EVM Schematics
SLEU098 – May 2008 Troubleshooting 39
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I INSTRUMENTS
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Anti-Aliasing Filters
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I TEXAS INSTRUMENTS
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{i TEXAS INSTRUMENTS WE a» A 1%}: m: 13% H $6 mm 5:?
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F1 FUSE
2
3
1
P2
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VOUT2 IS 1.9V 250mA
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C4
0.1uF
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1
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2
VIN1B
3
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5
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6
/RESET
7
GND
8
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10 NC 11
VOUT2B 12
VOUT2A 13
VSENSE2/FB2 14
PG2 15
PG1 16
VSENSE1/FB1 17
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VOUT1A 19
NC 20
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21
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2
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C30
22uF
C23
1uF
C24
1uF
C21
1uF
D3.3V
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L4
L5
C27
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C20
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L1
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C18
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2
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22uF
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*‘P‘Ifismm
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FFOE/DIG_V
1FFRE/DIG_H
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3FFWE/DVALID
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6FSY/HC/HSYA/~BLNK
7FFRSTW/CBFLAG
8FPDAT/VSYA/M2
9CLK5/M1
10 GND
11 PHI_D0
12 PHI_D1
13 PHI_D2
14 PHI_D3
15 PHI_D4
16 PHI_D5
17 PHI_D6
18 PHI_D7
19 PHI_A0
20 PHI_A1
21 PHI_CS
22 PHI_DS/RD
23 SDA/PHI_RWW
24 SCL/PHI_ACK
25 GND
26 GND
27 GND
28 5V
29 5V
30
D_VS
31D_HS
32 D_PREF
33 D_RDY
34 D_SCLK
35 VACTIVE
36SOGOUT
37 ITRDY
38 GND
39 GPCL
40 INTREQ
41 GPIO0
42 GPIO1
43 GPIO2
44 GPIO3
45 GND
46 GPIO4
47 GPIO5
48 GPIO6
49 GPIO7
50 GND
51 AMCLK
52 ASCLK
53 ALRCLK
54 AMXCLK
55 GND
56 GND
57 GND
58 5V
59 5V
60
D9
76 GND
77 RCr0
78 RCr1
79 RCr2
80 RCr3
81 RCr4
82 RCr5
83 RCr6
84 RCr7
85 RCr8
86 RCr9
87 GND
88 GND
89 5V
90
SCLK
91PCLK
92 VSYNC
93 GLCO
94 FID
95 GND
96GY0
97 GY1
98 GY2
99 GY3
100 GY4
101 GY5
102 GY6
103 GY7
104 GY8
105 GY9
106 GND
107 BCb0
108 BCb1
109 BCb2
110 BCb3
111 BCb4
112 BCb5
113 BCb6
114 BCb7
115 BCb8
116 BCb9
117 GND
118 GND
119 5V
120
PREF
61AVID
62 HSYNC
63 PALI
64 RESET
65 GND
66D0
67 D1
68 D2
69 D3
70 D4
71 D5
72 D6
73 D7
74 D8
75
P3
SAMTEC_TMMS_120PIN_M_RA
SDA
SCL
SDA
SCL
CONNECTOR
REV 1.1
D5V
D5V D5V D5V
G[9..0]
DCLK
VS
HS
HS VS
DCLK
B[9..0]
RESETBRESETB
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B[9..0]
G[9..0]
G0
G1
G2
G3
G4
G5
G6
G7
G8
G9
R[9..0] R[9..0]
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R2
R3
R4
R5
R6
R7
R8
R9
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SLEU098 – May 2008 TVP7002EVM Schematics 43
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Date: 8-Jun-2007 Sheet of
File: C:\userdata\TVP7002\EVM\TVP7002BoardRev1.0.ddb
Drawn By:
TESTPOINTS
SDA
SCL SDA
SCL
REV 1.1
B[9..0]
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
H4
HEADER 10X2
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
H3
HEADER 10X2
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
H2
HEADER 10X2
G[9..0]
R[9..0]
B[9..0]
G[9..0]
R[9..0]
SOG_OUT SOG_OUT
VS
HS HS
VS
TP
1
GND1
GND
TP
1
GND
TP
1
SCL
SCL
TP
1
SDA
SDA
TP
1
HS
HSOUT
TP
1
VS
VSOUT
TP
1
SOG_OUT
CLAMPCLAMP
COAST COAST
TP
1
CLAMP
TP
1
COAST
D3.3V
DVDD
AVDD
A3.3V
PLLAVDD
TP
1
AVDD
TP
1
PLLAVDD
TP
1
DVDD
TP
1
A3.3V
TP
1
D3.3V
DCLK
DCLK
DE_FID
DE_FID
TP
1
DE_FID
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
G0
G1
G2
G3
G4
G5
G6
G7
G8
G9
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
1
2
DCLK
HEADER 2
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Date: 8-Jun-2007 Sheet of
File: C:\userdata\TVP7002\EVM\TVP7002BoardRev1.0.ddb
Drawn By:
I2CA
I2C ADDRESS SELECTION
2-3: Base Addr 0xBA
1-2: Base Addr 0xB8 - Default
R26
10k
SDA
SCL
TVP7002
REV 1.1
R27
10k
C53 1nF
C9 0.1uF
C12 0.1uF
C11 0.1uF
C10 0.1uF
C13 0.1uF
C14 0.1uF
C15 0.1uF
C41
.1uF
RESETB
PWDN
1 3
2J2
JMP3
C8 0.1uF
C52 1nF
C7 0.1uF
C51 1nF
C60.1uF
GIN_3
GIN_1
BIN_1
BIN_3
RIN_1
RIN_3
COAST
CLAMP
SDA
SCL
I2CA
RESETB
PWDN
B_OUT0
B_OUT1
B_OUT2
B_OUT3
B_OUT4
B_OUT5
B_OUT6
B_OUT7
B_OUT8
B_OUT9
G_OUT0
G_OUT1
G_OUT2
G_OUT3
G_OUT4
G_OUT5
G_OUT6
G_OUT7
G_OUT8
G_OUT9
R_OUT0
R_OUT1
R_OUT2
R_OUT3
R_OUT4
R_OUT5
R_OUT6
R_OUT7
R_OUT8
SOG_OUT
HS_OUT
VS_O UT
R_OUT9
DCLK_OUT
PIN_89
FILT2
FILT1
VSYNC_A
VSYNC_B
EXT_CLK
HSYNC_A
B_OUT0
B_OUT1
B_OUT2
B_OUT3
B_OUT4
B_OUT5
B_OUT6
B_OUT7
B_OUT8
B_OUT9
G_OUT0
G_OUT1
G_OUT2
G_OUT3
G_OUT4
G_OUT5
G_OUT6
G_OUT7
G_OUT8
G_OUT9
R_OUT0
R_OUT1
R_OUT2
R_OUT3
R_OUT4
R_OUT5
R_OUT6
R_OUT7
R_OUT8
R_OUT9
DCLK_OUT
SDA
SCL
RESETB
VS_O UT
HS_OUT
SOG_OUT
SOG_OUT
C47
.1uF
C43
.1uF
C44
.1uF
C34
.1uF
C46
.1uF
C36
.1uF
C48
.1uF
C38
.1uF
C35
.1uF
C37
.1uF
C40
.1uF
C39
.1uF
C42
.1uF
C45
.1uF C50
4.7nF
C5
0.1uF
FILT1
FILT2
R35
RESARRAY_ISO_8
R36
RESARRAY_ISO_8
R34
RESARRAY_ISO_8
R37
RESARRAY_ISO_8
R38 49.9
PIN_89
R[9..0]
G[9..0]
B[9..0]
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
G0
G1
G2
G3
G4
G5
G6
G7
G8
G9
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R[9..0]
G[9..0]
B[9..0]
DCLK DCLK
VS VS
HS HS
D3.3V
D3.3V DVDD
AVDD
A3.3V
A3.3V
AVDD
R25
No Pop
1 3
2J1
JMP3
PLLAVDD
PLLAVDD
A3.3V
DVDD
D3.3V
D3.3V
1
2
3
4
5
EXTCLK
SMA_PCB_MT_MOD
R17
50
GREEN
BNC_RA
BLUE
BNC_RA
RED
BNC_RA
R31
75
R32
75
R33
75
VSYNC
BNC_RA
HSYNC
BNC_RA
VSYNC_B
GIN_1
BIN_1
RIN_1
R16
DNP
R10
DNP
R15 DNP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DB15
DB15F
RIN_3
GIN_3
BIN_3
R28
75
R29
75
R30
75
R12
DNP
R14
10K
R13 330
R11 330
FB1
FB2
FB3
R2
0
R23
1.5k
R3 No Pop
R1
NO POP
PLLAVDD
TEST
TEST
C54
.1uF
COAST
COAST
CLAMP
CLAMP
R39
10k
R40
10k
12
3
4
JP1
12
3
4
JP2
12
3
4
JP3
G_FIL_IN G_FIL_OUT
B_FIL_IN B_FIL_OUT
R_FIL_IN R_FIL_OUT
SOGIN_1
1
GIN_1
2
AGND
3
AVDD
4
AGND
5
AVDD
6
AVDD
7
AGND
8
RIN_3
9
RIN_2
10
RIN_1
11
A33GND
12
A33VDD
13
A33VDD
14
A33GND
15
BIN_3
16
BIN_2
17
BIN_1
18
AVDD
19
AGND
20
NSUB
21
FIDOUT
22
VSOU T
23
HSOUT
24
SOGOUT
25
IOVDD
26
IOGND
27
DATACLK
28
B_9
29
B_8
30
B_7
31
B_6
32
B_5
33
B_4
34
B_3
35
B_2
36
B_1
37
B_0
38
DVDD
39
GND
40
IOVDD
41
IOGND
42
G_9
43
G_8
44
G_7
45
G_6
46
G_5
47
G_4
48
G_3
49
G_2
50
G_1 51
G_0 52
IOVDD 53
IOGND 54
R_9 55
R_8 56
R_7 57
R_6 58
R_5 59
IOGND 60
R_4 61
R_3 62
R_2 63
R_1 64
R_0 65
IOVDD 66
IOGND 67
GND 68
DVDD 69
PWDN 70
RESETB 71
TMS 72
I2CA 73
SCL74
SDA 75
CLAMP 76
COAST 77
VSYNC_A 78
VSYNC_B 79
EXT_CLK 80
HSYNC_A 81
HSYNC_B 82
PLL_AGND 83
PLL_AVDD 84
PLL_AVDD 85
PLL_AGND 86
FILT1 87
FILT2 88
PLL_F 89
PLL_AGND 90
NSUB 91
A33GND 92
A33VDD 93
A33VDD 94
A33GND 95
GIN_4 96
SOGIN_3 97
GIN_3 98
SOGIN_2 99
GIN_2 100
PAD 101
U1
TVP7002
DE_FID
DE_FID
16
2 5
U7A
SN74LVC2G17
16
2 5
U6A
SN74LVC2G17
C63
1nF
C64
1nF
4
3
U6B
SN74LVC2G17
4
3
U7B
SN74LVC2G17
C66
.1uF
C65
.1uF
A3.3V
A3.3V
HSYNC_A
VSYNC_A
OE
1
GND 2
OUT
3
VCC 4
X1
MMD_27M_OSC_SMT
D3.3V
C67
.1uF
1 3
2J3
JMP3
REF_CLK
SMA_CLK
DE_FIDOUT
DE_FIDOUT
HSYNC_B
HSYNC_B
HSIN_A
VSIN_B
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Size
B
Date: 8-Jun-2007 Sheet of
File: C:\userdata\TVP7002\EVM\TVP7002BoardRev1.0.ddb
DrawnBy:
L6
NOPOP
C56
NOPOP
C57
NOPOP
C49
NOPOP
L7
NOPOP
C59
NOPOP
C61
NOPOP
C55
NOPOP
L8
NOPOP
C60
NOPOP
C58
NOPOP
C62
NOPOP
REV 1.1
RGB ANTI-ALIASING FILTERS
G_FIL_IN G_FIL_OUT
R_FIL_IN R_FIL_OUT
B_FIL_IN B_FIL_OUT
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Size
C
Date: 1-Sep-2005 Sheet of
File: C:\Documents and Settings\a0214685.ENT\Desktop\THS8200EVM_MODULE_REV1_2\THS8200EVM_MODULE_REV1_2.ddb
Drawn By:
SCL
SDA
I2C
I2C
THS8200EVM REV2.0
SCLK
VSYNC
FID
HSYNC
SDA
SCL
GY[9..0]
CONN_RESET
RCr[9..0]
BCb[9..0]
Connector
Connector
FID
SCL
SDA
GY[9..0]
SCLK
VSYNC
HSYNC
RCr[9..0]
BCb[9..0]
HS_OUT
VS_OUT
DCLK
D656[9..0]
Testpoints
Testpoints
FID
SCL
SDA
GY[9..0]
VSYNC
HSYNC
RESET
RCr[9..0]
BCb[9..0]
SCLK
HS_OUT
VS_OUT
DCLK
D656[9..0]
THS8200
THS8200 Y/G
Pb/B
Pr/R
VESA
RESET
CONN_RESET
Power
Power
THS8200EVM - MAIN
1 6
REV 2.0
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I TEXAS INSTRUMENTS
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Number Revision
Size
C
Date: 1-Sep-2005 Sheet of
File: C:\Documents and Settings\a0214685.ENT\Desktop\THS8200EVM_MODULE_REV1_2\THS8200EVM_MODULE_REV1_2.ddb
Drawn By:
THS8200EVM - I2C
SDA
SCL
C1
0.1uF
R1
2.2k
R3
2.2k
R2
2.2k R4
2.2k
R5
2.2k
SCL
R7
0
SDA
R6
0
D3_3V
DB11
DB9
DB17
DB15
5
6
U1C
74AHC05
11 10
U1E
74AHC05
9
8
U1D
74AHC05
13 12
U1F
74AHC05
3
4
U1B
74AHC05
D3_3V
12
147
U1A
74AHC05
R13
2.2k
R14
2.2k
2 6
REV 2.0
8
7
6
5
4
3
2
14
1
15
16
17
18
19
20
13
12
11
10
9
21
22
23
24
25
26 27
P3
DB25F
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C
Date: 1-Sep-2005 Sheet of
File: C:\Documents and Settings\a0214685.ENT\Desktop\THS8200EVM_MODULE_REV1_2\THS8200EVM_MODULE_REV1_2.ddb
Drawn By:
FFOE/DIG_V
1FFRE/DIG_H
2FFRSTWIN/~SCLK
3FFWE/DVALID
4FFIE/CCVALID
5VGAV/SYNC_T
6FSY/HC/HSYA/~BLNK
7FFRSTW/CBFLAG
8FPDAT/VSYA/M2
9CLK5/M1
10 GND
11 PHI_D0
12 PHI_D1
13 PHI_D2
14 PHI_D3
15 PHI_D4
16 PHI_D5
17 PHI_D6
18 PHI_D7
19 PHI_A0
20 PHI_A1
21 PHI_CS
22 PHI_DS/RD
23 SDA/PHI_RWW
24 SCL/PHI_ACK
25 GND
26 GND
27 GND
28 5V
29 5V
30
D_VS
31 D_HS
32 D_PREF
33 D_RDY
34 D_SCLK
35 VACTIVE
36 SOGOUT
37 ITRDY
38 GND
39 GPCL
40 INTREQ
41 GPIO0
42 GPIO1
43 GPIO2
44 GPIO3
45 GND
46 GPIO4
47 GPIO5
48 GPIO6
49 GPIO7
50 GND
51 AMCLK
52 ASCLK
53 ALRCLK
54 AMXCLK
55 GND
56 GND
57 GND
58 5V
59 5V
60
D9
76 GND
77 RCr0
78 RCr1
79 RCr2
80 RCr3
81 RCr4
82 RCr5
83 RCr6
84 RCr7
85 RCr8
86 RCr9
87 GND
88 GND
89 5V
90
SCLK
91 PCLK
92 VSYNC
93 GLCO
94 FID
95 GND
96 GY0
97 GY1
98 GY2
99 GY3
100 GY4
101 GY5
102 GY6
103 GY7
104 GY8
105 GY9
106 GND
107 BCb0
108 BCb1
109 BCb2
110 BCb3
111 BCb4
112 BCb5
113 BCb6
114 BCb7
115 BCb8
116 BCb9
117 GND
118 GND
119 5V
120
PREF
61 AVID
62 HSYNC
63 PALI
64 RESET
65 GND
66 D0
67 D1
68 D2
69 D3
70 D4
71 D5
72 D6
73 D7
74 D8
75
P2
SAMTEC_TMMS_120PIN_F_RA
FID
FID
GY[9..0] GY[9..0]
BCb[9..0] BCb[9..0]
GY0
GY1
GY2
GY3
GY4
GY5
GY6
GY7
GY8
GY9
BCb0
BCb1
BCb2
BCb3
BCb4
BCb5
BCb6
BCb7
BCb8
BCb9
THS8200EVM - CONNECTOR
D5V
D5V
SCLK
HSYNC VSYNC
SDA
SCL
SCLK
VSYNC
HSYNC
SDA
SCL
CONN_RESET
CONN_RESET
D5V D5V
RCr[9..0] RCr[9..0]
RCr0
RCr1
RCr2
RCr3
RCr4
RCr5
RCr6
RCr7
RCr8
RCr9
3 6
REV 2.0
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123456
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Title
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Size
C
Date: 1-Sep-2005 Sheet of
File: C:\Documents and Settings\a0214685.ENT\Desktop\THS8200EVM_MODULE_REV1_2\THS8200EVM_MODULE_REV1_2.ddb
Drawn By:
D1_8V
D3_3V
SDA
SCL
SDA
SCL
TP
1
SDA
TP
TP
1
SCL
TP
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
H1
HEADER 10X2
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
H2
HEADER 10X2
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
H3
HEADER 10X2
GY[9..0]
RCr[9..0]
BCb[9..0] BCb[9..0]
GY[9..0]
RCr[9..0]
RCr0
RCr1
RCr2
RCr3
RCr4
RCr5
RCr6
RCr7
RCr8
RCr9
GY0
GY1
GY2
GY3
GY4
GY5
GY6
GY7
GY8
GY9
BCb0
BCb1
BCb2
BCb3
BCb4
BCb5
BCb6
BCb7
BCb8
BCb9
HS_OUT
VS_OUT
SCLK
SCLK
HS_OUT
VS_OUT
TP
1
VS
TP
TP
1
HS
TP
THS8200EVM - TESTPOINTS
A3_3V
TP
1
D1.8V
TP
TP
1
A3.3V
TP
TP
1
D3.3V
TP
D656[9..0]
DCLK
D656[9..0]
DCLK
12
34
56
78
910
11 12
13 14
15 16
H4
HEADER 8X2
FID
VSYNC
HSYNC
FID
VSYNC
HSYNC
D6560
D6561
D6562
D6563
D6564
D6565
D6566
D6567
D6568
D6569
4 6
REV 2.0
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123456
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Size
C
Date: 1-Sep-2005 Sheet of
File: C:\Documents and Settings\a0214685.ENT\Desktop\THS8200EVM_MODULE_REV1_2\THS8200EVM_MODULE_REV1_2.ddb
Drawn By:
R_PR
G_Y
13
2I2C
JMP3
8200_I2CA
R/PR
BNC_RA
G/Y
BNC_RA
B/PB
BNC_RA
C2
0.1uF
C5
0.1uF
C8
0.1uF
C3
0.1uF
C6
0.1uF
C9
0.1uF
THS8200 I2C ADDRESS SELECT
1-2 0x42 - Default
2-3 0x40
R9
10k
C4
0.1uF
C7
0.1uF
C10
0.1uF
C12
0.1uF
A3_3V
D3_3V
D1_8V
D3_3V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
P4
DB15F
HS_OUT
VS_OUT
THS8200EVM - THS8200
G_YOUT
C30
CAP_805
C32
CAP_805
C38
CAP_805
L3
L
L5
L
L8
L
G_Y
B_PBOUT
C31
CAP_805
C33
CAP_805
C34
CAP_805
L4
L
L7
L
L9
L
B_PB
R_PROUT
C35
CAP_805
C36
CAP_805
C37
CAP_805
L10
L
L11
L
L12
L
R_PR
B_PB
12
3
4
JP3
12
3
4
JP4
12
3
4
JP2
FID
SCL
SDA
GY[9..0]
SCLK
VSYNC
HSYNC
1
2
3
R11 2k
1
2
3
R12 2k
COMP2
FSADJ2
COMP1
FSADJ1
8200_I2CA
GND_IO 20
VDD_IO 19
AVDD 18
ARPr 17
AVSS 16
ABPb 15
AVDD 14
AGY 13
AVSS 12
AVDD 11
BCb9 21
BCb8 22
BCb7 23
BCb6 24
BCb5 25
BCb4 26
BCb3 27
BCb2 28
BCb1 29
BCb0 30
DVSS 31
COMP1 10
COMP2 9
FSADJ2 8
FSADJ1 7
VSS 6
GND_DLL 2
TEST 1
I2CA 5
VDD_DLL 4
CLK_IN 3
SCAN_EN
80 DVDD
79 DVSS
78 DO0
77 DO1
76 DO2
75 DO3
74 DO4
73 GND_IO
72 D1CLKO
71 VDD_IO
70
GY0
57 GY1
56
DO5
69 DO6
68 DO7
67 DO8
66 DO9
65 SCL
64 SDA
63 VS_OUT
62
DVDD_?
59 DVSS_?
58
HS_OUT
61
~RST
60
VDD_IO
46
FID
47
GY9
48
GY8
49
GY7
50
RCr1
41
RCr0
42
HS_IN
43
VD_IN
44
GND_IO
45
DVDD 32
RCr9 33
RCr8 34
RCr7 35
RCr6 36
RCr5 37
RCr4 38
RCr3 39
RCr2 40
GY2
55 GY3
54 GY4
53 GY5
52 GY6
51
PPAD 81
U2
D1_8V
G_YOUT
B_PBOUT
R_PROUT
SCLKIN
GY[9..0]
RESET
SDA
SCL
RESET
SCLK
VS_OUT
HS_OUT
C22
10uF
C23
1uF
C20
0.47uF
C21
0.47uF
GY0
GY1
GY2
GY3
GY4
GY5
GY6
GY7
R17 1.2k
R16 1.2k
GY8
GY9
RCr[9..0] RCr[9..0]
RCr0
RCr1
RCr2
RCr4
RCr5
RCr9
RCr8
RCr7
RCr6
RCr3
BCb[9..0] BCb[9..0]
BCb0
BCb1
BCb2
BCb4
BCb5
BCb9
BCb8
BCb7
BCb6
BCb3
FID
VSYNC
HSYNC
D1_8V
D3_3V
D1_8V
A3_3V
D3_3V
A3_3V
D1_8V
D3_3V
HS_OUT
VS_OUT
D6560
D6561
D6562
D656[9..0]
D6563
D6564
D6565
D6566
D6567
D6568
D6569
DCLK
D656[9..0]
DCLK
R22 0SCLKIN
R25
75
R24
75
R23
75
R15
0
A3_3V
5 6
REV 2.0
R26
10k
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SLEU098 – May 2008 TVP7002EVM Schematics 51
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‘5‘ TEXAS INSTRUMENTS
123456
A
B
C
D
6
5
4
3
2
1
D
C
B
A
Title
Number Revision
Size
C
Date: 1-Sep-2005 Sheet of
File: C:\Documents and Settings\a0214685.ENT\Desktop\THS8200EVM_MODULE_REV1_2\THS8200EVM_MODULE_REV1_2.ddb
Drawn By:
NC
1
VIN1A
2
VIN1B
3
/MR
4
/EN1
5
/EN2
6
/RESET
7
GND
8
VIN2A
9
VIN2B
10NC 11
VOUT2B 12
VOUT2A 13
VSENSE2/FB2 14
PG2 15
PG1 16
VSENSE1/FB1 17
VOUT1B 18
VOUT1A 19
NC 20
U4
TPS70251
C29
22uF
C39
22uF
R20 250k
R21250k
R19
250k
VOUT1 IS 3.3V 500mA
VOUT2 IS 1.8V 250mA
C19
0.1uF
C24
0.1uF
C16
0.1uF
C17
0.1uF
C26
22uF
C27
22uF
THS8200 POWER SUPPLY
F1 FUSE
2
3
1
P1
PJ-002BH
D1
ZENER
OPTIONAL 5V, 3.0A DC INPUT
SS26
MAIN SUPPLY FROM CONNECTOR
R18
330
POWER ON LED (+5V)
C28
22uF
C18
0.1uF
L1 A3_3V
D3_3V
D1_8V
D5V
D5V
D5V
1
2
3
H5
HEADER 3
THS8200EVM - POWER
L2
L6
C25
1uF
R10
100k
RESET
PB
RESET ON POWER UP
D3_3V
CONN_RESET
R8
0
Remove R8 to disable
RESET from Connector
RESET
RESET RESET
MAN_RESET
MAN_RESET
C11
47uF
6 6
REV 2.0
21
5V
LED
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TVP7002EVM Schematics52 SLEU098 – May 2008
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l TEXAS INSTRUMENTS
Appendix ASLEU098 – May 2008
Recommended PLL Settings
Table A-1. Recommended PLL Settings
PLL PLLDIV Output VCO CPPixel PLLDIVFrame Line Rate Divider [11:4] Divider Range CurrentStandard Resolution Rate [3:0] Reg Reg 03hRate (Hz) (kHz) (Total Reg 01h Reg 04h Reg 03h Reg 03h(MHz) 02h [7:4]pix/line) [7:0] [0] [7:6] [5:3]
ULow640 x 480 59.94 31.469 25.175 800 32h 00h 20h 0 100b(00b)
ULow640 x 480 72.809 37.861 31.5 832 34h 00h 20h 0 100b(00b)VGA
ULow640 x 480 75 37.5 31.5 840 34h 80h 20h 0 100b(00b)
640 x 480 85.008 43.269 36 832 34h 00h 60h 0 Low (01b) 100b
800 x 600 56.25 35.156 36 1024 40h 00h 58h 0 Low (01b) 011b
800 x 600 60.317 37.879 40 1056 42h 00h 58h 0 Low (01b) 011b
SVGA 800 x 600 72.188 48.077 50 1040 41h 00h 58h 0 Low (01b) 011b
800 x 600 75 46.875 49.5 1056 42h 00h 58h 0 Low (01b) 011b
800 x 600 85.061 53.674 56.25 1048 41h 80h 58h 0 Low (01b) 011b
1024 x 768 60.004 48.363 65 1344 54h 00h 58h 0 Low (01b) 011b
1024 x 768 70.069 56.476 75 1328 53h 00h A8h 0 Med (10b) 101bXGA
1024 x 768 75.029 60.023 78.75 1312 52h 00h A8h 0 Med (10b) 101b
1024 x 768 84.997 68.677 94.5 1376 56h 00h A0h 0 Med (10b) 100b
1280 x 768 59.995 47.396 68.25 1440 5Ah 00h 50h 0 Low (01b) 010b
1280 x 768 59.87 47.776 79.5 1664 68h 00h A0h 0 Med (10b) 100bWXGA (I)
1280 x 768 74.893 60.289 102.25 1696 6Ah 00h A0h 0 Med (10b) 100b
1280 x 768 84.837 68.633 117.5 1712 6Bh 00h A0h 0 Med (10b) 100b
1280 x
60.02 63.981 108 1688 69h 80h A0h 0 Med (10b) 100b1024
1280 xSXGA 75.025 79.976 135 1688 69h 80h E8h 0 High (11b) 101b1024
1280 x
85.024 91.146 157.5 1728 6Ch 00h E8h 0 High (11b) 101b1024
1400 x
59.948 64.744 101 1560 61h 80h A0h 0 Med (10b) 100b1050
1400 xSXGA+ 59.978 65.317 121.75 1864 74h 80h 98h 0 Med (10b) 011b1050
1400 x
74.867 82.278 156 1896 76h 80h E0h 0 High (11b) 100b1050
1440 x 900 59.901 55.469 88.75 1600 64h 00h A0h 0 Med (10b) 100b
1440 x 900 59.887 55.935 106.5 1904 77h 00h 98h 0 Med (10b) 011bWXGA (II)
1440 x 900 74.984 70.635 136.75 1936 79h 00h E0h 0 High (11b) 100b
1440 x 900 84.842 80.43 157 1952 7Ah 00h E0h 0 High (11b) 100b
1600 xUXGA 60 75 162 2160 87h 00h E0h 0 High (11b) 100b1200
SLEU098 – May 2008 Recommended PLL Settings 53
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Appendix A
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Table A-1. Recommended PLL Settings (continued)
PLL PLLDIV Output VCO CPPixel PLLDIVFrame Line Rate Divider [11:4] Divider Range CurrentStandard Resolution Rate [3:0] Reg Reg 03hRate (Hz) (kHz) (Total Reg 01h Reg 04h Reg 03h Reg 03h(MHz) 02h [7:4]pix/line) [7:0] [0] [7:6] [5:3]
ULow720 x 480i 29.97 15.734 13.5 858 35h A0h 18h 0 011b(00b)
ULow720 x 576i 25 15.625 13.5 864 36h 00h 18h 0 011b(00b)
ULow720 x 480p 59.94 31.469 27 858 35h A0h 18h 0 011b(00b)
ULow720 x 576p 50 31.25 27 864 36h 00h 18h 0 011b(00b)
1280 x
60 45 74.25 1650 67h 20h A0h 0 Med (10b) 100b720pVideo
1280 x
50 37.5 74.25 1980 7Bh C0h 98h 0 Med (10b) 011b720p
1920 x
60 33.75 74.25 2200 89h 80h 98h 0 Med (10b) 011b1080i
1920 x
50 28.125 74.25 2640 A5h 00h 90h 0 Med (10b) 010b1080i
1920 x
60 67.5 148.5 2200 89h 80h E0h 0 High (11b) 100b1080p
1920 x
50 56.25 148.5 2640 A5h 00h D8h 0 High (11b) 011b1080p
Recommended PLL Settings54 SLEU098 – May 2008
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l TEXAS INSTRUMENTS
Appendix BSLEU098 – May 2008
Embedded Sync Setups
Table B-1. Embedded Sync Setups
I
2
C Register SA 480i60 480p60 720p60 1080i60 1080p60 XGA60
Output Format 15h 47h 47h 47h 47h 47h 47h
AVID Start LSB 40h 91h 93h 47h 06h 43h 43h
AVID Start MSB 41h 00h 00h 01h 01h 01h 01h
AVID Stop LSB 42h 0Bh 0Dh 4Bh 8Ah 8Ah 07h
AVID Stop MSB 43h 00h 00h 06h 08h 08h 00h
VBLK F0 Offset 44h 01h 05h 06h 02h 06h 02h
VBLK F1 Offset 45h 01h 05h 06h 02h 06h 00h
VBLK F0 DUR 46h 26h 2Ah 1Eh 16h 2Dh 26h
VBLK F1 DUR 47h 26h 2Ah 1Eh 17h 2Dh 26h
F0 F-bit 48h 02h 00h 00h 00h 00h 00h
F1 F-bit 49h 01h 00h 00h 00h 00h 00h
Figure B-1. 720p60 Example, Total Line Length = 1650 Pixels
AVID Start = Delay Factor + tri-level sync width + back-porch = 27 + 300 = 327 (147h)
AVID Stop = AVID Start + Active Pixels +4 = 327 + 1280 +4 = 1611
AVID Stop = 1611 (64Bh)
The horizontal reference point is the leading edge of the negative sync tip. The delay factor is a TVP7002internal delay factor and can change slightly with SOG LPF settings. If AVID Stop exceeds the total linelength, then subtract the total line length from the AVID Stop sum. An additional four pixels must be addedto the active video interval.
SLEU098 – May 2008 Embedded Sync Setups 55
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Embedded Sync Setups56 SLEU098 – May 2008
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l TEXAS INSTRUMENTS
Appendix CSLEU098 – May 2008
Color Space Converter Coefficients
BEGIN_DATASET //
DATASET_NAME,"CSC RGB to BT.709 HDTV YCbCr "
WR_REG,TVP7000,0x01,0x18,0x11 // CSC Enabled
WR_REG,TVP7000,0x01,0x4A,0xE3
WR_REG,TVP7000,0x01,0x4B,0x16
WR_REG,TVP7000,0x01,0x4C,0x4F
WR_REG,TVP7000,0x01,0x4D,0x02
WR_REG,TVP7000,0x01,0x4E,0xCE
WR_REG,TVP7000,0x01,0x4F,0x06
WR_REG,TVP7000,0x01,0x50,0xAB
WR_REG,TVP7000,0x01,0x51,0xF3
WR_REG,TVP7000,0x01,0x52,0x00
WR_REG,TVP7000,0x01,0x53,0x10
WR_REG,TVP7000,0x01,0x54,0x55
WR_REG,TVP7000,0x01,0x55,0xFC
WR_REG,TVP7000,0x01,0x56,0x78
WR_REG,TVP7000,0x01,0x57,0xF1
WR_REG,TVP7000,0x01,0x58,0x88
WR_REG,TVP7000,0x01,0x59,0xFE
WR_REG,TVP7000,0x01,0x5a,0x00
WR_REG,TVP7000,0x01,0x5b,0x10
END_DATASET
//////////////////////////////////////////////////////////////////////////////////////////////////
//////////////
BEGIN_DATASET //
DATASET_NAME,"CSC RGB to BT.601 SDTV YCbCr "
WR_REG,TVP7000,0x01,0x18,0x11 // CSC Enabled
WR_REG,TVP7000,0x01,0x4A,0xC9
WR_REG,TVP7000,0x01,0x4B,0x12
WR_REG,TVP7000,0x01,0x4C,0xA6
WR_REG,TVP7000,0x01,0x4D,0x03
WR_REG,TVP7000,0x01,0x4E,0x91
WR_REG,TVP7000,0x01,0x4F,0x09
WR_REG,TVP7000,0x01,0x50,0x66
WR_REG,TVP7000,0x01,0x51,0xF5
WR_REG,TVP7000,0x01,0x52,0x00
WR_REG,TVP7000,0x01,0x53,0x10
WR_REG,TVP7000,0x01,0x54,0x9A
WR_REG,TVP7000,0x01,0x55,0xFA
WR_REG,TVP7000,0x01,0x56,0x9A
WR_REG,TVP7000,0x01,0x57,0xF2
WR_REG,TVP7000,0x01,0x58,0x66
WR_REG,TVP7000,0x01,0x59,0xFD
WR_REG,TVP7000,0x01,0x5a,0x00
WR_REG,TVP7000,0x01,0x5b,0x10
END_DATASET
//////////////////////////////////////////////////////////////////////////////////////////////////
///////////
SLEU098 – May 2008 Color Space Converter Coefficients 57
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Color Space Converter Coefficients58 SLEU098 – May 2008
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l TEXAS INSTRUMENTS
Appendix DSLEU098 – May 2008
Macrovision Support
Macrovision support is provided through use of the MAC_EN bit in I
2
C register 22h and the MacrovisionStripper Width setting in I
2
C register 34h. The Macrovision Stripper Width setting defines a window thatmasks undesired signals outside the HSYNC interval to avoid disturbance of the H-PLL. The stripperwindow is derived from REFCLK cycles, so the settings required depend on which REFCLK is used.
Table D-1. Recommended Reg 34h Macrovsion Stripper Width Settings(MAC_EN = 1)
REG 34h (Internal REFCLK REG 34h (External 27-MhzVideo Standard
Used) REFCLK Used)
480i and 576i 24h 83h
480p and 576p 12h 43h
720p 07h 12h
1080i 07h 13h
1080p 03h 09h
Note: Settings less than those recommenced above can result in clamp and ALC placementissues. The stripper width setting has no effect when MAC_EN is set to 0.
SLEU098 – May 2008 Macrovision™ Support 59
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TVP7002EVM