LV8726TA Datasheet by ON Semiconductor

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0N Semiconductor®
© Semiconductor Components Industries, LLC, 2015 1 Publication Order Number:
October 2015- Rev. 0 LV8726TA/D
LV8726TA
Stepper Motor Pre-Driver, PWM,
Constant-Current Control, Micro step
Overview
The LV8726 is a bipolar stepper motor driver with ultra-small micro step drive
capability. The device uses external dual H-bridges consisting of P and N
channel MOSFETs. The operation voltage range is from 9V to 55V, and it is
applicable to various industrial applications. Synchronous rectification control
is implemented for all H-bridges to minimize power dissipation during a
MOSFET switching.
The device implements constant-current control using PWM. The step advance
sequencer covers from half step to 1/128 micro step, and is driven by a clock
input.
The configuration registers can be programmed through an SPI serial interface.
To enhance energy efficiency further, the device can be put into a power saving
standby mode.
Features
H-bridge gate drivers
o For bipolar stepper motor
o Clockwise(CW) and Counter-clockwise(CCW) direction control
o Built-in step vector, selectable number of step resolutions from 2, 3, 4,
5, 6, 8, 10, 12, 16, 20, 32, 36, 50, 64, 100 and 128
o Constant-current control
o Synchronous rectification to reduce power dissipation
Single clock input to advance the excitation step
Low power 1μA(max) standby mode
Separate power supplies for control logic (3.3-5V) and motor drivers ( 9V –
55V)
SPI 8-bit 3-wire serial interface for system configuration
Input pins for standby and active mode
Built-in system protection features such as:
o Under-voltage
o Over-current
o Over-temperature
Typical Applications
Textile machines
Packing machines
Large printers
Engraving machines
Industrial products
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48-pin TQFP with exposed pad
7 mm x 7 mm
MARKING DIAGRAM
ORDERING INFORMATION
Ordering Code:
LV8726TA-NH
Package
TQFP48 EP
(Pb-Free / Halogen Free)
Shipping (Qty / packing)
1000 / Tape & Reel
XXXXXXXXXX
XXXXXXXXXX
AWLYYWWG
XXXXX = Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G= Pb−Free Package
1
† For information on tape and reel specifications, including part
orientation and tape sizes, please refer to our Tape and Reel
Packaging Specifications Brochure, BRD8011/D.
http://www.onsemi.com/pub_link/Collateral/BRD8011-D.PDF
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LV8726TA
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BLOCK DIAGRAM
Figure 1. Block Diagram
fiflfl flflflfl VLQZLSAW
LV8726TA
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3
APPLICATION CIRCUIT EXAMPLE
37
GB4
38
GB3
39
NC
40
GU4
41
GU3
42
NC
43
NC
44
GB2
45
GB1
46
NC
47
GU2
48
GU1
1
2NC
3OUT2
4OUT1
5RF1
6NC
7VM
8VREG2
9NC
10 NC
11 NC
12 NC
24
23
22
21
20
19
18
17
16
15
14
13
EMO
MO
SDO
VREF
FR
OE
RST
STEP
STB
SDATA
SCLK
ST
36
35
34
33
32
31
30
29
28
27
26
25
NC
OUT4
OUT3
RF2
NC
GND
VREG1
NC
NC
NC
VCC
NCNC
0.1uF 0.1uF
0.1Ω
47KΩ
0.1Ω
TR3 TR5 TR7
TR4
TR2 TR6 TR8
TR1
PGND PGND
PGND
SGND
SGND
Serial Input
47KΩ
100uF
1uF
Logic Input
48V
5V
100uF
0.1uF
PGND
* Optional diodes and damping resistors for each gate are connected
to control turn OFF time of P-N channel MOSFETS, if needed.
SFT1342SFT1342
0Ω0Ω0Ω0Ω
SFT1446SFT1446
100Ω100Ω
SFT1342SFT1342
SFT1446 SFT1446
100Ω100Ω
M
Figure 2. Application Circuit Example
r
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4
PIN ASSIGNMENT
37 GB4
38 GB3
39 NC
40 GU4
41 GU3
42 NC
43 NC
44 GB2
45 GB1
46 NC
47 GU2
48 GU1
1
2
NC
3
OUT2
4
OUT1
5
RF1
6
NC
7
VM
8
VREG2
9
NC
10
NC
11
NC
12
NC
24
23
22
21
20
19
18
17
16
15
14
13
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
OUT4
OUT3
RF2
NC
GND
VREG1
NC
NC
NC
VCC
NC
EMO
MO
SDO
VREF
FR
OE
RST
STEP
STB
SDATA
SCLK
ST
Figure 3. Pin Assignment
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5
PIN FUNCTION DISCRIPTION
Pin No. Pin Name Description
1 NC No connection
2 NC No connection
3 OUT2 OUT2 voltage detection pin
4 OUT1 OUT1 voltage detection pin
5 RF1 Channel 1 Output current detection pin
6 NC No connection
7 VM Motor power supply pin
8 VREG2 Internal regulator capacitor connection pin for high side FET drive
9 NC No connection
10 NC No connection
11 NC No connection
12 NC No connection
13 ST Chip enable pin.
14 SCLK Serial data transfer clock input
15 SDATA Serial data input
16 STB Serial data latch pulse input
17 STEP Step clock signal input pin
18 RST Reset signal input pin
19 OE Output enable signal input pin
20 FR Direction control signal input pin
21 VREF Constant-current control reference voltage input pin.
22 SDO STEP detection output pin
23 MO Position detecting monitor pin
24 EMO Unusual condition warning output pins
25 VCC Logic power supply pin
26 NC No connection
27 NC No connection
28 NC No connection
29 VREG1 Internal regulator capacitor connection pin for low side FET drive
30 GND GND pin
31 NC No connection
32 RF2 Channel 2 Output current detection pin
33 OUT3 OUT3 voltage detection pin
34 OUT4 OUT4 voltage detection pin
35 NC No connection
36 NC No connection
37 GB4 Output terminal for low side gate drive 4
38 GB3 Output terminal for low side gate drive 3
39 NC No connection
40 GU4 Output terminal for high side gate drive 4
41 GU3 Output terminal for high side gate drive 3
42 NC No connection
43 NC No connection
44 GB2 Output terminal for low side gate drive 2
45 GB1 Output terminal for low side gate drive 1
46 NC No connection
47 GU2 Output terminal for high side gate drive 2
48 GU1 Output terminal for high side gate drive 1
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PIN EQUIVALENT CIRCUITS
Pin No. Pin Name Equivalent Circuit
13 ST
GND
14
15
16
17
18
19
20
SCLK
SDATA
STB
STEP
RST
OE
FR
VCC
100kΩ
GND
10kΩ
21 VREF
VCC
GND
500Ω
Continued on next page.
GNDC
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Continued from preceding page.
Pin No. Pin Name Equivalent Circuit
22
23
24
SDO
MO
EMO
200kΩ
29 VREG1
GND
VM
142kΩ20kΩ
2kΩ
8 VREG2
GND
VM
100kΩ102kΩ
2kΩ
Continued on next page.
VMO a: O at VREGZCL VREG1O a: O ——: GNDC
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Continued from preceding page.
Pin No. Pin Name Equivalent Circuit
5
32
RF1
RF2
VCC
GND
500Ω
40
41
47
48
GU4
GU3
GU2
GU1
37
38
44
45
GB4
GB3
GB2
GB1
3
4
33
34
OUT2
OUT1
OUT3
OUT4
VM
GND
60KΩ
60KΩ
nug/Iwww onsemImm/Eub Imk/CoualeraI/SOLDERRM PDF
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MAXIMUM RATINGS (Note 1)
Parameter Symbol Value Unit
Motor Supply Voltage (VM) VM 60 V
Logic Supply Voltage (VCC) VCC 6 V
Logic Input Voltage (ST, SCLK, SDATA, STB, STEP, RST, OE, FR) VIN 6 V
Output current (GU1, GU2, GU3, GU4, GB1, GB2, GB3, GB4) IO 50 mA
Reference input voltage (VREF) VREF 6 C
Allowable Power Dissipation (Note 2) Pd 3.35 W
Storage Temperature Tstg 55 to 150 ºC
Junction Temperature TJ 150 ºC
Moisture Sensitivity Level (MSL) (Note 3) MSL 3 -
Lead Temperature Soldering Pb-Free Versions (10sec or less) (Note 4) TSLD 260 ºC
ESD Human Body Model: HBM (Note 5) ESDHBM ±2000 V
ESD Charged Device Model: CDM (Note 6) ESDCDM ±500 V
1. Stresses exceeding those listed in the Absolute Maximum Rating table may damage the device. If any of these limits are exceeded,
device functionality should not be assumed, damage may occur and reliability may be affected.
2. Specified circuit board: 90mm 90mm 1.6mm, glass epoxy 2-layer board, with backside mounting. It has 1 oz copper traces on top and
bottom of the board.
3. Moisture Sensitivity Level (MSL): 3 per IPC/JEDEC standard: J-STD-020A
4. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
http://www.onsemi.com/pub_link/Collateral/SOLDERRM-D.PDF
5. ESD Human Body Model is based on JEDEC standard: JESD22-A114
6. ESD Charge Device Model is based on JEDEC standard: JESD22-C101
THERMAL CHARACTERISTICS
Parameter Symbol Value Unit
Thermal Resistance, Junction-to-Ambient (Note 2) RθJA 37.3 ºC/W
Thermal Resistance, Junction-to-Ambient (Note 7) 56.8 ºC/W
Thermal Resistance, Junction-to-Case (Top) (Note 2) RΨJT 4.8 ºC/W
Thermal Resistance, Junction-to-Case (Top) (Note 7) 14.9 ºC/W
7. Specified circuit board: 90mm 90mm1.6mm, glass epoxy 2-layer board, without backside mounting. It has 1 oz copper traces on top
and bottom of the board.
Figure 4. Power Dissipation vs Ambient Temperature Characteristic
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
-20 0 20 40 60 80 100
Allowable power dissipation, Pdmax - W
Ambient temperature, Ta - C
3.35
1.74
2-layer circuit board
with backside mounting
2-layer circuit board
with no backside mounting
1.10
2.20
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RECOMMENDED OPERATING RANGES (Note 8)
Parameter Symbol Ratings Unit
Motor Supply Voltage Range (VM) VM 9 to 55 V
Logic Supply Voltage Range (VCC) VCC 2.7 to 5.5 V
Logic Input Voltage Range (ST, SCLK, SDATA, STB, STEP, RST, OE, FR) VIN 0 to VCC V
VREF Input Voltage Range (3.8V≤ VCC ≤5.5V) VREF 0 to 2.0 V
VREF Input Voltage Range (2.7V≤ VCC ≤3.8V) 0 to VCC – 1.8 V
Ambient Temperature TA 40 to 85 ºC
8. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses
beyond the Recommended Operating Ranges limits may affect device reliability.
ELECTRICAL CHARACTERISTICS
TA=25ºC, VM = 48V, VCC=5V, VREF=1.5V unless otherwise noted. (Note 9)
Parameter Symbol Condition Min Typ Max Unit
Standby Mode Current
IMstn ST=”L”, No load 1 μA
ICCstn ST=”L”, No load 1 μA
Supply Current
IM ST=”H”, OE=”L”,RST=”L”, No load 1.6 2.3 mA
ICC ST=”H”, OE=”L”,RST=”L”, No load 1.7 2.3 mA
Thermal Shutdown Temperature TSD Guaranteed by design 150 180 210 ˚C
Thermal hysteresis ∆TSD Guaranteed by design 40 ˚C
Under-voltage Monitor
VCC under-voltage threshold
Vthvc VCC falling 2.3 2.45 V
Vrevc VCC rising 2.5 2.7 V
VM under-voltage threshold
Vthvm VM falling 7.6 8.4 V
Vrevm VM rising 7.85 8.7 V
Regulator
REG10 Output Voltage VREG1 9.4 10 10.6 V
VM-10V Output Voltage VREG2 37 38 39 V
MOSFET Drivers
High Side Output On Resistance
RonH1 GU1,GU2,GU3,GU4-source
Io=-10mA 20 32 Ω
RonH2 GU1,GU2,GU3,GU4-sink
Io=10mA 25 40 Ω
Low Side Output On Resistance
RonL1 GB1,GB2,GB3,GB4-source side
Io=-10mA 20 32 Ω
RonL2 GB1,GB2,GB3,GB4-sink side
Io=10mA 25 40 Ω
Logic Inputs
Logic Input Current
IINL ST,SCLK,SDATA,STB,STEP,RST,OE,FR
VIN=0.8V 4 8 12 μA
IINH ST,SCLK,SDATA,STB,STEP,RST,OE,FR
VIN=5V 30 50 70 μA
Logic Input Voltage
High VINH
ST,SCLK,SDATA,STB,STEP,RST,OE,FR
2.0 5.5 V
Low VINL 0 0.8 V
System Monitoring
Step signal OFF detection time
TSDO0 No rising edge in STEP pin
Register D[7]=’0’, D[1:0]=’01’ 0.39 0.52 0.65 S
TSDO1 No rising edge in STEP pin
Register D[7]=’1’, D[1:0]=’01’ 0.78 1.04 1.3 S
Continued on next page.
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Continued from preceding page.
Parameter Symbol Condition Min Typ Max Unit
PWM Current Control
VREF Pin Input Current IREF V
REF=1.5V 0.5 0 μA
Current setting comparator threshold
voltage
VREF000 Register D[4:2]=’000’, D[1:0]=’01’ 0.291 0.3 0.309 V
VREF001 Register D[4:2]=’001’, D[1:0]=’01’ 0.261 0.27 0.279 V
VREF010 Register D[4:2]=’010’, D[1:0]=’01’ 0.231 0.24 0.248 V
VREF011 Register D[4:2]=’011’, D[1:0]=’01’ 0.201 0.21 0.218 V
VREF100 Register D[4:2]=’100’, D[1:0]=’01’ 0.172 0.18 0.188 V
VREF101 Register D[4:2]=’101’, D[1:0]=’01’ 0.142 0.15 0.158 V
VREF110 Register D[4:2]=’110’, D[1:0]=’01’ 0.112 0.12 0.128 V
VREF111 Register D[4:2]=’111’, D[1:0]=’01’ 0.082 0.09 0.098 V
PWM (Chopping) Period
Fchop1 Register D[7:6]=’00’, D[1:0]=’10’ 6 8 10 μs
Fchop2 Register D[7:6]=’01’, D[1:0]=’10’ 12 16 20 μs
Fchop3 Register D[7:6]=’10’, D[1:0]=’10’ 18 24 30 μs
Fchop4 Register D[7:6]=’11’, D[1:0]=’10’ 24 32 40 μs
Open Drain Outputs
SDO pin saturation voltage Vsatsdo I
sod=1mA 400 mV
MO pin saturation voltage Vsatmo I
mo=1mA 400 mV
EMO pin saturation voltage Vsatemo I
emo=1mA 400 mV
Serial Data Interface (Note 10)
SCLK “H” Pulse Width Tckh 0.125 μs
SCLK “L” Pulse Width Tckl 0.125 μs
SCLK start setup time Tsup1 STB=Low -> SCLK rising edge 0.125 μs
STB setup time Tsup2 SCLK rising edge -> STB rising edge 0.125 μs
Serial Packet STB Interval Tstbw 0.125 μs
SDATA setup time Tds 0.125 μs
SDATA hold time Tdh 0.125 μs
SCLK Frequency Fclk 4 MHz
9. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted.
Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
10. See Figure 5 for the definition of the timing
Figure 5. Serial Interface (SPI) Timing Chart
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TYPICAL CHARACTERISTICS
Figure 6. Standby Mode Current
vs VM Voltage
Figure 7. Standby Mode Current
vs VCC Voltage
Figure 8. Current Consumption(IM)
vs VM Voltage
Figure 10. Current Consumption (ICC)
vs VCC Voltage
Figure 9. Logic H/L-Level Input Voltage
(except ST pin) vs VCC Voltage
Figure 11. ST pin Input Threshold Voltage
vs VCC Voltage
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0 102030405060
IMstn (uA)
VM (V)
Standby mode current - VM
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0123456
ICCstn (uA)
VCC (V)
Standby mode current - VCC
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
0 102030405060
IM (mA)
VM (V)
Current Consumption of VM
0
0.5
1
1.5
2
2.5
0123456
ICC (mA)
VCC (V)
Crrent Consumption of VCC
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
22.533.544.555.56
H-level (V)
VCC(V)
Logic Level Input Voltage (OE pin)
H-level L-Level
* Logic inputs are hysteresis type and
devide the thethreshold level at VCC rising 4V
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2 2.5 3 3.5 4 4.5 5 5.5 6
threshold voltage(V)
VCC(V)
Input Threshold Voltage (ST pin against VCC)
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TYPICAL CHARACTERISTICS (CONTINUED)
Figure 12. Logic Input Current
vs Input Voltage
Figure 13. STEP signal OFF detection time
vs VCC Voltage
Figure 14. VCC Under-voltage Protection
Threshold Voltage vs VCC Voltage
Figure 15. VM Under-voltage Protection
Threshold Voltage vs VM Voltage
Figure 16. VREG1 Output Voltage
vs VREG1 Load Current
Figure 17. VREG2 Output Voltage
vs VREG2 Load Current
0
10
20
30
40
50
60
70
0123456
IIN (uA)
VIN (V)
Logic pin input current (VM=48V VCC=6V)
ST SCLK SDATA STB
STEP RST OE FR
0
0.2
0.4
0.6
0.8
1
1.2
1.4
23456
Step signal OFF detection time (s)
VCC (V)
STEP signal OFF detection time
VM=48V setting mode=1.04s
-2
0
2
4
6
8
10
12
2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3
GB (V)
VCC (V)
VCC Under Voltage Protection
Threshold Voltage
-2
-1
0
1
2
3
4
5
6
7
8
9
7.5 7.6 7.7 7.8 7.9 8
VREG1 (V)
VM (V)
VM Under Voltage Protection
Threshold Voltage
0
2
4
6
8
10
12
-100-80-60-40-200
VREG1 (V)
Iload (mA)
VREG1 load regulation
VM=48V VCC=5.0V
30
32
34
36
38
40
42
44
46
48
50
0 10203040506070
VREG2 (V)
Iload (mA)
VREG2 load regulation
VM=48V VCC=5.0V
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TYPICAL CHARACTERISTICS (CONTINUED)
Figure 18. VREF pin Input Current (IREF)
vs VREF Voltage
Figure 19. SDO pin Saturation Voltage
vs SDO Load current
Figure 20. MO pin Saturation Voltage
vs MO Load Current
Figure 22. PWM (Chopping) Period
vs VCC Voltage
Figure 21. EMO pin Saturation Voltage
vs EMO Load Current
-25
-20
-15
-10
-5
0
012345
IREF (nA)
VREF (V)
VREF input current
VM=48 VCC=5.0V
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0 5 10 15 20 25 30
Saturation voltage (V)
Load currrent (mA)
SDO pin Saturation Voltage
VM=48V VCC=5V
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0 5 10 15 20 25 30
Saturation voltage (V)
Load current (mA)
MO pinl Saturation Voltage
VM=48V VCC=5V
0
5
10
15
20
25
30
35
40
45
23456
Chopping period (us)
VCC (V)
Chopping period
VM=48V VREF=1.5V setting mode=32us
0
0.2
0.4
0.6
0.8
1
1.2
0 5 10 15 20 25 30
Saturation voltage (V)
Load current (mA)
EMO pin Saturation Voltage
VM=48V VCC=5V
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FUNCTIONAL DESCRIPTION
Power Supply Input (VM, VCC)
The LV8726 has two power supply pins, VM and VCC.
VM is the motor power supply rail which is also
connected externally to the power MOSFETs. VCC
supplies power to internal circuits. It is highly
recommended to provide a decoupling capacitor of
100µF for each position close to the VM pin and VM
line of external MOSFETs on the application board.
Driver Pins (GUx, GBx and OUTx)
The pins GUx are the high side P-MOSFET gate driver
outputs, and GBx are the low side N-MOSFET gate
driver outputs. The pins OUTx are the voltage sense
inputs used for the over-current protection function to
measure the P-MOSFET voltage between drain and
source. The channel pairing is shown in the following
table.
Table 1: External MOSFETs Connection
Channel P-MOS
gate
P-MOS
drain
N-MOS
gate Motor coil
1 GU1 OUT1 GB1 1A
GU2 OUT2 GB2 1B
2 GU3 OUT3 GB3 2A
GU4 OUT4 GB4 2B
Refer to the APPLICATION CIRCUIT EXAMPLE of
page 3.
Internal Voltage Regulator for N-MOSFETs (VREG1)
This 10V regulator provides required biasing for low
side N-MOSFET gate drivers. The output of this
regulator is connected to pin VREG1. Do not use
VREG1 to drive any external load. It is recommended to
connect a 0.1µF decoupling capacitor between VREG1
pin and GND.
Internal Voltage Regulator for P-MOSFETs (VREG2)
This regulator provides required biasing for high side
P-MOSFET gate drivers at 10V below VM. The output
of this regulator is connected to pin VREG2. Do not use
VREG2 to drive any external load. It is recommended to
connect a 0.1µF decoupling capacitor between VREG2
and VM.
Standby Mode (ST)
When pin ST is pulled down to GND, the device enters
standby mode: all power MOSFETs are turned off, and,
all logic as well as the step counter are reset.
When ST pin is pulled to High, the device enters active
mode. The motor is excited at the home position. A
rising edge at the STEP pin will advance the motor
(which direction). Refer to Table 5 of page 16 for the
home position.
Table 2: Operating Mode control by ST pin
ST Operating mode Internal regulator
L Standby Standby
H Active Active
Initialize Step Position Pin (RST)
While pin RST is set High, the home position is excited.
After RST is released (Low), the first rising edge of
STEP pulse advances the step. The position monitor
output (MO pin) indicates that the output state is in the
home position by outputting Low level.
Figure 23. Initialize Step Position (RST)
Output Enable Pin (OE)
While OE pin is High, the output power MOSFETs are
turned off. During the output disabled, the internal step
sequencer keeps operation, advancing the step position
based on the clock at STEP pin.
0%
2ch output
1ch output
MO
STEP
Power save mode
Output is high-impeda nce
OE
Figure 24. Example of Output Enable (OE)
0%
2ch output
1ch output
MO
STEP
RST RESET
Home position
in Ha Senin
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Summary of System Mode Control (ST, OE, RST)
The following table shows the summary of the system
mode control function with ST, OE and RST pins.
Table 3: System Mode Control
ST OE RST Output Step position
L * * High
impedance -
H H H High
impedance Home position
H H L High
impedance
Based on
STEP signal
H L H Active Home position
H L L Active Based on
STEP signal
Step Clock Signal Input Pin (STEP)
A rising edge of the step clock signal at STEP pin
advances the step position of the stepper motor by
advancing the electrical angle of the excitation current
for the motor coils. The number of steps for 90 degree of
an electrical cycle (i.e. resolution) is determined by the
register bits which are accessible through the serial
interface.
Table 4: Step Position Control by STEP pin
ST STEP Operating mode
L * Standby mode
H Advancing step position
H step position is kept
Table 5: Micro Step Resolution Setting
Bit setting
(D1=0, D0=0) Micro step
resolution:
STEPMODE
Home position
1ch
current
2ch
Current
D5 D4 D3 D2
0 0 0 0 1/2 100% 0%
0 0 0 1 1/4 100% 0%
0 0 1 0 1/8 100% 0%
0 0 1 1 1/16 100% 0%
0 1 0 0 1/32 100% 0%
0 1 0 1 1/64 100% 0%
0 1 1 0 1/128 100% 0%
0 1 1 1 1/3 100% 0%
1 0 0 0 1/6 100% 0%
1 0 0 1 1/12 100% 0%
1 0 1 0 1/36 100% 0%
1 0 1 1 1/5 100% 0%
1 1 0 0 1/10 100% 0%
1 1 0 1 1/20 100% 0%
1 1 1 0 1/50 100% 0%
1 1 1 1 1/100 100% 0%
Rotational Direction Control Pin (FR)
FR controls the progression of the electrical angle of the
motor. When FR is Low, the direction is clockwise, and
when FR is High, direction is counter-clockwise.
Table 6: Direction Control by FR pin
FR Operating mode
Low Clockwise (CW)
High Counter-clockwise (CCW)
Figure 25 shows an example of the direction change
with FR pin.
Figure 25. Example of Direction Reversal
Position Monitor Output Pin (MO)
The active low, open drain pin MO indicates the home
position of the motor. An example of pin MO waveform
is as shown Figure 44 and Figure 45 of page 33 and 34.
FR CW mode CW modeCCW mode
STEP
Excitation position
1ch output
2ch output
(1) (2) (3) (4) (5) (6) (5) (4) (3) (4) (5)
5X0.1 fl
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Current Control Setting (VREF, RF1, RF2)
The LV8726 implements a current sense mechanism for
each channel using external shunt resistors.
To control a coil current, a RFx pin is provided for each
channel. A resistor connected at this RFx pin defines the
current gain of the coil current.
The resistive voltage generated by the coil current is
sensed by the RFx pin and the output duty cycle is
adjusted so that the RFx voltage level is equal to the
internal reference voltage (Equation 1). The reference
voltage is determined by the input voltage level at
VREF pin and the programmable attenuator. For this
VREF pin, it is required to provide an external constant
voltage source circuit. Refer to RECOMMENDED
OPERATING RANGES of page 10 for VREF range.
Table 7: VREF Attenuation Ratio Setting
Bit setting
(D1=0, D0=1) VREF (Reference voltage)
attenuation ratio: VREFATT
D4 D3 D2
0 0 0 100%
0 0 1 90%
0 1 0 80%
0 1 1 70%
1 0 0 60%
1 0 1 50%
1 1 0 40%
1 1 1 30%
The output current calculation method for using of
attenuation function of the VREF input voltage is as
shown in Equation 1.
Equation 2 is utilized to calculate the coil peak current,
IOUT.
 ∙ 
5∙
 …………1
  ∙

5∙ ………2
Where,
IOUT : Coil current [A]
RRFx : Resistor between RFx and GND [Ω]
VREF : Input voltage at the VREF pin [V]
ATTRATIO : Attenuator Ratio for the VREF pin
For example, in case of
 0.1Ω]
 1.5[V]
=1.0 (100%)
The coil current is
 1.51.0
50.1  3.0A
The LV8726 provides the built-in current vector
generator. The current ratio between channel 1 and 2
are preset based on cosine and sine element
individually.
PWM Constant-Current Control Ratio
The LV8726 implements constant current control drive
by applying a PWM to pins GUx and GBx.
When a coil current reaches the set target value, the
constant current control mechanism gets activated and
performs a repetitive sequence of Charge and Decay
operations as shown Figure 30-32 of page 22 and 23.
The target value is generated based on the step clock
pulse number. The angle of one step θ is
90
°∙………3
Where,
θ : Angle of micro step [deg]
S : Micro step (1/2, … 1/128)
The n-th current ratio can be represented by

%
 ∙100………4
The n-th current value can be represented by


 
………5
Where,
n : the position number of STEP from 0 to 1/S
For example, in case of
  1/128
32
The θ32 is
32  90°∙32
128 22.5°
Each current ratio is
32
22.5°∙100  92[%]
32
22.5°∙100  38[%]
Equation 4 represents the theoretical calculation. The
actual current ratio between the channel 1 and 2 is the
preset value as shown in Table 10-12 of page 28, 30 and
32. In case of 1/128 micro step case, the preset values
are plotted in Figure 41 of page 29. The current
waveforms for some micro step settings are illustrated
in Figure 44-1., Figure 45-1, Figure 46-1.
Ro|allon } He‘d } Rolallun STEPmpuI flflflfl hflflfl \ x H Tsuo \ SDO ompm \ \ OFF 1 Law 1 OFF 4’x‘7 ’x‘ \
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Output Pin for STEP Input Monitoring (SDO)
The step clock signal at pin STEP is monitored by an
internal counter. When the interval time of the rising
edge is longer than timeout criteria, open drain pin SDO
goes Low. The timeout period is selectable by the
register bits shown in the following table. The example
of detection timing is illustrated in Figure 26.
Table 8: STEP Signal OFF Detection Time Setting
Bit setting
(D1=0, D0=1) STEP signal OFF detection time:
TSDO
D7
0 0.52sec
1 1.04sec
Figure 26. Example of SDO Timing
SDO Output for Current Reduction
To avoid to applying high current to a motor coil for
long term at one step position, the SDO output may be
used to reduce the reference current. SDO is asserted
when the step clock interval is longer than TSDO. With
the circuit is shown in Figure 27. VREF voltage can be
reduced in case of an SDO assertion.
SDO
VREF
V1
R1
R2R3
Figure 27. VREF Voltage Attenuation Circuit
Fault Detection Output (EMO)
When a fault event is detected, open drain pin EMO
goes Low. The fault event is selectable by register from
the following four conditions.
Table 9: Fault Detection Output Setting
Bit setting
(D1=0, D0=0) Fault detection output:
EMOSEL
D7 D6
0 0 Over-current detection
0 1 None
1 0 VM low voltage < 7.6V (typ)
1 1 Thermal Shutdown
The all fault protection functions always work
regardless of the EMO output selection.
Serial Interface (ST, SDATA, SCLK, STB)
The LV8726 has registers to program settings and
parameters which are accessed through the serial
interface. It consists of the following three pins:
1. STB: When STB is Low, SDATA is input at
the rising edge of SCLK. SCLK signal is not
accepted when STB is High. The transmitted
data is latched at the rising edge of STB.
2. SDATA: LSB first 8-bit word. Its direction is
from external processor to the device. The
written data cannot be read back.
3. SCLK: Serial clock. The device fetches each
data bit at the rising edge of the clock.
The settings of ‘Micro step resolution’ and ‘Decay
mode’ are taking effect at the first rising edge of STEP
after a register write. Other settings are active
immediately after a register change.
When more than eight bits of data were received, the
latest eight bits are considered effective data. During
standby mode (ST=Low), the registers cannot be
accessed and all logic is reset.
Data latch timing
SCLK
SDATA
STB
ST
D0 D1 D2 D3 D4 D5 D6 D7
Figure 28. Serial Interface Timing Chart
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Register Map
The following Figure shows the register map. The two lowest bits are assigned for selecting one of four addresses.
D7 D6 D5 D4 D3 D2 D1 D0
Address
00
01
10
11
EMOSEL STEPMODE
ADDR1 ADDR0
TSDO DECAY VREFATT
TPWM TOFF TBLANK
NA NA NA NA OCM OCE
Figure 29. Register Map
ADDR D[1:0]: 00 (Address 00)
D7 D6 D5 D4 D3 D2 D1 D0
EMOSEL STEPMODE 0 0
STEPMODE D[5:2]
Step mode setting
D5 D4 D3 D2
Micro step resolution
(Step mode)
0 0 0 0 1/2
0 0 0 1 1/4
0 0 1 0 1/8
0 0 1 1 1/16
0 1 0 0 1/32
0 1 0 1 1/64
0 1 1 0 1/128
0 1 1 1 1/3
1 0 0 0 1/6
1 0 0 1 1/12
1 0 1 0 1/36
1 0 1 1 1/5
1 1 0 0 1/10
1 1 0 1 1/20
1 1 1 0 1/50
1 1 1 1 1/100
EMOSEL D[7:6]
Fault detection output select for EMO output
D7 D6 Fault detection output
0 0 Over-current detection
0 1 None
1 0 VM low voltage < 7.6V (typ)
1 1 Thermal shutdown
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ADDR D[1:0] : 01 (Address 01)
D7 D6 D5 D4 D3 D2 D1 D0
TSDO DECAY VREFATT 0 1
VREFATT D[4:2]
Attenuator ratio for VREF
D4 D3 D2
VREF attenuation ratio
0 0 0 100%
0 0 1 90%
0 1 0 80%
0 1 1 70%
1 0 0 60%
1 0 1 50%
1 1 0 40%
1 1 1 30%
DECAY D[6:5]
Selection of Decay mode:
In the case of 25%FAST at Mixed decay, 25% of the PWM period operates with Fast decay mode.
In the case of 50%FAST at Mixed decay, 50% of the PWM period operates with Fast decay mode.
D6 D5 Decay mode: DECAY
0 0 Mixed (25% Fast)
0 1 Mixed (50% Fast)
1 0 Slow
1 1 Fast
TSDO D[7]
STEP signal OFF detection time
D7 Step signal OFF detection time: TSDO
0 0.52sec
1 1.04sec
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ADDR D[1:0]: 10 (Address 10)
D7 D6 D5 D4 D3 D2 D1 D0
TPWM TOFF TBLANK 1 0
TBLANK D[3:2]
Blanking time: During this period, the mode is not switched from Charge to Decay even if the comparator detects the coil
current higher than the target current.
D3 D2 Blanking time
0 0 0.5µs
0 1 1.0µs
1 0 2.0µs
1 1 4.0µs
TOFF D[5:4]
Time for turning off the MOSFETs to avoid shoot through current
D5 D4 Through current protector OFF time
0 0 0.5µs
0 1 1.0µs
1 0 2.0µs
1 1 4.0µs
TPWM D[7:6]
PWM (Chopping) period
D7 D6 PWM (Chopping) period
0 0 8µs
0 1 16µs
1 0 24µs
1 1 32µs
ADDR D[1:0]: 11 (Address 11)
D7 D6 D5 D4 D3 D2 D1 D0
NA NA NA NA OCM OCE 1 1
OCE D[2]
Turn on/off the over-current protection function
D2 Over-current protection
0 ON
1 OFF
OCM D[3]
Over-current protection mode
D3 Over-current protection mode
0 Latch type
1 Auto reset type
The output is turned off at the over-current detection. In
case of the latch type, the outputs are turned off until the
standby pin ST is set Low when over-current is detected
with second detection at 256µs after the first detection.
Refer to Figure 47 of page 36 for a timing chart of latch
type. In case of the auto reset type, the output is turned on
with 2ms interval.
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Current Decay Mode Sequencing
LV8726 provides four selectable decay modes in one
PWM period:
1. Mixed decay mode
(Ratio is register programmable)
2. Slow decay mode
3. Fast decay mode
The description of the mixed decay sequence covers all
operation modes in detail. For slow and fast decay
operation only, the selected mode (slow, fast) covers the
entire decay period. Figures 30-32 show the sequence of
events in detail.
Mixed Decay Sequence
In Mixed Decay operation the following charge-discharge
sequence of three steps is applied assuming a current
direction from “A” to “B”. Refer to Figure 33 and Figure
34 of page 24 for the timing chart of PWM based
constant-current by Mixed decay:
1. During Charge operation the voltage VM is applied to
the “A” side of the coil until the coil current exceeds
the target. In case the current has already exceeded the
target value at the end of blanking time, the Charge
operation is directly changed over to Slow decay
operation (3).
2. Next the device activates Slow decay until 50% (or
75%) of the PWM period depending on register setting.
The slow decay shorts the coil to make the circulation
current decrease slowly as seen in (3) event in Figure
30
3. For the remaining PWM period Fast decay is applied
by reversing the voltage across the.
The operation is changed to Charge again from Fast decay.
During transition from the upper MOSFET to the lower
MOSFET of the same leg a programmable dead time
period avoids turning on both MOSFETs at the same time.
During this dead time, the coil current flows through the
body diode of the MOSFET as seen in (2), (4) and (6)
events in Figure 30. Dead time is determined by the
register bits through the serial interface.
For Slow decay and Fast decay mode, the coil current
flows through the body diode as shown in (2) event in
Figure 31 and Figure 32 same as Mixed decay.
AB
RF
VM
ON
ON
OFF
OFF
RF
VM
OFF
ON
OFF
OFF
RF
VM
OFF
ON
OFF
ON
1. CHARGE 2. 3. SLOW
GU1 GU2
GB1 GB2
Current pathway
AB
GU1 GU2
GB1 GB2
AB
GU1 GU2
GB1 GB2
AB
RF
VM
OFF
OFF
OFF
ON
RF
VM
OFF
OFF
ON
ON
RF
VM
OFF
OFF
OFF
OFF
4. 5. FAST 6.
GU1
GB1
GU2
GB2
AB
GU1
GB1
GU2
GB2
AB
GU1
GB1
GU2
GB2
Figure 30. Mixed Decay Sequence
Charge increases
current.
Transition from Charge to
Slow decay
Current regeneration by
Slow decay
Transition from Slow
decay to Fast decay
Current regeneration by
Fast decay
Transition from Fast decay
to Charge
1. Charge leem pamway VM OFF saw : 1. Charge VM Cuuem Damway ’ > OFF saw 0N GB? ON GE? OFF Gm OFF 651 2. w or; or; GUWAt} suz A 5 OFF or; saw»? 652 r» RF OFF Gm 3. Slow decay VM c 3. Fasl decay VM OFF 652 fliw
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Figure 31. Slow Decay Sequence
Figure 32. Fast Decay Sequence
Charge increases
current.
Transition from Charge to
Slow decay or from Slow
decay to Charge
Current regeneration by
Slow decay
Charge increases
current.
Transition from Charge to
Fast decay or from Fast
decay to Charge
Current regeneration by
Fast decay
—>S‘
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Timing Chart of PWM Constant-Current Control
When the current control mode is switched from Decay
mode to Charge mode, a noise in the current sense
resistance occurs by a recovery current, and it may
erroneously detect the voltage of the sense pin. Blanking
time is provided in order to prevent this erroneous
detection. During this period, the mode is not switched
from Charge to Decay even if the comparator detects the
coil current higher than the target current.
Mixed decay current control
Coil current
Fchop
Set current
CHARGE
STEP
Set current
SLOW FAST (50%) Current mode
CHARGE SLOW FAST (50%)
Blanking Time
PWM(Chopping) period
Figure 33. Mixed Decay (50%FAST) Rising Slope
Coil current
Fchop
Set current
CHARGE
STEP
Set current
SLOW FAST (50%)
Current mode Blanking Time FAST SLOW
CHARGE
Blanking Time
PWM(Chopping) period
FAST (50%)
Figure 34. Mixed Decay (50%FAST) Falling Slope
When a coil current reached the set current, external
MOSFETs are repeated Charge mode-> Slow decay
mode-> Fast decay mode according to PWM period. The
coil current is controlled constant-current by repeating
three modes.
As for the Fast period, it is selectable in 50% and 25% of
PWM period by serial interface.
The coil current (ICOIL) and set current (IREF) are
compared in blanking time.
When ICOIL < IREF:
The Charge mode is continued until ICOIL IREF. If
ICOIL reaches IREF, the mode is switched to Slow decay
mode, and then is changed Fast decay mode.
When ICOIL > IREF:
The Fast decay mode begins. The coil current is
attenuated in the Fast decay mode till one PWM period is
over.
<—>
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Slow decay current control
Coil current
Fchop
Set current
CHARGE
STEP
Set current
SLOW Current mode
CHARGE SLOW
Blanking Time
PWM(Chopping) period
Figure 35. Slow Decay Rising Slope
Coil curre nt
Fchop
Set current
CHARGE
STEP
Set current
SLOW Current m ode Blanking Tim e SLOW SLOW
Blanking Time
Blanking Time
PW M(Chopping) period
Figure 36. Slow Decay Falling Slope
When a coil current reached the set current, external
MOSFETs are repeated Charge mode-> Slow decay mode
according to PWM period. The coil current is controlled
constant-current by repeating two modes.
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Fast decay current control
Coil current
Fchop
Set current
CHARGE
STEP
Set current
FAST Current mode CHARGE FAST
Blanking Time
PWM(Chopping) period
Figure 37. Fast Decay Rising Slope
C oil current
Fchop
Set current
CHARGE
STEP
Set current
FAST Current mode Blanking Time FAST FAST CHARGE
Blanking Tim e
PW M(Chopping) period
Figure 38. Fast Decay Falling Slope
When a coil current reached the set current, external
MOSFETs are repeated Charge mode-> Fast decay mode
according to PWM period. The coil current is controlled
constant-current by repeating two modes.
VM Voltage supp‘y mung ol VM, vcc and VREF are not resumed Logm pln' mm 1 ' Here, we pm mean sow, 5mm srs, STEP, RST, OE FR exoepl ST pm VCC Vnuage supp‘y ummg DIVM‘ vcc VREF and VREF are not resumed. 4+ Longerman Ims
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Power on/off Sequence
Power-on timing of VM power supply and VCC power
supply and input timing of VREF voltage are not
restricted. It is possible to power on the VCC power
supply after VM and vice versa. It is also possible to
supply VREF voltage first.
At startup, when all of the following conditions are met;
VM ≥ 8.7V, VCC ≥ 2.7V, and PS = High, the internal
regulators and gate voltage regulators start. It takes
100us for the regulators to get a stable output. The
VREF input should not be floating, and the required
input signal should be applied at least 50µs, before ST is
pulled High. The register access by serial interface and
the logic pin control are possible at least 100us after ST
has gone High.
Figure 39 shows an example of timing chart that
supplied the voltage in order of VM, VCC and VREF
including the access timing of the logic pins and the
serial interface.
Power-off timing of VM power supply, VCC power
supply and VREF voltage are not restricted. It is
possible to power off the VM power supply after VCC
and vice versa. It is also possible to supply VREF
voltage last. VM, VCC and VREF voltage should be
turned off at least 10µs, after ST was pulled Low in
reverse with Power-on sequence.
Figure 40 shows an example of Power-off timing chart.
Figure 39. Timing Chart Example of Power-on
Sequence
Figure 40. Timing Chart Example of Power-off
Sequence
b 1 C r t a l Micr S 1 1/4 1/161/3 1/64 d1l1
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Table 10: Current Ratio [%] for Micro Step 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 and 1/128
1ch 2ch 1ch 2ch 1ch 2ch 1ch 2ch 1ch 2ch 1ch 2ch 1ch 2ch 1ch 2ch 1ch 2ch 1ch 2ch 1ch 2ch 1ch 2ch 1ch 2ch 1ch 2ch
θ0 100 0 100 0 100 0 100 0 100 0 100 0 100 0 θ65 70 72
θ1 100 1 θ66 69 72 69 72
θ2 100 2 100 2 θ67 68 73
θ3 100 4 θ68 67 74 67 74 67 74
θ4 100 5 100 5 100 5 θ69 66 75
θ5 100 6 θ70 65 76 65 76
θ6 100 7 100 7 θ71 64 77
θ7 100 9 θ72 63 77 63 77 63 77 63 77
θ8 100 10 100 10 100 10 100 10 θ73 62 78
θ99911 θ74 62 79 62 79
θ10 99 12 99 12 θ75 61 80
θ11 99 13 θ76 60 80 60 80 60 80
θ12 99 15 99 15 99 15 θ77 59 81
θ13 99 16 θ78 58 82 58 82
θ14 99 17 99 17 θ79 57 82
θ15 98 18 θ80 56 83 56 83 56 83 56 83 56 83
θ16 98 20 98 20 98 20 98 20 98 20 θ81 55 84
θ17 98 21 θ82 53 84 53 84
θ18 98 22 98 22 θ83 52 85
θ19 97 23 θ84 51 86 51 86 51 86
θ20 97 24 97 24 97 24 θ85 50 86
θ21 97 25 θ86 49 87 49 87
θ22 96 27 96 27 θ87 48 88
θ23 96 28 θ88 47 88 47 88 47 88 47 88
θ24 96 29 96 29 96 29 96 29 θ89 46 89
θ25 95 30 θ90 45 89 45 89
θ26 95 31 95 31 θ91 44 90
θ27 95 33 θ92 43 90 43 90 43 90
θ28 94 34 94 34 94 34 θ93 42 91
θ29 94 35 θ94 41 91 41 91
θ30 93 36 93 36 θ95 39 92
θ31 93 37 θ96 38 92 38 92 38 92 38 92 38 92 38 92
θ32 92 38 92 38 92 38 92 38 92 38 92 38 θ97 37 93
θ33 92 39 θ98 36 93 36 93
θ34 91 41 91 41 θ99 35 94
θ35 91 42 θ100 349434943494
θ36 90 43 90 43 90 43 θ101 33 95
θ37 90 44 θ102 31953195
θ38 89 45 89 45 θ103 30 95
θ39 89 46 θ104 2996299629962996
θ40 88 47 88 47 88 47 88 47 θ105 28 96
θ41 88 48 θ106 27962796
θ42 87 49 87 49 θ107 25 97
θ43 86 50 θ108 249724972497
θ44 86 51 86 51 86 51 θ109 23 97
θ45 85 52 θ110 22982298
θ46 84 53 84 53 θ111 21 98
θ47 84 55 θ112 20982098209820982098
θ48 83 56 83 56 83 56 83 56 83 56 θ113 18 98
θ49 82 57 θ114 17991799
θ50 82 58 82 58 θ115 16 99
θ51 81 59 θ116 159915991599
θ52 80 60 80 60 80 60 θ117 13 99
θ53 80 61 θ118 12991299
θ54 79 62 79 62 θ119 11 99
θ55 78 62 θ120 10 100 10 100 10 100 10 100
θ56 77 63 77 63 77 63 77 63 θ121 9 100
θ57 77 64 θ122 7 100 7 100
θ58 76 65 76 65 θ123 6 100
θ59 75 66 θ124 5 100 5 100 5 100
θ60 74 67 74 67 74 67 θ125 4 100
θ61 73 68 θ126 2 100 2 100
θ62 72 69 72 69 θ127 1 100
θ63 72 70 θ128 0 100 0 100 0 100 0 100 0 100 0 100 0 100
θ64 71 71 71 71 71 71 71 71 71 71 71 71 71 71
1/4 Step 1/2 Step
STEP
1/128 Step 1/64 Step 1/32 Step 1/16 Step 1/8 Step 1/4 Step 1/2 Step
STEP
1/128 Step 1/64 Step 1/32 Step 1/16 Step 1/8 Step
1ch current ratio ("/o) 100.0 66.7 33.3 0.0 932 0.0 33.3 66.7 20h current ratio (‘70) e104 9123 100.0
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Figure 41. Vector Locus Plot for Example of 1/128 Micro Step
0.0
33.3
66.7
100.0
0.0 33.3 66.7 100.0
1ch current ratio (%)
2ch current ratio (%)
θ0
θ32
θ104
θ128
θ120
θ112
θ96
θ88
θ80
θ72
θ64
θ56
θ48
θ40
θ24
θ16
θ8
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Table 11: Current Ratio [%] for Micro Step 1/5, 1/10, 1/20, 1/50 and 1/100
1ch 2ch 1ch 2ch 1ch 2ch 1ch 2ch 1ch 2ch 1ch 2ch 1ch 2ch 1ch 2ch 1ch 2ch 1ch 2ch
θ0 100 0 100 0 100 0 100 0 100 0 θ51 70 72
θ1 100 2 θ52 68 73 68 73
θ2 100 3 100 3 θ53 67 74
θ3 100 5 θ54 66 75 66 75
θ4 100 6 100 6 θ55 65 76 65 76
θ5 100 8 100 8 θ56 64 77 64 77
θ6 100 9 100 9 θ57 63 78
θ79911 θ58 61 79 61 79
θ8 99139913 θ59 60 80
θ99914 θ60 59 81 59 81 59 81 59 81 59 81
θ10 99 16 99 16 99 16 99 16 θ61 58 82
θ11 99 17 θ62 56 83 56 83
θ12 98 19 98 19 θ63 55 84
θ13 98 20 θ64 54 84 54 84
θ14 98 22 98 22 θ65 52 85 52 85
θ15 97 23 97 23 θ66 51 86 51 86
θ16 97 25 97 25 θ67 50 87
θ17 96 26 θ68 48 88 48 88
θ18 96 28 96 28 θ69 47 88
θ19 96 29 θ70 45 89 45 89 45 89 45 89
θ20 95 31 95 31 95 31 95 31 95 31 θ71 44 90
θ21 95 32 θ72 43 90 43 90
θ22 94 34 94 34 θ73 41 91
θ23 94 35 θ74 40 92 40 92
θ24 93 37 93 37 θ75 38 92 38 92
θ25 92 38 92 38 θ76 37 93 37 93
θ26 92 40 92 40 θ77 35 94
θ27 91 41 θ78 34 94 34 94
θ28 90 43 90 43 θ79 32 95
θ29 90 44 θ80 31 95 31 95 31 95 31 95 31 95
θ30 89 45 89 45 89 45 89 45 θ81 29 96
θ31 88 47 θ82 28 96 28 96
θ32 88 48 88 48 θ83 26 96
θ33 87 50 θ84 25 97 25 97
θ34 86 51 86 51 θ85 23 97 23 97
θ35 85 52 85 52 θ86 22 98 22 98
θ36 84 54 84 54 θ87 20 98
θ37 84 55 θ88 19 98 19 98
θ38 83 56 83 56 θ89 17 99
θ39 82 58 θ90 16 99 16 99 16 99 16 99
θ40 81 59 81 59 81 59 81 59 81 59 θ91 14 99
θ41 80 60 θ92 13 99 13 99
θ42 79 61 79 61 θ93 11 99
θ43 78 63 θ94 9 100 9 100
θ44 77 64 77 64 θ95 8 100 8 100
θ45 76 65 76 65 θ96 6 100 6 100
θ46 75 66 75 66 θ97 5 100
θ47 74 67 θ98 3 100 3 100
θ48 73 68 73 68 θ99 2 100
θ49 72 70 θ100 0 100 0 100 0 100 0 100 0 100
θ50 71 71 71 71 71 71 71 71
STEP
1/100 Step 1/50 Step 1/20 Step 1/10 Step 1/5 Step
STEP
1/100 Step 1/50 Step 1/20 Step 1/10 Step 1/5 Step
100.0 66.7 915 920 940 1ch current ratio ("/a) 0.0 0.0 950 960 33.3 980 985 990 ‘ I 9100 33.3 66.7 20h current ratio (‘70) 100.0
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Figure 42. Vector Locus Plot for Example of 1/100 Micro Step
0.0
33.3
66.7
100.0
0.0 33.3 66.7 100.0
1ch current ratio (%)
2ch current ratio (%)
θ80
θ95
θ90
θ70
θ60
θ50
θ40
θ15 θ20
θ0
θ75
θ100
θ85
θ65
θ55
θ45
θ10
θ5
θ25
θ30
θ35
b : re 1 % M Ste 1/3 1 n 1/36 1000 66] § .9 E ‘E E 3 .: 927 o ‘— 33‘3 0.0 836 0.0 33.3 66.7 100.0 2ch currem ratio (%)
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Table 12: Current Ratio [%] for Micro Step 1/3, 1/6, 1/12 and 1/36
Figure 43. Vector Locus Plot for Example of 1/36 Micro Step
1ch 2ch 1ch 2ch 1ch 2ch 1ch 2ch 1ch 2ch 1ch 2ch 1ch 2ch 1ch 2ch
θ0 100 0 100 0 100 0 100 0 θ19 68 74
θ1 100 4 θ20 64 77
θ2 100 9 θ21 61 79 61 79
θ3 99139913 θ22 57 82
θ49817 θ23 54 84
θ59822 θ24 50 87 50 87 50 87 50 87
θ6 972697269726 θ25 46 89
θ79530 θ26 42 91
θ89434 θ27 38 92 38 92
θ9 92389238 θ28 34 94
θ10 91 42 θ29 30 95
θ11 89 46 θ30 26 97 26 97 26 97
θ12 87 50 87 50 87 50 87 50 θ31 22 98
θ13 84 54 θ32 17 98
θ14 82 57 θ33 13 99 13 99
θ15 79 61 79 61 θ34 9 100
θ16 77 64 θ35 4 100
θ17 74 68 θ36 0 100 0 100 0 100 0 100
θ18 71 71 71 71 71 71
STEP
1/36 Step 1/12 Step 1/6 Step 1/3 Step
STEP
1/36 Step 1/12 Step 1/6 Step 1/3 Step
0.0
33.3
66.7
100.0
0.0 33.3 66.7 100.0
1ch current ratio (%)
2ch current ratio (%)
θ0
θ27
θ36
θ33
θ30
θ24
θ21
θ18
θ15
θ12
θ9
θ6
θ3
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STEP
I1
I2
100
0
-100
100
0
-100
(%)
(%)
MO
Figure 44-1. Current Waveform Example: Case of 1/2 Step CW
Figure 44-2. Current Waveform Example of the stepper motor: Case of 1/2 Step CW
OUT1
Motor Current
2A/div
STEP
5V/div
MO
5V/div
OUT3
Motor Current
2A/div
1/2 (Half) step
VM=48V, VCC=3.3V, VREF=1.1V (Iout≈2.0A)
RF1/2=0.11kΩ, STEP=2000Hz
Rcoil=0.47Ω
Decay mode: Mixed (25% Fast)
PWM (chopping) period: 8us
1ms/div
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STEP
MO
I1 0
50
100
[%]
-50
-100
I2 0
50
100
[%]
-50
-100
Figure 45-1. Current Waveform Example: Case of 1/16 Step CW
Figure 45-2. Current Waveform Example of the stepper motor: Case of 1/16 Step CW
OUT1
Motor Current
2A/div
STEP
5V/div
MO
5V/div
OUT3
Motor Current
2A/div
1/16 step
VM=48V, VCC=3.3V, VREF=1.1V (Iout≈2.0A)
RF1/2=0.11kΩ, STEP=2000Hz
Rcoil=0.47Ω
Decay mode: Mixed (25% Fast)
PWM (chopping) period: 8us
STEP MO [mm 50 60 40m M110 , H 50 50 400 «« mm; Luk
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Figure 46-1. Current Waveform Example: Case of 1/128 Step CW
Figure 46-2. Current Waveform Example of the stepper motor: Case of 1/128 Step CW
OUT1
Motor Current
2A/div
STEP
5V/div
MO
5V/div
OUT3
Motor Current
2A/div
1/128 step
VM=48V, VCC=3.3V, VREF=1.1V (Iout≈2.0A)
RF1/2=0.11kΩ, STEP=2000Hz
Rcoil=0.47Ω
Decay mode: Mixed (25% Fast)
PWM (chopping) period: 8us
50ms/div
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Over-Current Protection (OCP)
The over-current covers the following three circuit short
modes.
1. Output shorted to power rail
2. Output shorted to ground
3. Loads shorted to each other (two outputs of a
channel)
Figure 48, Figure 49. and Figure 50. show these three
circuit short modes.
The over-current is detected when the voltage between
drain and source of the external P-MOSFET exceeds 3V
during turn-on.
For the low side, it is detected when RFx voltage
exceeds three times the RFx voltage defined by
applying setting current (ATTRATIO =1.0:100%). RFx
pin voltage is as shown in Equation 6. Refer to equation
2 to determine Iout.

 ∙

5………6
Where,
IOUT(max) : Coil current [A] (ATTRATIO=1.0: 100%)
RRFx : Resistor between RFx and GND [Ω]
VRFx(max) : RFx voltage [V] (ATTRATIO=1.0: 100%)
For example, in case of
 1.5V]
 1.5
5[V]0.3V
The over-current protection voltage of low side is
3∙
 30.3[V]0.9V
It depends on VREF input voltage.
Latched OCP
If a coil current exceeds the detection current level for
2µs, the outputs are turned off. Subsequently, the
outputs are turned on again after the timer latch period
(typ: 256μs). If the output remains in over-current
condition, it will be turned off again and remain latched
off. In this case the programmed EMO output is asserted.
The over-current protection latch (the outputs are turned
off), is released by setting ST = "L".
Figure 47. Timing Chart of Latched OCP
Auto Reset OCP
When the over-current is detected for 2µs (typ), the
outputs turned off for 2ms (typ), and they are turned on
again after 2ms. If the over-current mode still continues,
over-current protection circuit is continued repetition
operation of on and off until the current gets down.
Under Voltage Lockout (UVLO)
The integrated UVLO protection enables safe shutdown
of the system if the voltage on either VM or VCC drops.
When the VM voltage is less than 7.6V (typ), the
outputs are turned off and EMO output is asserted.
When the VCC voltage is less than 2.3V (typ), logic
circuits are put into the reset state and the outputs are
turned off.
Thermal Shutdown (TSD)
The built-in TSD protection prevents damage to the
LV8726 from excessive heat. If the junction
temperature Tj exceeds 180°C (typ), the outputs are
turned off. If Tj goes down under 140°C (40°C of
hysteresis), the outputs are automatically restored. This
thermal shutdown function doesn’t guarantee protection
of the set and the destruction prevention.
Faul
t
Detection
H-bridge
Output state
Output ON
Internal
counte
2µs
Output ON
Output OFF
Over-curren
t
Detected
Over-current
Detected
Release
1st counte
r
start
1st counte
r
stop
1st counte
r
start
1st counte
r
stop 2nd counte
r
start
2nd counte
r
stop
Timer latch period
(typ:256
µs
)
Output OFF
2µs
VM VM Ta Tr1 Ta ‘3? OFF OFF ‘E’ / \ ‘3” OFF OUT2 fl OUT1 ___M/, OUT2 TfZ m Ta Tr4 % F %* F E a K a Shunrmrcun Delecuon PGNDi PGNDi VM VM Shonclrcun Shamrclrcmt Delecuon T Daemon T Trl m m m -*E’ \ ‘3* OF / \ HF 0F OUT1 M/ OUT2 OUT1 / OUT2 TI? Tr4 TQ Tr4 OFF 4{E 4E“,-EEI OFF +Efi AEIF-Efil Shantlrcu R T T Shantlrcu n Deteclwon FGND FGND
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Short to Power
Figure 48. Short Output to Power Rail
Short to GND
Figure 49. Short Output to GND
Load short
Figure 50. Short Load
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PCB LAYOUT GUIDELINES
VM and Ground routing
Make sure to connect VM and the power rail of the
external P channel MOSFETs by a low impedance route.
As high current flows into the source of the N channel
MOSFETs, these sources must also be connected by a
low impedance route to power ground (PGND). PGND
and GND (pin 30) of LV8726 must also be connected by
low impedance traces.
Exposed Pad
The exposed pad is connected to the frame of the
LV8726 and must be connected to GND. When GND
(pin 30) and PGND of the N channel MOSFETs are in
the same plane, connect the exposed pad to same GND.
Do not connect the exposed pad to the PGND only. If
GND (30pin) and PGND are divided, connect it to GND
(30pin).
Thermal Test conditions
Size: 90mm × 90mm × 1.6mm (two layers PCB)
Material: Glass epoxy
Copper wiring density: L1 = 55% / L2 = 70%
L1 : Copper wiring pattern diagram (top) L2 : Copper wiring pattern diagram (bottom)
Figure 51. Pattern Diagram of Top and Bottom Layer
Recommendation
The thermal data provided is for the thermal test
condition where 90% or more of the exposed die pad is
soldered.
It is recommended to derate critical parameters for a
safe design. Electrical parameters that are recommended
to be derated are: operating voltage, operating current,
junction temperature, and device power dissipation. The
recommended derating for a safe design is as shown
below:
Check solder joints and verify reliability of solder joints
for critical areas such as exposed die pad, power pins
and grounds.
Any void or deterioration in solder joint of these critical
areas may cause deterioration in thermal conduction and
lead to thermal destruction of the device.
Maximum 80% for operating voltage
Maximum 80% for operating current
Maximum 80% for junction temperature
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PACKAGE DIMENSIONS
unit : mm
SEATING
0.20 H
A
BOTTOM VIEW
TOP VIEW
SIDE VIEW
D
B
E
0.08 C
C
e
PLANE
48X
0.05
1
37
48
25
13
4X
NOTE 9
NOTE 7
NOTE 7NOTE 7
NOTES 4 & 6
NOTES
4 & 6 NOTE 9
4X 12 TIPS
DETAIL A
NOTE 3
D
A
E1
D1
A-B D
0.20 C A-B D
D2 E2
0.20 C A-B D
bDETAIL A
A2
A1
H
LM
L2
TQFP48 EP 7x7, 0.5P
CASE 932F
ISSUE C
DIM MIN MAX
MILLIMETERS
A0.95 1.25
A1 0.05 0.15
D1 7.00 BSC
b0.17 0.27
D9.00 BSC
D2 4.90 5.10
e0.50 BSC
L0.45 0.75
M0 7
L2 0.25 BSC
SOLDERING FOOTPRINT*
0.29
48X
RECOMMENDED
DIMENSIONS: MILLIMETERS
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL BE 0.08 MAX. AT MMC. DAMBAR CANNOT BE
LOCATED ON THE LOWER RADIUS OF THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD IS 0.07.
SIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE
BURRS SHALL NOT EXCEED 0.25 PER SIDE. DIMENSIONS D1 AND E1
ARE MAXIMUM PLASTIC BODY SIZE INCLUDING MOLD MISMATCH.
5. THE TOP PACKAGE BODY SIZE MAY BE SMALLER THAN THE BOTTOM
PACKAGE SIZE BY AS MUCH AS 0.15.
6. DATUMS A-B AND D ARE DETERMINED AT DATUM PLANE H.
7. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING
8. DIMENSIONS D AND E TO BE DETERMINED AT DATUM PLANE C.
A2 0.90 1.20
E1 7.00 BSC
E9.00 BSC
E2 4.90 5.10
5.30
9.36
5.30 9.36
0.50
PITCH
1.13
48X
1
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ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States
and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of
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without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated foreach
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