InnoSwitch3-EP Family Datasheet by Power Integrations
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integrations“
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InnoSwitch3-EP Family
www.power.com June 2020
Off-Line CV/CC QR Flyback Switcher IC with Integrated
Primary Switch, Synchronous Rectification and
FluxLink Feedback
This Product is Covered by Patents and/or Pending Patent Applications.
Product Highlights
Highly Integrated, Compact Footprint
•Very high efficiency across full load range
•Incorporates a multi-mode Quasi-Resonant (QR) / CCM flyback
controller, high-voltage switch, secondary-side sensing and synchro-
nous rectification driver
•Excellent multi-output cross regulation with weighted secondary-side
regulation (SSR) feedback and synch FETs
•Integrated FluxLink™, HIPOT-isolated, feedback link
•Exceptional CV/CC accuracy, independent of external components
•Adjustable accurate output current sense using external output sense
resistor
•PowiGaN™ technology – up to 100 W without heat sinks (INN3678C,
INN3679C and INN3670C)
EcoSmart™ – Energy Efficient
•Less than 30 mW no-load including line sense
•Easily meets all global energy efficiency regulations
•Low heat dissipation
Advanced Protection / Safety Features
•Open SR FET-gate detection
•Fast input line UV/OV protection
•Auto-restart fault response for output OVP
•725 V / 750 V switch rating series for excellent surge withstand
•900 V switch rating series for industrial design or extra safety
margin
Optional Features
•Auto-restart output UV protection with option for peak power delivery
Full Safety and Regulatory Compliance
•Reinforced isolation
•Isolation voltage >4000 VAC
•100% production HIPOT testing
•UL1577 and TUV (EN60950 and EN62368) safety approved
•Excellent noise immunity enables designs that achieve class “A”
performance criteria for EN61000-4 suite; EN61000-4-2, 4-3
(30 V/m), 4-4, 4-5, 4-6, 4-8 (100 A/m) and 4-9 (1000 A/m)
Green Package
•Halogen free and RoHS compliant
Applications
•Auxiliary, standby and bias power supplies for appliances, computers
and consumer products
•Utility meter, smart grid and industrial power supplies
Description
The InnoSwitch™3-EP family of ICs dramatically simplifies the design
and manufacture of flyback power converters, particularly those
requiring high efficiency and/or compact size. The InnoSwitch3-EP
family combines primary and secondary controllers and safety-rated
feedback into a single IC.
InnoSwitch3-EP family devices incorporate multiple protection features
including line over and undervoltage protection, output overvoltage
and over-current limiting, and over-temperature shutdown. Devices are
available with standard and peak power delivery options, and
commonly used auto-restart protection behaviors.
Figure 1. Typical Application Schematic.
Output Power Table
Product3
725 V MOSFET
230 VAC ± 15% 85-265 VAC
Peak or
Open Frame1,2
Peak or
Open Frame1,2
INN3672C 12 W 10 W
INN3673C 15 W 12 W
INN3674C 25 W 20 W
INN3675C 30 W 25 W
INN3676C 40 W 36 W
INN3677C 45 W 40 W
Product3
750 V PowiGaN Switch
230 VAC ± 15% 85-265 VAC
Peak or
Open Frame1,2
Peak or
Open Frame1,2
INN3678C 75 W 65 W
INN3679C 85 W 75 W
INN3670C 100 W 85 W
Product3
900 V MOSFET
230 VAC ± 15% 85-265 VAC
Peak or
Open Frame1,2
Peak or
Open Frame1,2
INN3692C 12 W 10 W
INN3694C 25 W 20 W
INN3696C 35 W 30 W
Table 1. Output Power Table.
Notes:
1. Minimum continuous power in a typical non-ventilated enclosed typical size
adapter measured at 40 °C ambient. Max output power is dependent on the
design. With condition that package temperature must be < 125 °C.
2. Minimum peak power capability.
3. Package: InSOP-24D.
Figure 2. High Creepage, Safety-Compliant InSOP-24D Package.
PI-8184-072419
Secondary
Control IC
SR FET
D V
S IS
VOUT
BPS
FB
GND
SR
BPP
FWD
Primary Switch
and Controller
Optional
Current
Sense
InnoSwitch3-EP
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Figure 3. Primary Controller Block Diagram.
Figure 4. Secondary Controller Block Diagram.
PI-8045l-101619
DETECTOR
ENABLE
SR
FORWARD
(FW)
FEEDBACK
(FB)
SECONDARY
BYPASS
(BPS)
SECONDARY
GROUND
(GND)
ISENSE
(IS)
SYNC RECTIFIER DRIVE
(SR)
CABLE DROP
COMPENSATION/
FEEDBACK
COMPENSATION
FEEDBACK
DRIVER
VO
INH
QR
Ts
MAX
INH
QR
t
OFF(MIN)
t
SECINH(MAX)
t
SS(RAMP)
V
BPS(UVLO)(TH)
SR CONTROL
INH
DCM
VREF
SR
IS THRESHOLD
FORWARD
BPS
UV
VO
VOUT
OSCILLATOR/
TIMER
REGULATOR
V
BPS
SECONDARY
LATCH/
AUTO-RESTART
HANDSHAKE/
AUTO-RESTART
SR
THRESHOLD
CONTROL
S
Q
Q
R
+
+
-
+
-
+
-
PI-8044h-111219
RESET
Q
R
S
Q
+
-
+
-
THERMAL
SHUTDOWN
OSCILLATOR/
TIMERS
OV/UV
BPP/UV
VILIM
PRIM/SEC
SecPulse
PRIM/SEC
UV/OV
BPP/UV
ENABLE
ENABLE
IS
FAULT
FAULT
PRIM-CLK
GATE
BPP
DRIVER
JITTER
tON(MAX)
ILIM
BPP/UV
GATE
DRAIN
(D)
SOURCE
(S)
UNDER/OVER
INPUT VOLTAGE (V)
PRIMARY BYPASS
(BPP)
tOFF(BLOCK)
SenseFET
Power
Switch
tON(MAX) tOFF(BLOCK)
GATE
VILIM
LATCH-OFF/
AUTO-RESTART
GATE
PRIMARY OVP
LATCH/
AUTO-RESTART
RECEIVER
CONTROLLER
PRIMARY
BYPASS PIN
UNDERVOLTAGE
VSHUNT
VBP+
LINE
INTERFACE
AUTO-RESTART
COUNTER
PRIMARY BYPASS
REGULATOR
PRIMARY
BYPASS PIN
CAPACITOR
SELECT AND
CURRENT
LIMIT
LEB
SecREQ
PRIM-CLK
SEC-
LATCH
From
Secondary
Controller
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Figure 5. Pin Configuration.
Pin Functional Description
ISENSE (IS) Pin (Pin 1)
Connection to the power supply output terminals. An external
current sense resistor should be connected between this and the
GND pin. If current regulation/accurate over-current protection is not
required, this pin should be tied to the GND pin.
SECONDARY GROUND (GND) (Pin 2)
GND for the secondary IC. Note this is not the power supply output
GND due to the presence of the sense resistor between this and the
ISENSE pin.
FEEDBACK (FB) Pin (Pin 3)
Connection to an external resistor divider to set the power supply
output voltage.
SECONDARY BYPASS (BPS) Pin (Pin 4)
Connection point for an external bypass capacitor for the secondary
IC supply.
SYNCHRONOUS RECTIFIER DRIVE (SR) Pin (Pin 5)
Gate driver for external SR FET. If no SR FET is used connect this pin
to GND.
OUTPUT VOLTAGE (VOUT) Pin (Pin 6)
Connected directly to the output voltage, to provide current for the
controller on the secondary-side and provide secondary protection.
FORWARD (FWD) Pin (Pin 7)
The connection point to the switching node of the transformer output
winding providing information on primary switch timing. Provides power
for the secondary-side controller when VOUT is below threshold.
NC Pin (Pin 8-12)
Leave open. Should not be connected to any other pins.
UNDER/OVER INPUT VOLTAGE (V) Pin (Pin 13)
A high-voltage pin connected to the AC or DC side of the input bridge
for detecting undervoltage and overvoltage conditions at the power
supply input. This pin should be tied to SOURCE pin to disable UV/OV
protection.
PRIMARY BYPASS (BPP) Pin (Pin 14)
The connection point for an external bypass capacitor for the
primary-side supply. This is also the ILIM selection pin for choosing
standard ILIM or ILIM+1.
NC Pin (Pin 15)
Leave open or connect to SOURCE pin or BPP pin.
SOURCE (S) Pin (Pin 16-19)
These pins are the power switch source connection. Also ground
reference for primary BYPASS pin.
DRAIN (D) Pin (Pin 24)
Power switch drain connection.
V 13 12 NC
BPP 14 11 NC
NC 15 10 NC
9 NC
S 16-19
D 24
8 NC
7 FWD
6 VOUT
5 SR
4 BPS
3 FB
2 GND
1 IS
PI-7877-022216
InnoSwitch3-EP Functional Description
The InnoSwitch3-EP combines a high-voltage power switch, along
with both primary-side and secondary-side controllers in one device.
The architecture incorporates a novel inductive coupling feedback
scheme (FluxLink) using the package lead frame and bond wires to
provide a safe, reliable, and cost-effective means to transmit
accurate, output voltage and current information from the secondary
controller to the primary controller.
The primary controller on InnoSwitch3-EP is a Quasi-Resonant (QR)
flyback controller that has the ability to operate in continuous
conduction mode (CCM), boundary mode (CrM) and discontinuous
conduction mode (DCM). The controller uses both variable frequency
and variable current control schemes. The primary controller consists
of a frequency jitter oscillator, a receiver circuit magnetically coupled to
the secondary controller, a current limit controller, 5 V regulator on
the PRIMARY BYPASS pin, audible noise reduction engine for light
load operation, bypass overvoltage detection circuit, a lossless input
line sensing circuit, current limit selection circuitry, over-temperature
protection, leading edge blanking, secondary output diode / SR FET
short protection circuit and a power switch.
The InnoSwitch3-EP secondary controller consists of a transmitter
circuit that is magnetically coupled to the primary receiver, a constant
voltage (CV) and a constant current (CC) control circuit, a 4.4 V
regulator on the SECONDARY BYPASS pin, synchronous rectifier FET
driver, QR mode circuit, oscillator and timing circuit, and numerous
integrated protection features.
Figure 3 and Figure 4 show the functional block diagrams of the
primary and secondary controller, highlighting the most important
features.
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Figure 6. Normalized Primary Current vs. Frequency.
30 40 50 60 70 90 10080
Steady-State Switching Frequency (kHz)
Normalized ILIM (A)
1.05
0.8
0.75
0.85
0.9
0.95
1.0
PI-8205-120516
Primary Controller
InnoSwitch3-EP has variable frequency QR controller plus CCM/CrM/
DCM operation for enhanced efficiency and extended output power
capability.
PRIMARY BYPASS Pin Regulator
The PRIMARY BYPASS pin has an internal regulator that charges the
PRIMARY BYPASS pin capacitor to VBPP by drawing current from the
DRAIN pin whenever the power switch is off. The PRIMARY BYPASS
pin is the internal supply voltage node. When the power switch is on,
the device operates from the energy stored in the PRIMARY BYPASS
pin capacitor.
In addition, a shunt regulator clamps the PRIMARY BYPASS pin
voltage to VSHUNT when current is provided to the PRIMARY BYPASS
pin through an external resistor. This allows the InnoSwitch3-EP to
be powered externally through a bias winding, decreasing the no-load
consumption to less than 30 mW in a 5 V output design.
Primary Bypass ILIM Programming
InnoSwitch3-EP ICs allows the user to adjust current limit (ILIM)
settings through the selection of the PRIMARY BYPASS pin capacitor
value. A ceramic capacitor can be used.
There are 2 selectable capacitor sizes - 0.47 mF and 4.7 mF for setting
standard and increased ILIM settings respectively.
Primary Bypass Undervoltage Threshold
The PRIMARY BYPASS pin undervoltage circuitry disables the power
switch when the PRIMARY BYPASS pin voltage drops below ~4.5 V
(VBPP - VBP(H)) in steady-state operation. Once the PRIMARY BYPASS
pin voltage falls below this threshold, it must rise to VSHUNT to
re-enable turn-on of the power switch.
Primary Bypass Output Overvoltage Function
The PRIMARY BYPASS pin has a latching/auto-restart OV protection
feature depending on H Code. A Zener diode in parallel with the
resistor in series with the PRIMARY BYPASS pin capacitor is typically
used to detect an overvoltage on the primary bias winding and
activate the protection mechanism. In the event that the current into
the PRIMARY BYPASS pin exceeds ISD, the device will latch-off or
disable the power switch switching for a time tAR(OFF), after which time
the controller will restart and attempt to return to regulation (see
Secondary Fault Response in the Feature Code Addendum).
VOUT OV protection is also included as an integrated feature on the
secondary controller (see Output Voltage Protection).
Over-Temperature Protection
The thermal shutdown circuitry senses the primary Switch die
temperature. The threshold is set to TSD with either a hysteretic or
latch-off response depending on H Code.
Hysteretic response: If the die temperature rises above the threshold,
the power switch is disabled and remains disabled until the die
temperature falls by TSD(H) at which point switching is re-enabled. A
large amount of hysteresis is provided to prevent over-heating of the
PCB due to a continuous fault condition.
Latch-off response: If the die temperature rises above the threshold
the power switch is disabled. The latching condition is reset by
bringing the PRIMARY BYPASS pin below VBPP(RESET) or by going below
the UNDER/OVER INPUT VOLTAGE pin UV (IUV-) threshold.
Current Limit Operation
The primary-side controller has a current limit threshold ramp that is
linearly decreasing to the time from the end of the previous primary
switching cycle (i.e. from the time the primary Switch turns off at the
end of a switching cycle).
This characteristic produces a primary current limit that increases as
the switching frequency (load) increases (Figure 6).
This algorithm enables the most efficient use of the primary switch
with the benefit that this algorithm responds to digital feedback
information immediately when a feedback switching cycle request is
received.
At high load, switching cycles have a maximum current approaching
100% ILIM. This gradually reduces to 30% of the full current limit as
load decreases. Once 30% current limit is reached, there is no
further reduction in current limit (since this is low enough to avoid
audible noise). The time between switching cycles will continue to
increase as load reduces.
Jitter
The normalized current limit is modulated between 100% and 95%
at a modulation frequency of fM. This results in a frequency jitter of
~7 kHz with average frequency of ~100 kHz.
Auto-Restart
In the event a fault condition occurs (such as an output overload,
output short-circuit, or external component/pin fault), the
InnoSwitch3-EP enters auto-restart (AR) or latches off. The latching
condition is reset by bringing the PRIMARY BYPASS pin below ~3 V or
by going below the UNDER/OVER INPUT VOLTAGE pin UV (IUV-)
threshold.
In auto-restart, switching of the power switch is disabled for tAR(OFF).
There are 2 ways to enter auto-restart:
1. Continuous secondary requests at above the overload detection
frequency fOVL (~110 kHz) for longer than 82 ms (tAR).
2. No requests for switching cycles from the secondary for >tAR(SK).
The second is included to ensure that if communication is lost, the
primary tries to restart. Although this should never be the case in
normal operation, it can be useful when system ESD events (for
example) causes a loss of communication due to noise disturbing the
secondary controller. The issue is resolved when the primary restarts
after an auto-restart off-time.
v Has Renewed
Handshaklng
Mae;
5: Has Taken
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Figure 7. Primary-Secondary Handshake Flowchart.
Yes
tAR(OFF)
tAR
Yes
Yes
No
No
No
S: Has powered
up within tAR
P: Has Received
Handshaking
Pulses
S: Has Taken
Control?
P: Switching
S: Sends Handshaking Pulses
P: Stops Switching, Hands
Over Control to Secondary
P: Not Switching
S: Doesn’t Take Control
P: Continuous Switching
S: Doesn’t Take Control
P: Goes to Auto-Restart Off
S: Bypass Discharging
P: Auto-Restart
S: Powering Up
P: Primary Chip
S: Secondary Chip
End of Handshaking,
Secondary Control Mode
PI-7416a-102116
Start
P: Powered Up, Switching
S: Powering Up
The auto-restart is reset as soon as an AC reset occurs.
SOA Protection
In the event that there are two consecutive cycles where the 110%
ILIM is reached within ~500 ns (the blanking time + current limit delay
time) (including leading edge current spike), the controller will skip 2.5
cycles or ~25 ms (based on full frequency of 100 kHz). This provides
sufficient time for the transformer to reset with large capacitive loads
without extending the start-up time.
Secondary Rectifier/SR Switch Short Protection (SRS)
In the event that the output diode or SR FET is short-circuited before
or during the primary conduction cycle, the drain current (prior to the
end of the leading edge blanking time) can be much higher than the
maximum current limit threshold. If the controller turns the high-
voltage power switch off, the resulting peak drain voltage could
exceed the rated BVDSS of the device, resulting in catastrophic failure
even with minimum on-time.
To address this issue, the controller features a circuit that reacts
when the drain current exceeds the maximum current limit threshold
prior to the end of leading-edge blanking time. If the leading-edge
current exceeds current limit within a cycle (200 ns), the primary
controller will trigger a 30 ms off-time event. SOA mode is triggered if
there are two consecutive cycles above current limit within tLES
(~500 ns). SRS mode also triggers tAR(OFF)SH off-time, if the current
limit is reached within 200 ns after a 30 ms off-time.
SRS protection is not available on PowiGaN devices INN3678C,
INN3679C and INN3670C.
Input Line Voltage Monitoring
The UNDER/OVER INPUT VOLTAGE pin is used for input undervoltage
and overvoltage sensing and protection.
A sense resistor is tied between the high-voltage DC bulk capacitor
after the bridge (or to the AC side of the bridge rectifier for fast AC
reset) and the UNDER/OVER INPUT VOLTAGE pin to enable this
functionality. This function can be disabled by shorting the UNDER/
OVER INPUT VOLTAGE pin to SOURCE pin.
At power-up, after the primary bypass capacitor is charged and the
ILIM state is latched, and prior to switching, the state of the UNDER/
OVER INPUT VOLTAGE pin is checked to confirm that it is above the
brown-in and below the overvoltage shutdown thresholds.
In normal operation, if the UNDER/OVER INPUT VOLTAGE pin current
falls below the brown-out threshold and remains below brown-in for
longer than tUV-, the controller enters auto-restart. Switching will only
resume once the UNDER/OVER INPUT VOLTAGE pin current is above
the brown-in threshold.
In the event that the UNDER/OVER INPUT VOLTAGE pin current is
above the overvoltage threshold, the controller will also enter
auto-restart. Again, switching will only resume once the UNDER/
OVER INPUT VOLTAGE pin current has returned to within its normal
operating range.
The input line UV/OV function makes use of an internal high-voltage
Switch on the UNDER/OVER INPUT VOLTAGE pin to reduce power
consumption. If the cycle off-time tOFF is greater than 50 ms, the
internal high-voltage Switch will disconnect the external sense
resistor from the internal IC to eliminate current drawn through the
sense resistor. The line sensing function will activate again at the
beginning of the next switching cycle.
Primary-Secondary Handshake
At start-up, the primary-side initially switches without any feedback
information (this is very similar to the operation of a standard
TOPSwitch™, TinySwitch™ or LinkSwitch™ controllers).
If no feedback signals are received during the auto-restart on-time
(tAR), the primary goes into auto-restart mode. Under normal
conditions, the secondary controller will power-up via the FORWARD
pin or from the OUTPUT VOLTAGE pin and take over control. From
this point onwards the secondary controls switching.
If the primary controller stops switching or does not respond to cycle
requests from the secondary during normal operation (when the
secondary has control), the handshake protocol is initiated to ensure
that the secondary is ready to assume control once the primary
begins to switch again. An additional handshake is also triggered if
the secondary detects that the primary is providing more cycles than
were requested.
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The most likely event that could require an additional handshake is
when the primary stops switching as the result of a momentary line
brown-out event. When the primary resumes operation, it will default
to a start-up condition and attempt to detect handshake pulses from
the secondary.
If the secondary does not detect that the primary responds to
switching requests for 8 consecutive cycles, or if the secondary
detects that the primary is switching without cycle requests for 4 or
more consecutive cycles, the secondary controller will initiate a
second handshake sequence. This provides additional protection
against cross-conduction of the SR FET while the primary is
switching. This protection mode also prevents an output overvoltage
condition in the event that the primary is reset while the secondary is
still in control.
Wait and Listen
When the primary resumes switching after initial power-up recovery
from an input line voltage fault (UV or OV) or an auto-restart event, it
will assume control and require a successful handshake to relinquish
control to the secondary controller.
As an additional safety measure the primary will pause for an
auto-restart on-time period, tAR (~82 ms), before switching. During
this “wait” time, the primary will “listen” for secondary requests. If it
sees two consecutive secondary requests, separated by ~30 ms, the
primary will infer secondary control and begin switching in slave
mode. If no pulses occurs during the tAR “wait” period, the primary
will begin switching under primary control until handshake pulses are
received.
Audible Noise Reduction Engine
The InnoSwitch3-EP features an active audible noise reduction mode
whereby the controller (via a “frequency skipping” mode of operation)
avoids the resonant band (where the mechanical structure of the
power supply is most likely to resonate − increasing noise amplitude)
between 5 kHz and 12 kHz - 200 ms and 83 ms period respectively. If a
secondary controller switch request occurs within this time window
from the last conduction cycle, the gate drive to the power switch is
inhibited.
Secondary Controller
As shown in the block diagram in Figure 4, the IC is powered by a
4.4 V (VBPS) regulator which is supplied by either VOUT or FWD. The
SECONDARY BYPASS pin is connected to an external decoupling
capacitor and fed internally from the regulator block.
The FORWARD pin also connects to the negative edge detection
block used for both handshaking and timing to turn on the SR FET
connected to the SYNCHRONOUS RECTIFIER DRIVE pin. The
FORWARD pin voltage is used to determine when to turn off the
SR FET in discontinuous conduction mode operation. This is when
the voltage across the RDS(ON) of the SR FET drops below zero volts.
In continuous conduction mode (CCM) the SR FET is turned off when
the feedback pulse is sent to the primary to demand the next
switching cycle, providing excellent synchronous operation, free of
any overlap for the FET turn-off.
The mid-point of an external resistor divider network between the
OUTPUT VOLTAGE and SECONDARY GROUND pins is tied to the
FEEDBACK pin to regulate the output voltage. The internal voltage
comparator reference voltage is VFB (1.265 V).
The external current sense resistor connected between ISENSE and
SECONDARY GROUND pins is used to regulate the output current in
constant current regulation mode.
Minimum Off-Time
The secondary controller initiates a cycle request using the inductive-
connection to the primary. The maximum frequency of secondary-
cycle requests is limited by a minimum cycle off-time of tOFF(MIN). This
is in order to ensure that there is sufficient reset time after primary
conduction to deliver energy to the load.
Maximum Switching Frequency
The maximum switch-request frequency of the secondary controller
is fSREQ.
Frequency Soft-Start
At start-up the primary controller is limited to a maximum switching
frequency of fSW and 75% of the maximum programmed current limit
at the switch-request frequency of 100 kHz.
The secondary controller temporarily inhibits the FEEDBACK short
protection threshold (VFB(OFF)) until the end of the soft-start (tSS(RAMP))
time. After hand-shake is completed the secondary controller linearly
ramps up the switching frequency from fSW to fSREQ over the tSS(R AMP)
time period.
In the event of a short-circuit or overload at start-up, the device will
move directly into CC (constant-current) mode. The device will go
into auto-restart (AR), if the output voltage does not rise above the
VFB(AR) threshold before the expiration of the soft-start timer (tSS(R AMP))
after handshake has occurred.
The secondary controller enables the FEEDBACK pin-short protection
mode (VFB(OFF)) at the end of the tSS(RAMP) time period. If the output
short maintains the FEEDBACK pin below the short-circuit threshold,
the secondary will stop requesting pulses triggering an auto-restart
cycle.
If the output voltage reaches regulation within the tSS(RAMP) time
period, the frequency ramp is immediately aborted and the secondary
controller is permitted to go full frequency. This will allow the
controller to maintain regulation in the event of a sudden transient
loading soon after regulation is achieved. The frequency ramp will
only be aborted if quasi-resonant-detection programming has already
occurred.
Maximum Secondary Inhibit Period
Secondary requests to initiate primary switching are inhibited to
maintain operation below maximum frequency and ensure minimum
off-time. Besides these constraints, secondary-cycle requests are
also inhibited during the “ON” time cycle of the primary switch (time
between the cycle request and detection of FORWARD pin falling
edge). The maximum time-out in the event that a FORWARD pin
falling edge is not detected after a cycle requested is ~30 ms.
Output Voltage Protection
In the event that the sensed voltage on the FEEDBACK pin is 2%
higher than the regulation threshold, a bleed current of ~2.5 mA (3
mA max) is applied on the OUTPUT VOLTAGE pin (weak bleed). This
bleed current increases to ~200 mA (strong bleed) in the event that
the FEEDBACK pin voltage is raised beyond ~10% of the internal
FEEDBACK pin reference voltage. The current sink on the OUTPUT
VOLTAGE pin is intended to discharge the output voltage after
momentary overshoot events. The secondary does not relinquish
control to the primary during this mode of operation.
If the voltage on the FEEDBACK pin is sensed to be 20% higher than
the regulation threshold, a command is sent to the primary to either
latch-off or begin an auto-restart sequence (see Secondary Fault
Response in Feature Code Addendum). This integrated VOUT OVP can
be used independently from the primary sensed OVP or in conjunction.
R uest Wlndow
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Figure 8. Intelligent Quasi-Resonant Mode Switching.
PI-8147-102816
Output Voltage
Request Window
Time
Time
Primary VDS FORWARD Pin Voltage
FEEDBACK Pin Short Detection
If the sensed FEEDBACK pin voltage is below VFB(OFF) at start-up, the
secondary controller will complete the handshake to take control of
the primary complete tSS(R AMP) and will stop requesting cycles to initiate
auto-restart (no cycle requests made to primary for longer than tAR(SK)
second triggers auto-restart).
During normal operation, the secondary will stop requesting pulses
from the primary to initiate an auto-restart cycle when the FEEDBACK
pin voltage falls below the VFB(OFF) threshold. The deglitch filter on the
protection mode is on for less than ~10 ms. By this mechanism, the
secondary will relinquish control after detecting that the FEEDBACK
pin is shorted to ground.
Auto-Restart Thresholds
The FEEDBACK pin includes a comparator to detect when the
feedback voltage falls below VFB(AR), for a duration exceeding tFB(AR).
The secondary controller will relinquish control when this fault
condition is detected. This threshold is meant to limit the range of
constant current (CC) operation and is included to support high power
charger applications.
SECONDARY BYPASS Pin Overvoltage Protection
The InnoSwitch3-EP secondary controller features a SECONDARY
BYPASS pin OV feature similar to the PRIMARY BYPASS pin OV
feature. When the secondary is in control, in the event that the
SECONDARY BYPASS pin current exceeds IBPS(SD) (~7 mA) the
secondary will send a command to the primary to initiate an
auto-restart off-time (tAR(OFF)).
Output Constant Current Regulation/Output Over-Current
Protection
The InnoSwitch3-EP regulates the output current through an external
current sense resistor between the ISENSE and SECONDARY
GROUND pins and also controls output power in conjunction with the
output voltage sensed on the OUTPUT VOLTAGE pin. If constant
current regulation/accurate over-current protection is not required,
the ISENSE pin must be tied to the SECONDARY GROUND pin. Also
see ‘Peak Power Delivery’ section.
SR Disable Protection
In each cycle SR is only engaged if a set cycle was requested by the
secondary controller and the negative edge is detected on the
FORWARD pin. In the event that the voltage on the ISENSE pin
exceeds approximately 3 times the CC threshold, the SR FET drive is
disabled until the surge current has diminished to nominal levels.
rent/,
I ARwh
—power
\ntegmtmnS'
Rev. M 06/20
8
InnoSwitch3-EP
www.power.com
Figure 9. Current Sense Resistor in a Design.
SR Static Pull-Down
To ensure that the SR gate is held low when the secondary is not in
control, the SYNCHRONOUS RECTIFIER DRIVE pin has a nominally
“ON” device to pull the pin low and reduce any voltage on the SR gate
due to capacitive coupling from the FORWARD pin.
Open SR Protection
In order to protect against an open SYNCHRONOUS RECTIFIER
DRIVE pin system fault the secondary controller has a protection
mode to ensure the SYNCHRONOUS RECTIFIER DRIVE pin is
connected to an external FET. If the external capacitance on the
SYNCHRONOUS RECTIFIER DRIVE pin is below 100 pF, the device
will assume the SYNCHRONOUS RECTIFIER DRIVE pin is “open” and
there is no FET to drive. If the pin capacitance detected is above
100 pF, the controller will assume an SR FET is connected.
In the event the SYNCHRONOUS RECTIFIER DRIVE pin is detected to
be open, the secondary controller will stop requesting pulses from
the primary to initiate auto-restart.
If the SYNCHRONOUS RECTIFIER DRIVE pin is tied to ground at
start-up, the SR drive function is disabled and the open
SYNCHRONOUS RECTIFIER DRIVE pin protection mode is also
disabled.
Intelligent Quasi-Resonant Mode Switching
In order to improve conversion efficiency and reduce switching
losses, the InnoSwitch3-EP features a means to force switching when
the voltage across the primary switch is near its minimum voltage
when the converter operates in discontinuous conduction mode (DCM).
This mode of operation is automatically engaged in DCM and disabled
once the converter moves to continuous-conduction mode (CCM).
Rather than detecting the magnetizing ring valley on the primary-
side, the peak voltage of the FORWARD pin voltage as it rises above
the output voltage level is used to gate secondary requests to initiate
the switch “ON” cycle in the primary controller.
The secondary controller detects when the controller enters in
discontinuous-mode and opens secondary cycle request windows
corresponding to minimum switching voltage across the primary
power switch.
Quasi-Resonant (QR) mode is enabled for 20 ms after DCM is detected
or when ring amplitude (pk-pk) >2 V. Afterwards, QR switching is
disabled, at which point switching may occur at any time a secondary
request is initiated.
The secondary controller includes blanking of ~1 ms to prevent false
detection of primary “ON” cycle when the FORWARD pin rings below
ground. See Figure 8.
Peak Power Delivery
Output overload response depends on whether the IS pin is shorted
to ground or the design includes a current sense resistor to set the
overload threshold.
If there is an external current sense resistor on the IS pin, the
InnoSwitch has options to set the overload response in two different
ways.
If the device is configured to have the FEEDBACK pin auto-restart
enabled, once the load current reaches the current limit threshold set
by the IS pin resistor, the output voltage will fold back and auto-
restart will occur once the output voltage falls below the AR threshold
for a time period exceeding the AR timer.
If the device is configured for overload response, once the load
current exceeds the current sense threshold the output voltage does
not fold back. The auto-restart timer will begin and auto-restart
occurs if the load current remains higher than the current sense
threshold for a time period exceeding the AR timer.
PI-8962-040819
No CC with Overload Response
AR when Load > ISVTH for t > tIS(AR)
Constant Current
when VFB(AR) is
enabled
AR when VFB
< VFB(AR) for t(FBAR)
ISVTH Threshold
Load Current
Output Voltage
The two cases where a current sense resistor is included in the
design are shown in the Figure 9 above.
If the IS pin is shorted to the GND pin, the overload response heavily
depends on the operating conditions. If the device is configured to
have feedback auto-restart enabled (VFB(AR)), auto-restart will occur if
the output voltage droops below the auto-restart threshold for longer
than the auto-restart timer (tFB(AR)). Otherwise, the auto-restart
occurs if the primary switches above the overload frequency limit
(fOVL) for longer than the auto-restart on-time (tAR).
14"“?
rh—W
nnnnnnnnnnnn
Rev. M 06/20
9
InnoSwitch3-EP
www.power.com
Figure 10. Schematic DER-611, 5 V, 0.3 A and 12 V, 0.7 A for HVAC (Heating, Ventilation and Air-Conditioning) Application.
Applications Example
The circuit shown in Figure 10 is a low cost 5 V, 0.3 A and 12 V, 0.7 A
dual output power supply using INN3672C. This dual output design
features high efficient design satisfying cross regulation requirement
without a post-regulator.
Bridge rectifier BR1 rectifies the AC input supply. Capacitors C2 and
C3 provide filtering of the rectified AC input and together with
inductor L1 form a pi-filter to attenuate differential mode EMI.
Y capacitor C10 connected between the power supply output and
input help reduce common mode EMI.
Thermistor RT1 limits the inrush current when the power supply is
connected to the input AC supply.
Input fuse F1 provides protection against excess input current
resulting from catastrophic failure of any of the components in the
power supply. One end of the transformer primary is connected to
the rectified DC bus; the other is connected to the drain terminal of
the Switch inside the InnoSwitch3-EP IC (U1).
A low-cost RCD clamp formed by diode D1, resistors R22, R8, and
capacitor C4 limits the peak drain voltage of U1 at the instant of
turn-off of the Switch inside U1. The clamp helps to dissipate the
energy stored in the leakage reactance of transformer T1.
The InnoSwitch3-EP IC is self-starting, using an internal high-voltage
current source to charge the PRIMARY BYPASS pin capacitor (C6)
when AC is first applied. During normal operation the primary-side
block is powered from an auxiliary winding on the transformer T1.
Output of the auxiliary (or bias) winding is rectified using diode D7
and filtered using capacitor C5. Resistor R6 limits the current being
supplied to the PRIMARY BYPASS pin of InnoSwitch3-EP IC (U1). The
latch-off/auto-restart primary-side overvoltage protection is obtained
using Zener diode VR1 with current limiting resistor R26.
The secondary-side controller of the InnoSwitch3-EP IC provides
output voltage sensing, output current sensing and drive to a Switch
providing synchronous rectification. The 5 V secondary of the
transformer is rectified by SR FET Q1 and filtered by capacitor C18.
High frequency ringing during switching transients that would
otherwise create radiated EMI is reduced via a snubber (resistor R24
and capacitor C22). The 12 V secondary of the transformer is rectified
by SR FET Q2 and filtered by capacitor C19. High frequency ringing
during switching transients that would otherwise create radiated EMI
is reduced via a snubber (resistor R25 and capacitor C21).
Synchronous rectifications (SR) are provided by Switchs Q1 and Q2.
Q1 and Q2 are turned on by the secondary-side controller inside IC
U1, based on the winding voltage sensed via resistor R9 and fed into
the FORWARD pin of the IC.
In continuous conduction mode of operation, the Switch is turned off
just prior to the secondary-side’s commanding a new switching cycle
from the primary. In discontinuous conduction mode of operation,
the power switch is turned off when the voltage drop across the
Switch falls below 0 V. Secondary-side control of the primary-side
power switch avoids any possibility of cross conduction of the two
Switchs and provides extremely reliable synchronous rectification.
The secondary-side of the IC is self-powered from either the
secondary winding forward voltage or the output voltage. Capacitor
C7 connected to the SECONDARY BYPASS pin of InnoSwitch3-EP IC
U1, provides decoupling for the internal circuitry.
Total output current is sensed by R12 between the IS and GROUND
pins with a threshold of approximately 35 mV to reduce losses. Once
the current sense threshold is exceeded the device adjusts the
number of switch pulses to maintain a fixed output current.
PI-8374-051818
C4
1000 pF
630 V
C2
10 µF
400 V
C3
10 µF
400 V
C5
22 µF
50 V
C6
4.7 µF
16 V
L1
330 µH
C10
470 pF
250 VAC
C8
330 pF
50 V
C18
560 µF
6.3 V
C12
2.2 µF
25 V
VR2
SMAZ8V2-13-F
8.2 V
C19
680 µF
16 V
C7
2.2 µF
25 V
C14
2.2 µF
25 V
L2
10 µH
L3
10 µH
2
1
FL1
FL2
T1
EE1621
NC
6
5
12 V, 0.7 A
5 V, 0.3 A
12 V
RTN
RTN
R8
200 kΩ
R22
68 Ω
RT1
10 Ω
R9
47 Ω
1/10 W
D1
DFLR1600-7
600 V
D7
DFLR1200-7
D3
BAV21WS-7-F
VR1
MMSZ5231B-7-F
R26
36 Ω
1/10 W
R6
6.2 kΩ
1/10 W
4
3
D V
S IS
GND
SR
VO
FWD
FB
InnoSwitch3-EP
CONTROL
R24
62 Ω
1/8 W
C22
1 nF
200 V
R25
30 Ω
1/8 W
C21
1 nF
200 V
R12
0.2 Ω
1%
R13
33.2 kΩ
1%
1/16 W
R16
133 kΩ
1%
1/16 W
R30
100 Ω
1/10 W
C24
2.2 nF
50 V
R29
100 Ω
1/10 W
C23
2.2 nF
50 V
Q1
AO6420
Q2
AO4486
R27
1.2 MΩ
1%
1/16 W
BPP
BPS
U1
INN3672C-H602
BR1
DF08S
800 V
F1
1 A
90 - 265
VAC
L N
tO
R3
2 MΩ
1%
R4
1.8 MΩ
1%
—power
\ntegmtmnS'
Rev. M 06/20
10
InnoSwitch3-EP
www.power.com
The output voltages are sensed via resistor divider R13, R16, and
R27, and output voltages are regulated so as to achieve a voltage of
1.265 V on the FEEDBACK pin. The 12 V phase boost circuit, R30 and
C24, in parallel with 12 V feedback resistor, R27, and 5 V phase boost
circuit, R29 and C23, in parallel with 5 V feedback resistor, R16,
reduce the output voltage ripples. Capacitor C8 provides noise
filtering of the signal at the FEEDBACK pin. Zener VR2 was added for
tighter cross-regulation to limit the 12 V output when it is unloaded.
Resistors R3 and R4 provide line voltage sensing and provide a current
to U1, which is proportional to the DC voltage across capacitor C3. At
approximately 100 VDC, the current through these resistors exceeds
the line undervoltage threshold, which results in enabling of U1. At
approximately 435 VDC, the current through these resistors exceeds
the line over voltage threshold, which results in disabling of U1.
WA
Ami/k
w—L—qk
nnnnnnnnnnnn
Rev. M 06/20
11
InnoSwitch3-EP
www.power.com
The circuit shown in Figure 11 is a 20 V, 3.25 A adapter using
INN3679C. This design is DOE Level 6 and EC CoC 5 compliant. Fuse
F1 isolates the circuit and provides protection from component
failure, and the common mode choke L1 and L2 with capacitor C1
attenuation for EMI. Bridge rectifier BR1 rectifies the AC line voltage
and provides a full wave rectified DC across the filter capacitor C2.
Capacitor C3 is used to mitigate the common mode EMI.
Resistors R1 and R2 along with U2 discharges capacitor C1 when the
power supply is disconnected from AC mains.
One end of the transformer (T1) primary is connected to the rectified
DC bus; the other is connected to the drain terminal of the switch
inside the InnoSwitch3-EP IC (U1). Resistors R3 and R4 provide input
voltage sense protection for undervoltage and overvoltage conditions.
A low-cost RCD clamp formed by diode D1, resistors R5, R6, and R7,
and capacitor C4 limits the peak drain voltage of U1 at the instant of
turn off of the switch inside U1. The clamp helps to dissipate the
energy stored in the leakage reactance of transformer T1.
The IC is self-starting, using an internal high-voltage current source
to charge the BPP pin capacitor (C6) when AC is first applied. During
normal operation the primary-side block is powered from an auxiliary
winding on the transformer T1. Output of the auxiliary (or bias)
winding is rectified using diode D2 and filtered using capacitor C5.
Resistor R8 limits the current being supplied to the BPP pin of the
InnoSwitch3-EP IC (U1).
Output regulation is achieved using ramp time modulation control,
the frequency and ILIM of switching cycles are adjusted based on the
output load. At high load, most switching cycles are enabled which
have high value of ILIM in the selected ILIM range, and at light load
or no-load most cycles are disabled and the ones enabled have low
value of ILIM in the selected ILIM range. Once a cycle is enabled, the
switch will remain on until the primary current ramps to the device
current limit for the specific operating state.
Zener diode VR1 along with R9 and D3 offers primary sensed output
overvoltage protection. In a flyback converter, output of the auxiliary
winding tracks the output voltage of the converter. In case of
overvoltage at output of the converter, the auxiliary winding voltage
increases and causes breakdown of VR1 which then causes a current
to flow into the BPP pin of InnoSwitch3-EP IC U1. If the current
flowing into the BPP pin increases above the ISD threshold, the U1
controller will latch-off and prevent any further increase in output
voltage.
The secondary-side of the InnoSwitch3-EP IC provides output
voltage, output current sensing and drive to a MOSFET providing
synchronous rectification. The secondary of the transformer is
rectified by SR FET Q1 and filtered by capacitors C8 and C9.
Capacitors C15 and C17 are used to reduce the high frequency output
voltage ripple. High frequency ringing during switching transients
that would otherwise create radiated EMI is reduced via a RCD
snubber R11, C7 and D4. Diode D4 was used to minimize the
dissipation in resistor R11.
The gate of Q1 is turned on by secondary-side controller inside IC U1,
based on the winding voltage sensed via resistor R12 and fed into the
FWD pin of the IC.
In continuous conduction mode of operation, the MOSFET is turned
off just prior to the secondary-side commanding a new switching
cycle from the primary. In discontinuous mode of operation, the
power MOSFET is turned off when the voltage drop across the
MOSFET falls below a threshold of approximately VSR(TH) mV.
Secondary-side control of the primary-side power switch avoids any
possibility of cross conduction of the two switches and provides
extremely reliable synchronous rectification.
The secondary-side of the IC U1 is self-powered from either the
secondary winding forward voltage or the output voltage. Capacitor
C10 connected to the BPS pin of IC U1 provides decoupling for the
internal circuitry. Capacitor C11 provides decoupling for the VO pin.
Below the CC threshold, the device operates in constant voltage
mode. During constant voltage mode operation, output voltage
regulation is achieved through sensing the output voltage via divider
resistors R15 and R16. The voltage across R16 is fed into the FB pin
with an internal reference voltage threshold of 1.265 V. Output
voltage is regulated so as to achieve a voltage of 1.265 V on the FB
pin. Capacitor C13 provides noise filtering of the signal at the FB pin.
Figure 11. 20 V, 3.25 A Notebook Adapter.
2
3
FL1
6
T1
EQ25
4
FL2
D
S IS
GND
SR
VO
FWD
FB
InnoSwitch3-EP
BPP
BPS
U1
INN3679C-H606
C4
2.2 nF
630 V
C6
4.7 µF
16 V
C5
6.8 µF
63 V
C8
330 µF
25 V
C10
2.2 µF
25 V
C11
2.2 µF
25 V
C12
1000 pF
50 V
C9
330 µF
25 V
C15
10 µF
35 V
C16
1 µF
100 V
C13
330 pF
100 V
C2
100 µF
400 V
VR1
MMSZ5242B-7-F
R7
680 kΩ
R6
20 Ω
R5
20 Ω
D1
DFLR1800-7
D2
BAV3004WS-7
300 V
D3
BAV19WS
100 V
R11
10 Ω
C7
1 nF
200 V
C3
680 pF
250 VAC
D4
BAV19WS
100 V
R15
169 kΩ
1%
1/16 W
R16
11.5 kΩ
1%
1/10 W
R13
0.0 Ω
1/10 W
R14
0.009 Ω
1%
1/2 W
R8
3 kΩ
1/10 W
R9
47 Ω
Q1
AON6220
R12
47 Ω
1/10 W
R3
2.00 MΩ
1%
R4
1.80 MΩ
1%
V
CONTROL
BR1
GBL06
600 V
J3
J4
J1
J2
L2
04291-T231
18 mH
L1
250 µH
C1
330 nF
275 VAC
1 2
4 3
1 2
3 4
R1
1 MΩ
R2
1 MΩ
F1
3.15 A
90 - 265
VAC
D2
D1
CAPZero-2
U2
CAP200DG
PI-8770b-012720
EU
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[u
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IHS ||
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power
integrations"
Rev. M 06/20
12
InnoSwitch3-EP
www.power.com
During CC operation, when the output voltage falls, the device will
directly power itself from the secondary winding. During the on-time
of the primary-side power MOSFET, the forward voltage that appears
across the secondary winding is used to charge the decoupling
capacitor C10 via resistor R12 and an internal regulator. This allows
output current regulation to be maintained down to ~3.4 V. Output
current is sensed by monitoring the voltage drop across resistor R14
between the IS and SECONDARY GROUND pins. A threshold of
approximately 35 mV reduces losses. C12 provides filtering on the IS
pin from external noise. Once the internal current sense threshold is
exceeded the device regulates the number of switch pulses to
maintain a fixed output current.
Layout Example
Figure 12. PCB Layout.
PCB - Bottom Side
PI-9112-012820
Maximize source area for good heat sinking.
Keep drain and clamp loop short; keep drain
components away from BPP and V pin circuitry.
Y capacitor connection to the plus bulk rail on the
primary-side for surge protection.
Keep BPP and BPS capacitors near the IC.Place V pin sense resistor
close to the IC.
Maximize drain area of SR FET for good
heat sinking.
Keep IS-GND pin sense
resistor close to output
capacitor and output
connector. Keep IS-
GND pin decoupling
capacitor close to
the IC.
Keep FEEDBACK pin
decoupling capacitor
close to the IC.
Keep output SR FET
and output filter
capacitor loop short.
Place forward and
feedback sense
resistors near the IC.
6.5 mm spark gap.
—power
mtegranons
Rev. M 06/20
13
InnoSwitch3-EP
www.power.com
Key Application Considerations
Output Power Table
The data sheet output power table (Table 1) represents the maximum
practical continuous output power level that can be obtained under
the following conditions:
1. The minimum DC input voltage is 90 V or higher for 85 VAC input,
220 V or higher for 230 VAC input or 115 VAC with a voltage-
doubler. Input capacitor voltage should be sized to meet these
criteria for AC input designs.
2. Efficiency assumptions depend on power level. Smallest device
power level assumes efficiency >84% increasing to >89% for the
largest device (for thermally constrained environment efficiency
should be >92% with larger devices).
3. Transformer primary inductance tolerance of ±10%.
4. Reflected output voltage (VOR) is set to maintain KP = 0.8 at
minimum input voltage for universal line and KP = 1 for high input
line designs.
5. Maximum conduction losses for adapters is limited to 0.6 W, 0.8 W
for open frame designs.
6. Increased current limit is selected for peak and open frame power
columns and standard current limit for adapter columns.
7. The part is board mounted with SOURCE pins soldered to a
sufficient area of copper and/or a heat sink to keep the SOURCE
pin temperature at or below 110 °C.
8. Ambient temperature of 50 °C for open frame designs and 40 °C
for sealed adapters.
9. Below a value of 1, KP is the ratio of ripple to peak primary
current. To prevent reduced power delivery, due to premature
termination of switching cycles, a transient KP limit of ≥0.25 is
recommended. This prevents the initial current limit (IINT) from
being exceeded at Switch turn-on.
Primary-Side Overvoltage Protection (Latch-Off/
Auto-Restart Mode)
Primary-side output overvoltage protection provided by the
InnoSwitch3-EP IC uses an internal protection depending on H Code
that is triggered by a threshold current of ISD into the PRIMARY
BYPASS pin. In addition to an internal filter, the PRIMARY BYPASS pin
capacitor forms an external filter helping noise immunity. For the
bypass capacitor to be effective as a high frequency filter, the
capacitor should be located as close as possible to the SOURCE and
PRIMARY BYPASS pins of the device.
The primary sensed OVP function can be realized by connecting a
series combination of a Zener diode, a resistor and a blocking diode
from the rectified and filtered bias winding voltage supply to the
PRIMARY BYPASS pin. The rectified and filtered bias winding output
voltage may be higher than expected (up to 1.5X or 2X the desired
value) due to poor coupling of the bias winding with the output
winding and the resulting ringing on the bias winding voltage
waveform. It is therefore recommended that the rectified bias
winding voltage be measured. This measurement should be ideally
done at the lowest input voltage and with highest load on the output.
This measured voltage should be used to select the components
required to achieve primary sensed OVP. It is recommended that a
Zener diode with a clamping voltage approximately 6 V lower than the
bias winding rectified voltage at which OVP is expected to be
triggered be selected. A forward voltage drop of 1 V can be assumed
for the blocking diode. A small signal standard recovery diode is
recommended. The blocking diode prevents any reverse current
discharging the bias capacitor during start-up. Finally, the value of
the series resistor required can be calculated such that a current
higher than ISD will flow into the PRIMARY BYPASS pin during an
output overvoltage.
Reducing No-load Consumption
The InnoSwitch3-EP IC can start in self-powered mode, drawing
energy from the BYPASS pin capacitor charged through an internal
current source. Use of a bias winding is however required to provide
supply current to the PRIMARY BYPASS pin once the InnoSwitch3-EP
IC has started switching. An auxiliary (bias) winding provided on the
transformer serves this purpose. A bias winding driver supply to the
PRIMARY BYPASS pin enables design of power supplies with no-load
power consumption less than 15 mW. Resistor R6 shown in Figure 10
should be adjusted to achieve the lowest no-load input power.
Secondary-Side Overvoltage Protection (Auto-Restart Mode)
The secondary-side output overvoltage protection provided by the
InnoSwitch3-EP IC uses an internal auto restart circuit that is
triggered by an input current exceeding a threshold of IBPS(SD) into the
SECONDARY BYPASS pin. The direct output sensed OVP function can
be realized by connecting a Zener diode from the output to the
SECONDARY BYPASS pin. The Zener diode voltage needs to be the
difference between 1.25 × VOUT and 4.4 V − the SECONDARY BYPASS
pin voltage. It is necessary to add a low value resistor in series with
the OVP Zener diode to limit the maximum current into the
SECONDARY BYPASS pin.
Selection of Components
Components for InnoSwitch3-EP
Primary-Side Circuit
BPP Capacitor
A capacitor connected from the PRIMARY BYPASS pin of the
InnoSwitch3-EP IC to GND provides decoupling for the primary-side
controller and also selects current limit. A 0.47 mF or 4.7 mF capacitor
may be used. Though electrolytic capacitors can be used, often
surface mount multi-layer ceramic capacitors are preferred for use on
double sided boards as they enable placement of capacitors close to
the IC. Their small size also makes it ideal for compact power supplies.
At least 10 V, 0805 or larger size rated X5R or X7R dielectric capacitors
are recommended to ensure that minimum capacitance requirements
are met. The ceramic capacitor type designations, such as X7R, X5R
from different manufacturers or different product families do not have
the same voltage coefficients. It is recommended that capacitor data
sheets be reviewed to ensure that the selected capacitor will not have
more than 20% drop in capacitance at 5 V. Do not use Y5U or Z5U /
0603 rated MLCC due to this type of SMD ceramic capacitor has very
poor voltage and temperature coefficient characteristics.
Bias Winding and External Bias Circuit
The internal regulator connected from the DRAIN pin of the Switch to
the PRIMARY BYPASS pin of the InnoSwitch3-EP primary-side
controller charges the capacitor connected to the PRIMARY BYPASS
pin to achieve start-up. A bias winding should be provided on the
transformer with a suitable rectifier and filter capacitor to create a
bias supply that can be used to supply at least 1 mA of current to the
PRIMARY BYPASS pin.
The turns ratio for the bias winding should be selected such that 7 V
is developed across the bias winding at the lowest rated output
voltage of the power supply at the lowest load condition. If the
voltage is lower than this, no-load input power will increase.
power
mtegrauonS'
Rev. M 06/20
14
InnoSwitch3-EP
www.power.com
The bias current from the external circuit should be set to IS1(MAX) to
achieve lowest no-load power consumption when operating the
power supply at 230 VAC input, (VBPP > 5 V). A glass passivated
standard recovery rectifier diode with low junction capacitance is
recommended to avoid the snappy recovery typically seen with fast
or ultrafast diodes that can lead to higher radiated EMI.
An aluminum capacitor of at least 22 mF with a voltage rating 1.2
times greater than the highest voltage developed across the capacitor
is recommended. Highest voltage is typically developed across this
capacitor when the supply is operated at the highest rated output
voltage and load with the lowest input AC supply voltage.
Line UV and OV Protection
Resistors connected from the UNDER/OVER INPUT VOLTAGE pin to
the DC bus enable sensing of input voltage to provide line
undervoltage and overvoltage protection. For a typical universal
input application, a resistor value of 3.8 MW is recommended.
Figure 17 shows circuit configurations that enable either the line UV
or the line OV feature only to be enabled.
InnoSwitch3-EP features a primary sensed OV protection feature that
can be used to latch-off the power supply. Once the power supply is
latched off, it can be reset if the UNDER/OVER INPUT VOLTAGE pin
current is reduced to zero. Once the power supply is latched off,
even after the input supply is turned off, it can take considerable
amount of time to reset the InnoSwitch3-EP controller as the energy
stored in the DC bus will continue to provide current to the controller.
A fast AC reset can be achieved using the modified circuit
configuration shown in Figure 18. The voltage across capacitor CS
reduces rapidly after input supply is disconnected reducing current
into the INPUT VOLTAGE MONITOR pin of the InnoSwitch3-EP IC and
resetting the InnoSwitch3-EP controller.
Primary Sensed OVP (Overvoltage Protection)
The voltage developed across the output of the bias winding tracks
the power supply output voltage. Though not precise, a reasonably
accurate detection of the amplitude of the output voltage can be
achieved by the primary-side controller using the bias winding
voltage. A Zener diode connected from the bias winding output to
the PRIMARY BYPASS pin can reliably detect a secondary overvoltage
fault and cause the primary-side controller to latch-off or auto-restart
depending on H Code. It is recommended that the highest voltage at
the output of the bias winding should be measured for normal steady-
state conditions (at full load and lowest input voltage) and also under
transient load conditions. A Zener diode rated for 1.25 times this
measured voltage will typically ensure that OVP protection will only
operate in case of a fault.
Primary-Side Snubber Clamp
A snubber circuit should be used on the primary-side as shown in
Figure 10. This prevents excess voltage spikes at the drain of the
Switch at the instant of turn-off of the Switch during each switching
cycle though conventional RCD clamps can be used. RCDZ clamps
offer the highest efficiency. The circuit example shown in Figure 10
uses an RCD clamp with a resistor in series with the clamp diode.
This resistor dampens the ringing at the drain and also limits the
reverse current through the clamp diode during reverse recovery.
Standard recovery glass passivated diodes with low junction
capacitance are recommended as these enable partial energy
recovery from the clamp thereby improving efficiency.
Components for InnoSwitch3-EP
Secondary-Side Circuit
SECONDARY BYPASS Pin – Decoupling Capacitor
A 2.2 mF, 10V / X7R or X5R /0805 or larger size multi-layer ceramic
capacitor should be used for decoupling the SECONDARY BYPASS pin
of the InnoSwitch3-EP IC. Since the SECONDARY BYPASS Pin voltage
needs to be 4.4 V earlier than output voltage reaches the regulation
voltage level, the significantly higher BPS capacitor value could lead
to output voltage overshoot during start-up. Values lower than 1.5 mF
may not enough capacitance, which can cause unpredictable operation.
The capacitor must be located adjacent to the IC pins. At least 10 V
is recommended voltage rating to give enough margin from BPS
voltage, and 0805 size is necessary to guarantee the actual value in
operation since the capacitance of ceramic capacitors drops
significantly with applied DC voltage especially with small package
SMD such as 0603. 6.3 V / 0603 / X5U or Z5U type of MLCC is not
recommended for this reason. The ceramic capacitor type designations,
such as X7R, X5R from different manufacturers or different product
families do not have the same voltage coefficients. It is recommended
that capacitor datasheets be reviewed to ensure that the selected
capacitor will not have more than 20% drop in capacitance at 4.4 V.
Capacitors with X5R or X7R dielectrics should be used for best results.
FORWARD Pin Resistor
A 47 W, 5% resistor is recommended to ensure sufficient IC supply
current. A higher or lower resistor value should not be used as it can
affect device operation such as the timing of the synchronous rectifier
drive. Figures 11, 12, 13 and 14 below show examples of unacceptable
and acceptable FORWARD pin voltage waveforms. VD is forward
voltage drop across the SR.
Figure 13. Unacceptable FORWARD Pin Waveform After Handshake with
SR Switch Conduction During Flyback Cycle.
Figure 14. Acceptable FORWARD Pin Waveform After Handshake with
SR Switch Conduction During Flyback Cycle.
0 V
VSR(TH)
VD
PI-8392-051818
0 V
VSR(TH)
VD
PI-8393-051818
mtegranons
—power
Rev. M 06/20
15
InnoSwitch3-EP
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Figure 15. Unacceptable FORWARD Pin Waveform before Handshake with Body
Diode Conduction During Flyback Cycle.
Note:
If t1 + t2 = 1.5 ms ± 50 ns, the controller may fail the handshake and
trigger a primary bias winding OVP latch-off/auto-restart.
Figure 16. Acceptable FORWARD Pin Waveform before Handshake with Body
Diode Conduction During Flyback Cycle.
SR Switch Operation and Selection
Although a simple diode rectifier and filter works for the output, use
of an SR FET enables the significant improvement in operating
efficiency often necessary to meet the European CoC and the U.S.
DoE energy efficiency requirements. The secondary-side controller
turns on the SR FET once the flyback cycle begins. The SR FET gate
should be tied directly to the SYNCHRONOUS RECTIFIER DRIVE pin
of the InnoSwitch3-EP IC (no additional resistors should be connected
in the gate circuit of the SR FET). The SR FET is turned off once the
VDS of the SR FET reaches 0 V.
A FET with 18 mW RDS(ON) is appropriate for a 5 V, 2 A output, and a
FET with 8 mW RDS(ON) is suitable for designs rated with a 12 V, 3 A
output. The SR FET driver uses the SECONDARY BYPASS pin for its
supply rail, and this voltage is typically 4.4 V. A FET with a high
threshold voltage is therefore not suitable; FETs with a threshold
0 V
VSR(TH)
VD
PI-8393-051818
PI-8394-051818
0 V
VSR(TH)
VD
t1t2
voltage of 1.5 V to 2.5 V are ideal although Switchs with a threshold
voltage (absolute maximum) as high as 4 V may be used provided
their data sheets specify RDS(ON) across temperature for a gate voltage
of 4.5 V.
There is a slight delay between the commencement of the flyback
cycle and the turn-on of the SR FET. During this time, the body diode
of the SR FET conducts. If an external parallel Schottky diode is
used, this current mostly flows through the Schottky diode. Once the
InnoSwitch3-EP IC detects end of the flyback cycle, voltage across
SR FET RDS(ON) reaches 0 V, any remaining portion of the flyback cycle
is completed with the current commutating to the body diode of the
SR FET or the external parallel Schottky diode. Use of the Schottky
diode parallel to the SR FET may provide higher efficiency and
typically a 1 A surface mount Schottky diode is adequate. However,
the gains are modest. For a 5 V, 2 A design the external diode adds
~0.1% to full load efficiency at 85 VAC and ~0.2% at 230 VAC.
The voltage rating of the Schottky diode and the SR FET should be at
least 1.4 times the expected peak inverse voltage (PIV) based on the
turns ratio used for the transformer. 60 V rated FETs and diodes are
suitable for most 5 V designs that use a VOR < 60 V, and 100 V rated
FETs and diodes are suitable for 12 V designs.
The interaction between the leakage reactance of the output
windings and the SR FET capacitance (COSS) leads to ringing on the
voltage waveform at the instance of voltage reversal at the winding
due to primary Switch turn-on. This ringing can be suppressed using
an RC snubber connected across the SR FET. A snubber resistor in
the range of 10 W to 47 W may be used (higher resistance values lead
to noticeable drop in efficiency). A capacitance value of
1 nF to 2.2 nF is adequate for most designs.
Output Capacitor
Low ESR aluminum electrolytic capacitors are suitable for use with
most high frequency flyback switching power supplies, though the
use of aluminum-polymer solid capacitors have gained considerable
popularity due to their compact size, stable temperature characteristics,
extremely low ESR and high RMS ripple current rating. These
capacitors enable the design of ultra-compact chargers and adapters.
Typically, 200 mF to 300 mF of aluminum-polymer capacitance per
ampere of output current is adequate. The other factor that
influences choice of the capacitance is the output ripple. Ensure that
capacitors with a voltage rating higher than the highest output
voltage plus sufficient margin be used.
Output Voltage Feedback Circuit
The output voltage FEEDBACK pin voltage is 1.265 V [VFB]. A voltage
divider network should be connected at the output of the power
supply to divide the output voltage such that the voltage at the
FEEDBACK pin will be 1.265 V when the output is at its desired
voltage. The lower feedback divider resistor should be tied to the
SECONDARY GROUND pin. A 300 pF (or smaller) decoupling
capacitor should be connected at the FEEDBACK pin to the
SECONDARY GROUND pin of the InnoSwitch3-EP IC. This capacitor
should be placed close to the InnoSwitch3-EP IC.
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16
InnoSwitch3-EP
www.power.com
Recommendations for Circuit Board Layout
See Figure 19 for a recommended circuit board layout for an
InnoSwitch3-EP based power supply.
Single-Point Grounding
Use a single-point ground connection from the input filter capacitor to
the area of copper connected to the SOURCE pins.
Bypass Capacitors
The PRIMARY BYPASS and SECONDARY BYPASS pin capacitor must
be located directly adjacent to the PRIMARY BYPASS-SOURCE and
SECONDARY BYPASS-SECONDARY GROUND pins respectively and
connections to these capacitors should be routed with short traces.
Primary Loop Area
The area of the primary loop that connects the input filter capacitor,
transformer primary and IC should be kept as small as possible.
Primary Clamp Circuit
A clamp is used to limit peak voltage on the DRAIN pin at turn-off.
This can be achieved by using an RCD clamp or a Zener diode
(~200 V) and diode clamp across the primary winding. To reduce
EMI, minimize the loop from the clamp components to the
transformer and IC.
Thermal Considerations
The SOURCE pin is internally connected to the IC lead frame and
provides the main path to remove heat from the device. Therefore
the SOURCE pin should be connected to a copper area underneath
the IC to act not only as a single point ground, but also as a heat
sink. As this area is connected to the quiet source node, it can be
maximized for good heat sinking without compromising EMI
performance. Similarly for the output SR Switch, maximize the PCB
area connected to the pins on the package through which heat is
dissipated from the SR Switch.
Sufficient copper area should be provided on the board to keep the
IC temperature safely below the absolute maximum limits. It is
recommended that the copper area provided for the copper plane on
PI-8412-081717
Secondary
Control IC
SR FET
Primary FET
and Controller
D V
S IS
VOUT
BPS
FB
GND
SR
BPP
CS
100 nF
FWD
InnoSwitch3-EP
PI-8410-081717
D V
R1
R2
1N4148
S IS
VOUT
BPS
FB
GND
SR
BPP
FWD
InnoSwitch3-EP
+
PI-8411-051818
D V
R1
R2
6.2 V
S IS
VOUT
BPS
FB
GND
SR
BPP
FWD
InnoSwitch3-EP
+
Figure 17. (Top) Line OV Only; (Bottom) Line UV Only.
Figure 18. Fast AC Reset Configuration.
—power
mtegranons
Rev. M 06/20
17
InnoSwitch3-EP
www.power.com
which the SOURCE pin of the IC is soldered is sufficiently large to
keep the IC temperature below 110 °C when operating the power
supply at full rated load and at the lowest rated input AC supply
voltage.
Y Capacitor
The Y capacitor should be placed directly between the primary input
filter capacitor positive terminal and the output positive or return
terminal of the transformer secondary. This routes high amplitude
common mode surge currents away from the IC. Note – if an input
pi-filter (C, L, C) EMI filter is used then the inductor in the filter should
be placed between the negative terminals of the input filter
capacitors.
Output SR Switch
For best performance, the area of the loop connecting the secondary
winding, the output SR Switch and the output filter capacitor, should
be minimized.
ESD
Sufficient clearance should be maintained (>8 mm) between the
primary-side and secondary-side circuits to enable easy compliance
with any ESD / hi-pot requirements.
The spark gap is best placed directly between output positive rail and
one of the AC inputs. In this configuration a 6.4 mm spark gap is
often sufficient to meet the creepage and clearance requirements of
many applicable safety standards. This is less than the primary to
secondary spacing because the voltage across spark gap does not
exceed the peak of the AC input.
Drain Node
The drain switching node is the dominant noise generator. As such
the components connected the drain node should be placed close to
the IC and away from sensitive feedback circuits. The clamp circuit
components should be located physically away from the PRIMARY
BYPASS pin and trace lengths minimized.
The loop area of the loop comprising of the input rectifier filter
capacitor, the primary winding and the IC primary-side Switch should
be kept as small as possible.
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Rev. M 06/20
18
InnoSwitch3-EP
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Layout Example
Figure 19. PCB.
Maximize source
area for good heat
sinking
PCB - Top Side
PCB - Bottom Side
6.4 mm spark gap AC side
directly connected to
input line
SOURCE pin ground
provides heat sink
and shield between
DRAIN and signal
pins circuitry
Place VOLTAGE pin
resistor (R4) and BPP
bypass capacitor (C6)
close to the IC pin
Tight loop area for the
external bias supply with
dedicated ground trace
returned to the bulk
negative
Tight loop area for
the 12 V (1) and
5 V (2) outputs
power train
Feedback lower
resistor (R13) and
decoupling capacitor
(C8) are placed
across FEEDBACK
and GROUND pins
Current sense resistor
(R12) and secondary
bypass capacitor (C7)
are placed across ISENSE
and GROUND pins, BPS
and GROUND pins
respectively
Keep drain and
clamp loop short;
Keep drain
components away
from PRIMARY BYPASS
pin circuitry
PI-8413-091919
In order to increase ESD immunity
and to meet isolation requirement,
no traces are routed beneath the IC
—power
mtegranons
Rev. M 06/20
19
InnoSwitch3-EP
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Recommendations for EMI Reduction
1. Appropriate component placement and small loop areas of the
primary and secondary power circuits help minimize radiated and
conducted EMI. Care should be taken to achieve a compact loop
area.
2. A small capacitor in parallel to the clamp diode on the primary-
side can help reduce radiated EMI.
3. A resistor in series with the bias winding helps reduce radiated EMI.
4. Common mode chokes are typically required at the input of the
power supply to sufficiently attenuate common mode noise.
However, the same performance can be achieved by using shield
windings on the transformer. Shield windings can also be used in
conjunction with common mode filter inductors at input to
improve conducted and radiated EMI margins.
5. Adjusting SR switch RC snubber component values can help
reduce high frequency radiated and conducted EMI.
6. A pi-filter comprising differential inductors and capacitors can be
used in the input rectifier circuit to reduce low frequency
differential EMI.
7. A 1 mF ceramic capacitor connected at the output of the power
supply helps to reduce radiated EMI.
Recommendations for Transformer Design
Transformer design must ensure that the power supply delivers the
rated power at the lowest input voltage. The lowest voltage on the
rectified DC bus depends on the capacitance of the filter capacitor
used. At least 2 mF/W is recommended to always keep the DC bus
voltage above 70 V, though 3 mF/W provides sufficient margin. The
ripple on the DC bus should be measured to confirm the design
calculations for transformer primary-winding inductance selection.
Switching Frequency (fSW)
It is a unique feature in InnoSwitch3-EP that for full load, the designer
can set the switching frequency to between 25 kHz to 95 kHz. For
lowest temperature, the switching frequency should be set to around
60 kHz. For a smaller transformer, the full load switching frequency
needs to be set to 95 kHz. When setting the full load switching
frequency it is important to consider primary inductance and peak
current tolerances to ensure that average switching frequency does
not exceed 110 kHz which may trigger auto-restart due to overload
protection. The following table provides a guide to frequency
selection based on device size. This represents the best compromise
between overall device losses (conduction losses and switching
losses) based on the size of the integrated high-voltage Switch.
INN3672C and INN3673C 85-90 kHz
INN3674C and INN3675C 80 kHz
INN3676C 75 kHz
INN3677C 70 kHz
INN369x 70 kHz
PowiGaN device INN3678C 70 kHz
PowiGaN device INN3679C 65 kHz
PowiGaN device INN3670C 60 kHz
Reflected Output Voltage, VOR (V)
This parameter describes the effect on the primary Switch drain
voltage of the secondary-winding voltage during diode/SR conduction
which is reflected back to the primary through the turns ratio of the
transformer. To make full use of QR capability and ensure flattest
efficiency over line/load, set reflected output voltage (VOR) to
maintain KP = 0.8 at minimum input voltage for universal input and
KP = 1 for high-line-only conditions.
Consider the following for design optimization:
1. Higher VOR allows increased power delivery at VMIN, which
minimizes the value of the input capacitor and maximizes power
delivery from a given InnoSwitch3-EP device.
2. Higher VOR reduces the voltage stress on the output diodes and
SR Switchs.
3. Higher VOR increases leakage inductance which reduces power
supply efficiency.
4. Higher VOR increases peak and RMS current on the secondary-side
which may increase secondary-side copper and diode losses.
There are some exceptions to this. For very high output currents the
VOR should be reduced to get highest efficiency. For output voltages
above 15 V, VOR should be higher to maintain an acceptable PIV across
the output synchronous rectifier.
Ripple to Peak Current Ratio, KP
A KP below 1 indicates continuous conduction mode, where KP is the
ratio of ripple-current to peak-primary-current (Figure 20).
KP ≡ KRP = IR / IP
A value of KP higher than 1, indicates discontinuous conduction mode.
In this case KP is the ratio of primary Switch off-time to the secondary
diode conduction-time.
KP ≡ KDP = (1 – D) x T/ t = VOR × (1 – DMAX) / ((VMIN – VDS) × DMAX)
It is recommended that a KP close to 0.9 at the minimum expected DC
bus voltage should be used for most InnoSwitch3-EP designs. A KP
value of <1 results in higher transformer efficiency by lowering the
primary RMS current but results in higher switching losses in the
primary-side Switch resulting in higher InnoSwitch3-EP temperature.
The benefits of quasi-resonant switching start to diminish for a
further reduction of KP.
For a typical USB PD and rapid charge designs which require a wide
output voltage range, KP will change significantly as the output
voltage changes. KP will be high for high output voltage conditions
and will drop as the output voltage is lowered. The PIXls spreadsheet
can be used to effectively optimize selection of KP, inductance of the
primary winding, transformer turns ratio, and the operating frequency
while ensuring appropriate design margins.
Core Type
Choice of a suitable core is dependent on the physical limits of the
power supply enclosure. It is recommended that only cores with low
loss be used to reduce thermal challenges.
Safety Margin, M (mm)
For designs that require safety isolation between primary and
secondary that are not using triple insulated wire, the width of the
safety margin to be used on each side of the bobbin is important.
For universal input designs a total margin of 6.2 mm is typically
required − 3.1 mm being used on either side of the winding. For
vertical bobbins the margin may not be symmetrical. However if a
total margin of 6.2 mm is required then the physical margin can be
placed on only one side of the bobbin. For designs using triple
insulated wire it may still be necessary to add a small margin in order
to meet required creepage distances. Many bobbins exist for each
core size and each will have different mechanical spacing. Refer to
the bobbin data sheet or seek guidance to determine what specific
margin is required. As the margin reduces the available area for the
windings, the winding area will disproportionately reduce for small
core sizes.
It is recommended that for compact power supply designs using an
InnoSwitch3-EP IC, triple insulated wire should be used.
— W r
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InnoSwitch3-EP
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Primary Layers, L
Primary layers should be in the range of 1 ≤ L ≤ 3 and in general
should be the lowest number that meets the primary current density
limit (CMA). A value of ≥200 Cmils / Amp can be used as a starting
point for most designs. Higher values may be required due to
thermal constraints. Designs with more than 3 layers are possible but
the increased leakage inductance and the physical fit of the windings
should be considered. A split primary construction may be helpful for
designs where clamp dissipation due to leakage inductance is too
high. In split primary construction, half of the primary winding is
placed on either side of the secondary (and bias) winding in a
sandwich arrangement. This arrangement is often disadvantageous
for low power designs as this typically increases common mode noise
and adds cost to the input filtering.
Maximum Operating Flux Density, BM (Gauss)
A maximum value of 3800 gauss at the peak device current limit
(at 132 kHz) is recommended to limit the peak flux density at start-up
and under output short-circuit conditions. Under these conditions the
output voltage is low and little reset of the transformer occurs during
the Switch off-time. This allows the transformer flux density to
staircase beyond the normal operating level. A value of 3800 gauss
at the peak current limit of the selected device together with the
built-in protection features of InnoSwitch3-EP IC provide sufficient
margin to prevent core saturation under start-up or output short-
circuit conditions.
KP ≡ KRP =
(a) Continuous, KP < 1
(b) Borderline Continuous/Discontinuous, KP = 1
IR
IP
IPIR
IP
IR
PI-2587-103114
Primary
Primary
Figure 20. Continuous Conduction Mode Current Waveform, KP < 1.
KP ≡ KDP =
T = 1/fS
T = 1/fS
(1-D) × T
(1-D) × T = t
t
D × T
D × T
(b) Borderline Discontinuous/Continuous, KP = 1
(a) Discontinuous, KP > 1
Primary
Secondary
Primary
Secondary
PI-2578-103114
(1-D) × T
t
Figure 21. Discontinuous Conduction Mode Current Waveform, KP > 1.
‘EiSQ’r‘éEEs -
Rev. M 06/20
21
InnoSwitch3-EP
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Transformer Primary Inductance, LP
Once the lowest operating input voltage, switching frequency at full
load, and required VOR are determined, the transformers primary
inductance can be calculated. The PIXls design spreadsheet can be
used to assist in designing the transformer.
Quick Design Checklist
As with any power supply, the operation of all InnoSwitch3-EP
designs should be verified on the bench to make sure that component
limits are not exceeded under worst-case conditions.
As a minimum, the following tests are strongly recommended:
1. Maximum Drain Voltage – Verify that VDS of InnoSwitch3-EP and
SR FET do not exceed 90% of breakdown voltages at the highest
input voltage and peak (overload) output power in normal
operation and during start-up.
2. Maximum Drain Current – At maximum ambient temperature,
maximum input voltage and peak output (overload) power.
Review drain current waveforms for any signs of transformer
saturation or excessive leading-edge current spikes at start-up.
Repeat tests under steady-state conditions and verify that the
leading edge current spike is below ILIMIT(MIN) at the end of tLEB(MIN).
Under all conditions, the maximum drain current for the primary
Switch should be below the specified absolute maximum ratings.
3. Thermal Check – At specified maximum output power, minimum
input voltage and maximum ambient temperature, verify that
temperature specification limits for InnoSwitch3-EP IC,
transformer, output SR FET, and output capacitors are not
exceeded. Enough thermal margin should be allowed for
part-to-part variation of the RDS(ON) of the InnoSwitch3-EP IC.
Under low-line, maximum power, a maximum InnoSwitch3-EP
SOURCE pin temperature of 110 °C is recommended to allow for
these variations.
Design Considerations When Using PowiGaN
Devices (INN3678C, INN3679C and INN3670C)
For a flyback converter configuration, typical voltage waveform at the
DRAIN pin of the IC is shown in Figure 22.
VOR is the reflected output voltage across the primary winding when
the secondary is conducting. VBUS is the DC voltage connected to one
end of the transformer primary winding.
In addition to VBUS+VOR, the drain also sees a large voltage spike at
turn off that is caused by the energy stored in the leakage inductance
of the primary winding. To keep the drain voltage from exceeding the
rated maximum continuous drain voltage, a clamp circuit is needed
across the primary winding. The forward recovery of the clamp diode
will add a spike at the instant of turn-OFF of the primary switch. VCLM
in Figure 22 is the combined clamp voltage including the spike. The
peak drain voltage of the primary switch is the total of VBUS, VOR and VCLM.
VOR and the clamp voltage VCLM should be selected such that the peak
drain voltage is lower than 650 V for all normal operating conditions.
This provides sufficient margin to ensure that occasional increase in
voltage during line transients such as line surges will maintain the
peak drain voltage well below 750 V under abnormal transient
operating conditions. This ensures excellent long term reliability and
design margin.
To make full use of QR capability and ensure flattest efficiency over
line/load, set reflected output voltage (VOR) to maintain KP = 0.8 at
minimum input voltage for universal input and KP ≥ 1 for high-line-
only conditions.
Consider the following for design optimization:
1. Higher VOR allows increased power delivery at VMIN, which
minimizes the value of the input capacitor and maximizes power
delivery from a given PowiGaN INN3678C, INN3679C and
INN3670C device.
2. Higher VOR reduces the voltage stress on the output diodes and
SR FETs.
3. Higher VOR increases leakage inductance which reduces power
supply efficiency.
4. Higher VOR increases peak and RMS current on the secondary-side
which may increase secondary-side copper and diode losses.
There are some exceptions to this. For very high output currents the
VOR should be reduced to get highest efficiency. For output voltages
above 15 V, VOR should be maintained higher to maintain an
acceptable PIV across the output synchronous rectifier.
VOR choice will affect the operating efficiency and should be selected
carefully. Table below shows the typical range of VOR for optimal
performance:
Output Voltage Optimal Range for VOR
5 V 45 - 70
12 V 80 - 120
15 V 100 - 135
20 V 120 - 150
24 V 135 - 180
Figure 22. Peak Drain Voltage for 264 VAC Input Voltage.
Typical margin (150 V)
gives de-rating of >80%
Safe Surge Voltage
Region (SSVR)
VCLM
750 V = VMAX(NON-REPETITIVE)
650 V = VMAX(CONTINUOUS)
Primary Switch Voltage Stress (264 VAC)
380 VDC
VOR
VBUS
PI-8769-071218
power
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InnoSwitch3-EP
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Thermal resistance value is for primary power device junction to
ambient only.
Testing performed on custom thermal test PCB as shown in the figure
above. The test board consists of 2 layers of 2 oz. Cu with the InSOP
package mounted to the top surface and connected to a bottom layer
Cu heatsinking area of 550mm
2
.
Connection between the two layers was made by 82 vias in a 5 x 17
matrix outside the package mounting area. Vias are spaced at 40 mils,
with 12 mil diameter and plated through holes are not filled.
Figure xx. Thermal Resistance Test Conditions for INN3379C and INN3370C
Figure 23. Ther3mal Resistance Test Conditions for PowiGaN
Devices (INN3678C, INN3679C and INN3670C.)
Thermal Resistance Test Conditions for
PowiGaN Devices (INN3678C, INN3679C and
INN3670C)
Thermal resistance value is for primary power device junction to
ambient only.
Testing performed on custom thermal test PCB as shown in Figure 23.
The test board consists of 2 layers of 2 oz. Cu with the InSOP
package mounted to the top surface and connected to a bottom layer
Cu heat sinking area of 550 mm2.
Connection between the two layers was made by 82 vias in a 5 x 17
matrix outside the package mounting area. Vias are spaced at
40 mils, with 12 mil diameter and plated through holes are not filled.
—power
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InnoSwitch3-EP
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Absolute Maximum Ratings1,2
DRAIN Pin Voltage: INN3672C - INN3677C ................. -0.3 V to 725 V
INN3678C - INN3670C ................ -0.3 V to 750 V7
INN369x .....................................-0.3 V to 900 V
DRAIN Pin Peak Current: INN3672C .......................................1.70 A3
INN3673C ....................................... 2.38 A3
INN3674C ....................................... 3.47 A3
INN3675C ....................................... 4.11 A3
INN3676C ....................................... 5.19 A3
INN3677C .......................................5.92 A3
PowiGaN device INN3678C ................6.5 A8
PowiGaN device INN3679C .................10 A8
PowiGaN device INN3670C .................14 A8
INN3692C .........................................2.2 A4
INN3694C .......................................3.96 A4
INN3696C ....................................... 5.72 A4
BPP/BPS Pin Voltage ........................................................-0.3 to 6 V
BPP/BPS Current ................................................................. 100 mA
FWD Pin Voltage ...................................................... -1.5 V to 150 V
FB Pin Voltage .............................................................-0.3 V to 6 V
SR Pin Voltage .............................................................-0.3 V to 6 V
VOUT Pin Voltage .......................................................-0.3 V to 27 V
V Pin Voltage ............................................................ -0.3 V to 725 V
IS Pin Voltage9 .......................................................... -0.3 V to 0.3 V
Storage Temperature ...................................................-65 to 150 °C
Operating Junction Temperature5 ................................ -40 to 150 °C
Ambient Temperature...................................................-40 to 105 °C
Lead Temperature6................................................................ 260 °C
NOTES:
1. All voltages referenced to SOURCE and Secondary GROUND,
TA = 25 °C.
2. Maximum ratings specified may be applied one at a time without
causing permanent damage to the product. Exposure to Absolute
Maximum Ratings conditions for extended periods of time may
affect product reliability.
3. Please refer to Figure 24 about maximum allowable voltage and
current combinations.
4. Please refer to Figure 30 about maximum allowable voltage and
current combinations.
5. Normally limited by internal circuitry.
6. 1/16” from case for 5 seconds.
7. PowiGaN devices:
Maximum drain voltage (non-repetitive pulse) .........-0.3 V to 750 V
Maximum continuous drain voltage ........................-0.3 V to 650 V
8. Please refer to Figures 38 for maximum allowable voltage and
current combinations.
9. Absolutely maximum voltage for less than 500 msec is 3 V.
Thermal Resistance
Thermal Resistance: INN3672C to INN3677C & INN3692C to INN3696C
(qJA) .................................... 76 °C/W1, 65 °C/W2
(qJC) ..................................................... 8 °C/W3
PowiGan devices INN3678C to INN3670C
(qJA) ................................................... 50 °C/W4
Notes:
1. Soldered to 0.36 sq. inch (232 mm2) 2 oz. (610 g/m2) copper clad.
2. Soldered to 1 sq. inch (645 mm2), 2 oz. (610 g/m2) copper clad.
3. The case temperature is measured on the top of the package.
4. Please see Figure 23.
Parameter Conditions Rating Units
Ratings for UL1577
Primary-Side
Current Rating Current from pin (16-19) to pin 24 1.5 A
Primary-Side
Power Rating
TAMB = 25 °C
(device mounted in socket resulting in TCASE = 120 °C) 1.35 W
Secondary-Side
Power Rating
TAMB = 25 °C
(device mounted in socket) 0.125 W
Package Characteristics
Clearance 12.1 mm (typ)
Creepage 11.7 mm (typ)
Distance Through
Insulation (DTI) 0.4 mm (min)
Transient Isolation
Voltage 6 kV (min)
Comparative Tracking
Index (CTI) 600 -
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24
InnoSwitch3-EP
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Parameter Symbol
Conditions
SOURCE = 0 V
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Min Typ Max Units
Control Functions
Startup Switching
Frequency fSW TJ = 25 °C 23 25 27 kHz
Jitter Frequency fM
TJ = 25 °C
fSW = 100 kHz 0.80 1.25 1.70 kHz
Maximum On-Time tON(MAX) TJ = 25 °C 12.4 14.6 16.9 ms
Minimum Primary
Feedback Block-Out
Timer
tBLOCK tOFF(MIN) ms
BPP Supply Current
IS1
VBPP = VBPP + 0.1 V
(Switch not Switching)
TJ = 25 °C
INN36xxC 145 200 300 mA
INN3678C -
INN3670C 145 266 425 mA
IS2
VBPP = VBPP + 0.1 V
(Switch Switching at
132 kHz)
TJ = 25 °C
INN3672C 0.33 0.44 0.60
mA
INN3673C 0.36 0.48 0.65
INN3674C 0.44 0.58 0.83
INN3675C 0.59 0.79 1.10
INN3676C 0.77 1.02 1.38
INN3677C 0.90 1.20 1.73
INN3692C 0.33 0.44 0.60
INN3694C 0.44 0.58 0.85
INN3696C 0.7 0.90 1.35
INN3678C 0.93 1.24 1.79
INN3679C -
INN3670C 1.46 1.95 2.81
BPP Pin Charge Current
ICH1 VBP = 0 V, TJ = 25 °C -1.75 -1.35 -0.88
mA
ICH2 VBP = 4 V, TJ = 25 °C -5.98 -4.65 -3.32
BPP Pin Voltage VBPP 4.65 4.90 5.15 V
BPP Pin Voltage
Hysteresis VBPP(H) TJ = 25 °C 0.39 V
BPP Shunt Voltage VSHUNT IBPP = 2 mA 5.15 5.36 5.65 V
BPP Power-Up Reset
Threshold Voltage VBPP(RESET) TJ = 25 °C 2.80 3.15 3.50 V
UV/OV Pin Brown-In
Threshold IUV+ TJ = 25 °C
INN36xxC 23.9 26.1 28.2
mA
INN3678C -
INN3670C 22.4 24.4 26.7
UV/OV Pin Brown-Out
Threshold IUV- TJ = 25 °C
INN36xxC 21.0 23.7 25.5
mA
INN3678C -
INN3670C 19 21.6 23.5
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InnoSwitch3-EP
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Parameter Symbol
Conditions
SOURCE = 0 V
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Min Typ Max Units
Control Functions (cont.)
Brown-Out Delay Time tUV- TJ = 25 °C 35 ms
UV/OV Pin Line
Overvoltage Threshold IOV+ TJ = 25 °C
INN36xxC 106 115 118
mA
INN3678C -
INN3670C 106 112 118
UV/OV Pin Line
Overvoltage Hysteresis IOV(H) TJ = 25 °C
INN36xxC 7
mA
INN3678C -
INN3670C 8
UV/OV Pin Line
Overvoltage Recovery
Threshold
IOV- TJ = 25 °C 100 mA
Line Fault Protection
VOLTAGE Pin Line Over-
voltage Deglitch Filter tOV+
TJ = 25 °C
See Note B 3ms
VOLTAGE Pin
Voltage Rating VVTJ = 25 °C 650 V
Circuit Protection
Standard Current Limit
(BPP) Capacitor =
0.47 mF
See Note C
ILIMIT
di/dt = 138 mA/ms
TJ = 25 °C INN3672C 418 450 482
mA
di/dt = 163 mA/ms
TJ = 25 °C INN3673C 511 550 589
di/dt = 188 mA/ms
TJ = 25 °C INN3674C 697 750 803
di/dt = 213 mA/ms
TJ = 25 °C INN3675C 883 950 1017
di/dt = 238 mA/ms
TJ = 25 °C INN3676C 1162 1250 1338
di/dt = 300 mA/ms
TJ = 25 °C INN3677C 1255 1350 1445
di/dt = 375 mA/ms
TJ = 25 °C INN3678C 1581 1700 1819
di/dt = 425 mA/ms
TJ = 25 °C INN3679C 1767 1900 2033
di/dt = 525 mA/ms
TJ = 25 °C INN3670C 2139 2300 2461
di/dt = 138 mA/ms
TJ = 25 °C INN3692C 416 450 483
di/dt = 188 mA/ms
TJ = 25 °C INN3694C 693 750 806
di/dt = 238 mA/ms
TJ = 25 °C INN3696C 1156 1250 1344
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Rev. M 06/20
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InnoSwitch3-EP
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Parameter Symbol
Conditions
SOURCE = 0 V
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Min Typ Max Units
Circuit Protection (cont.)
Increased Current Limit
(BPP) Capacitor =
4.7 mF
See Note C
IL I MI T+1
di/dt = 138 mA/ms
TJ = 25 °C INN3672C 500 550 600
mA
di/dt = 163 mA/ms
TJ = 25 °C INN3673C 591 650 709
di/dt = 188 mA/ms
TJ = 25 °C INN3674C 864 950 1036
di/dt = 213 mA/ms
TJ = 25 °C INN3675C 1046 1150 1254
di/dt = 238 mA/ms
TJ = 25 °C INN3676C 1319 1450 1581
di/dt = 300 mA/ms
TJ = 25 °C INN3677C 1410 1550 1689
di/dt = 375 mA/ms
TJ = 25 °C INN3678C 1767 1900 2033
di/dt = 425 mA/ms
TJ = 25 °C INN3679C 1980 2130 2279
di/dt = 525 mA/ms
TJ = 25 °C INN3670C 2395 2576 2756
di/dt = 138 mA/ms
TJ = 25 °C INN3692C 495 550 605
di/dt = 188 mA/ms
TJ = 25 °C INN3694C 855 950 1045
di/dt = 238 mA/ms
TJ = 25 °C INN3696C 1305 1450 1595
Overload Detection
Frequency fOVL TJ = 25 °C 102 110 118 kHz
BYPASS Pin Latching
Shutdown Threshold
Current
ISD TJ = 25 °C 6.0 7.5 11.3 mA
Auto-Restart On-Time tAR TJ = 25 °C 75 82 89 ms
Auto-Restart Trigger
Skip Time tAR(SK)
TJ = 25 °C
See Note A 1.3 sec
Auto-Restart Off-Time tAR(OFF) TJ = 25 °C 1.7 2.11 sec
Short Auto-Restart
Off-Time tAR(OFF)SH TJ = 25 °C 0.17 0.20 0.23 sec
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InnoSwitch3-EP
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Parameter Symbol
Conditions
SOURCE = 0 V
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Min Typ Max Units
Output
ON-State Resistance RDS(ON)
INN3672C
ID = IL I MI T+1
TJ = 25 °C 6.30 7. 25
W
TJ = 100 °C 9.77 11.24
INN3673C
ID = IL I MI T+1
TJ = 25 °C 4.42 5.08
TJ = 100 °C 6.85 7.88
INN3674C
ID = IL I MI T+1
TJ = 25 °C 3.22 3.70
TJ = 100 °C 4.99 5.74
INN3675C
ID = IL I MI T+1
TJ = 25 °C 1.95 2.24
TJ = 100 °C 3.02 3.47
INN3676C
ID = IL I MI T+1
TJ = 25 °C 1.34 1.54
TJ = 100 °C 2.08 2.39
INN3677C
ID = IL I MI T+1
TJ = 25 °C 1.20 1.38
TJ = 100 °C 1.86 2.14
INN3678C
ID = IL I MI T+1
TJ = 25 °C 0.52 0.68
TJ = 100 °C 0.78 1.02
INN3679C
ID = IL I MI T+1
TJ = 25 °C 0.35 0.44
TJ = 100 °C 0.49 0.62
INN3670C
ID = IL I MI T+1
TJ = 25 °C 0.29 0.39
TJ = 100 °C 0.41 0.54
INN3692C
ID = IL I MI T+1
TJ = 25 °C 6.0 7.2
TJ = 100 °C 9.5 11.2
INN3694C
ID = IL I MI T+1
TJ = 25 °C 3.5 4.1
TJ = 100 °C 5.2 6.0
INN3696C
ID = IL I MI T+1
TJ = 25 °C 2.35 2.8
TJ = 100 °C 3.4 4.2
OFF-State Drain
Leakage Current
IDSS1
VBPP = VBPP + 0.1 V
VDSS = 80% Peak Drain Voltage
TJ = 125 °C
200 mA
IDSS2
VBPP = VBPP + 0.1 V
VDSS = 325 V
TJ = 25 °C
15 mA
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Rev. M 06/20
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InnoSwitch3-EP
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Parameter Symbol
Conditions
SOURCE = 0 V
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Min Typ Max Units
Output (cont.)
Drain Supply Voltage 50 V
Thermal Shutdown TSD See Note A 135 142 150 °C
Thermal Shutdown
Hysteresis TSD(H) See Note A 70 °C
Secondary
Feedback Pin Voltage VFB TJ = 25 °C 1.25 1.265 1.280 V
Maximum Switching
Frequency fSREQ TJ = 25 °C 118 132 145 kHz
FEEDBACK Pin
Auto-Restart Threshold VFB(AR) 90 %
FEEDBACK and IS Pin
Auto-Restart Timer
tFB(AR)
tIS(AR)
TJ = 25 °C 49.5 ms
BPS Pin Current at
No-Load ISNL TJ = 25 °C 325 485 mA
BPS Pin Voltage VBPS 4.20 4.40 4.60 V
BPS Pin Undervoltage
Threshold VBPS(UVLO)(TH) 3.60 3.80 4.00 V
BPS Pin Undervoltage
Hysteresis VBPS(UVLO)(H) 0.65 V
Current Limit
Voltage Threshold ISV(TH)
Set By External Resistor
TJ = 25 °C 35.17 35.90 36.62 mV
FWD Pin Voltage VFWD 150 V
Minimum Off-Time tOFF(MIN) 2.48 3.38 4.37 ms
Soft-Start Frequency
Ramp Time tSS(RAMP) TJ = 25 °C 7.5 11.8 19.0 ms
BPS Pin Latch/
Auto-Restart Command
Shutdown Threshold
Current
IBPS(SD) 5.2 8.9 12 mA
FEEDBACK Pin
Short-Circuit VFB(OFF) TJ = 25 °C 112 135 mV
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InnoSwitch3-EP
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Parameter Symbol
Conditions
SOURCE = 0 V
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Min Typ Max Units
Synchronous Rectifier @ TJ = 25 °C
SR Pin Drive Voltage VSR 4.2 4.4 4.6 V
SR Pin Voltage
Threshold VSR(TH) -2.5 0mV
SR Pin Pull-Up Current ISR(PU)
TJ = 25 °C
CLOAD = 2 nF, fSW = 100 kHz 125 165 195 mA
SR Pin Pull-Down
Current ISR(PD)
TJ = 25 °C
CLOAD = 2 nF, fSW = 100 kHz 87 97 115 mA
Rise Time tR
TJ = 25 °C
CLOAD = 2 nF
See Note B
10-90% 50 ns
Fall Time tF
TJ = 25 °C
CLOAD = 2 nF
See Note B
90-10% 80 ns
Output Pull-Up
Resistance RPU
TJ = 25 °C
VBPS = 4.4 V
ISR = 10 mA
7.2 8.3 12 W
Output Pull-Down
Resistance RPD
TJ = 25 °C
VBPS = 4.4 V
ISR = 10 mA
10.0 12.1 15 W
NOTES:
A. This parameter is derived from characterization.
B. This parameter is guaranteed by design.
C. To ensure correct current limit it is recommended that nominal 0.47 mF / 4.7 mF capacitors are used. In addition, the BPP capacitor value
tolerance should be equal or better than indicated below across the ambient temperature range of the target application. The minimum and
maximum capacitor values are guaranteed by characterization.
Nominal BPP Pin
Capacitor Value
BPP Capacitor Value Tolerance
Minimum Maximum
0.47 mF-60% +10 0 %
4.7 mF-50% N/A
Recommended to use at least 10 V / 0805 / X7R SMD MLCC.
1.4 ‘
42:.
Drain Current (A)
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InnoSwitch3-EP
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Typical Performance Curves
Figure 24. Maximum Allowable Drain Current vs. Drain Voltage
(INN3672-INN3677).
Time (ns)
SYNCHRONOUS RECTIFIER DRIVE
Pin Voltage Limits (V)
PI-7474-011215
500 ns
-0.0
VSR(t)
-0.3
-1.8
Drain Voltage (V)
Drain Capacitance (pF)
PI-8426-090117
1 100 200 300 400 500 600
1
10
1000
100
10000
INN3672 1.00
INN3673 1.40
INN3674 1.95
INN3675 3.20
INN3676 4.60
INN3677 5.20
Scaling Factors:
Drain Voltage (V)
Drain Current (A)
0 2 4 6 8 10
TCASE = 25 °C
TCASE = 100 °C
PI-8427-121418
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0
INN3672 1.00
INN3673 1.40
INN3674 1.95
INN3675 3.20
INN3676 4.60
INN3677 5.20
Scaling Factors:
Drain Voltage (V)
Power (mW)
PI-8428-090117
0 100 200 300 400 500 600
0
25
75
50
100
Switching Frequency = 100 kHz
INN3672 1.00
INN3673 1.40
INN3674 1.95
INN3675 3.20
INN3676 4.60
INN3677 5.20
Scaling Factors:
Figure 25. Output Characteristics.
Figure 26. COSS vs. Drain Voltage. Figure 27. Drain Capacitance Power.
Figure 28. SYNCHRONOUS RECTIFIER DRIVE Pin Negative
Voltage.
Figure 29. Standard Current Limit vs. di/dt.
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1 2 3 4
Normalized di/dt
PI-8432-090717
Normalized Current Limit
Normalized
di/dt = 1
Note: For the
normalized current
limit value, use the
typical current limit
specified for the
appropriate BP/M
capacitor.
Drain Voltage (V)
Drain Current (A)
(Normalized to Absolute
Maximum Current Rating)
PI-8966-042919
0 100 200 300 400 500 700600 800
0.0
0.25
0.50
0.75
1.0
\\
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InnoSwitch3-EP
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Typical Performance Curves
Figure 30. Maximum Allowable Drain Current vs. Drain Voltage
(INN369x). Figure 31. Output Characteristics.
Figure 32. COSS vs. Drain Voltage. Figure 33. Drain Capacitance Power.
Figure 34. Breakdown vs. Temperature (Exclude INN3678C /
INN3679C / INN3670C).
Drain Voltage (V)
Drain Current (A)
(Normalized to Absolute
Maximum Current Rating)
PI-8900-042919
0 100 200 300 400 500 700600 800 900 1000
0.0
1.0
0.75
0.50
0.25
2.5
2
1.5
1
0.5
0
0 1 2 3 4 5 6 7 8 9 10
Drain Voltage (V)
PI-8959-040519
Drain Current (A)
T = 25 °C
T = 100 °C
INN3692 0.5
INN3694 1.0
INN3696 1.5
Scaling Factors:
Drain Voltage (V)
Drain Capacitance (pF)
PI-8960-040519
1 100 200 300 400 500 600
1
10
1000
100
10000
INN3692 0.5
INN3694 1.0
INN3696 1.5
Scaling Factors:
Drain Voltage (V)
Power (mW)
PI-8961-040519
0 100 200 300 400 500 600
0
50
100
200
250
150
300
Switching Frequency = 100 kHz
INN3692 0.5
INN3694 1.0
INN3694 1.5
Scaling Factors:
1.1
1.0
0.9
Breakdown Voltage
(Normalized to 25 °C)
PI-2213-021518
Junction Temperature (°C)
-50 -25 0 25 50 75 100 125 150
Drain Voltage (V)
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InnoSwitch3-EP
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Typical Performance Curves
Figure 36. COSS vs. Drain Voltage.
Figure 35. Output Characteristics.
Figure 37. Drain Capacitance Power. Figure 38. Maximum Allowable Drain Current vs. Drain Voltage
(PowiGaN Devices INN3678C / INN3679C /
INN3670C).
Drain Voltage (V)
Drian Current (A)
PI-8851m-012720
10 100 1000
0.001
0.01
1
10
0.1
100
INN3678C 0.65
INN3679C 1.0
INN3670C 1.4
Scaling Factors:
Drain Voltage (V)
Drain Capacitance (pF)
PI-8852l-110719
15050 250 350 450 5500
10
100
1000
10000
INN3678C 0.62
INN3679C 1.0
INN3670C 1.4
Scaling Factors:
Drain Voltage VDS (V)
Drain Current IDS (A)
0 2 4 6 8 10
TCASE = 25 °C
TCASE = 100 °C
PI-8853l-110719
5
15
10
20
25
0
INN3678C 0.62
INN3679C 1.0
INN3670C 1.4
Scaling Factors:
Drain Voltage (V)
Power (mW)
PI-8854l-110719
0 100 200 300 400 500
0
50
200
100
150
250
INN3678C 0.62
INN3679C 1.0
INN3670C 1.4
Scaling Factors:
Rev. M 06/20
33
InnoSwitch3-EP
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5 Lead Tips
12 Lead Tips
Pin #1 I.D.
16X
0.50 [0.020] Ref. 0.20 [0.008] Ref.
0.25 [0.010] 0.45 [0.018]
Ref.
Seating Plane
Coplanarity: 17 Leads
Body Thickness
Seating
Plane
C
Standoff
Gauge
Plane
3.35 [0.132] Ref.
10.80 [0.425] 13.43 [0.529]
9.40 [0.370]
0.15 [0.006] C
0.10 [0.004] C
0.15 [0.006] C
0.10 [0.004] C A
0.75 [0.030]
0.25 [0.010] M C A B
0.10 [0.004] C B
0.81 0.032
0.51 0.020
0.25 0.010
0.10 0.004
1.45 0.057
1.25 0.049
0.30 0.012
0.18 0.007
1.32 [0.052] Ref.
Detail A
3
17X
0.30 0.012
0.20 0.008
2.71 0.107
2.59 0.102
12
34
1
2
24
2X 13
3 4
2
H
C
2X
A
TOP VIEW BOTTOM VIEW
SIDE VIEW END VIEW PCB PAD LAYOUT
DETAIL A
0° – 8°
1.60 [0.063] Max.
Total Mounting Height
Notes:
1. Dimensioning and Tolerancing per ASME Y14.5M – 1994.
2. Dimensions noted are determined at the outermost extremes of the plastic body exculsive of mold flash, tie bar burrs, gate burrs, and interlead flash,
but including any mismatch between the top and bottom of the plastic body. Maximum mold protrusion is 0.18 [0.007] per side.
3. Dimensions noted are inclusive of plating thickness.
4. Does not include inter-lead flash or protrusions.
5. Controlling dimensions in millimeters [inches].
6. Datums A & B to be determined at Datum H. PI-8106-052620
POD-InSOP-24D Rev B
InSOP-24D
4.80
[0.189]
7.50
[0.295]
8.25
[0.325]
6.75
[0.266]
12.72
[0.501]
0.75
[0.030]
0.41
[0.016]
1.58
[0.062]
1.58
[0.062]
2.81
[0.111]
8.25
[0.325]
- wer
PHSQWS.
Rev. M 06/20
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InnoSwitch3-EP
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PI-8727-050418
InSOP-24D
A. Power Integrations Registered Trademark
B. Assembly Date Code (last two digits of year followed by 2-digit work week)
C. Product Identification (Part #/Package Type)
D. Lot Identification Code
E. Test Sublot and Feature Code
PACKAGE MARKING
AB
E
C
D
INN3676C
M6J542A
1738
1 Hxxx
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ESD and Latch-Up Table
Test Conditions Results
Latch-up at 125 °C JESD78D > ±100 mA or > 1.5 × VMAX on all pins
Human Body Model ESD ANSI/ESDA/JEDEC JS-001-2014 > ±2000 V on all pins
Charge Device Model ESD ANSI/ESDA/JEDEC JS-002-2014 > ±500 V on all pins
MSL Table
Part Number MSL Rating
INN36xxC 3
Feature Code Table1
Features H6012H6022H6053H606
FeedBack Resistors External External External External
IS Sense Resistor External External External External
ILIM Selectable Yes Yes Yes Yes
Primary Fault Response Auto-Restart Auto-Restart Auto-Restart Auto-Restart
Secondary Fault Response Auto-Restart Auto-Restart Auto-Restart Auto-Restart
Auto-Restart VFB(AR) = 90% x VFB VFB(AR) = Overload VFB(AR) = 90% × VFB VFB(AR) = Overload
Over-Temperature Protection Hysteretic Hysteretic Hysteretic Hysteretic
Line OV/UV Enabled Enabled OV Disabled
UV Enabled Enabled
UV Timer tUV- = 35 ms (Typ) tUV- = 35 ms (Typ) tUV- = 35 ms (Typ) tUV- = 35 ms (Typ)
Secondary Switch/Diode Short-Circuit Protection Enabled Enabled Disabled Disabled
Integrated VOUT OVP Enabled Enabled Enabled Enabled
Peak Power Delivery No Yes No Yes
1For the latest updates, please visit www.power.com InnoSwitch Family page to Build Your Own InnoSwitch.
2Available only on INN3672C – INN3677C.
3Available only on INN3674C – INN3677C and PowiGaN devices INN3678C / INN3679C / INN3670C.
Part Ordering Information
• InnoSwitch3 Product Family
• EP Series Number
• Switch Rating
7 725 V / 750 V
9 900 V
• Package Identifier
C InSOP-24D
• Features Code
• Tape & Reel and Other Options
TL Tape & Reel, 2 k pcs per reel.
INN 3672 C - H601 - TL
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Revision Notes Date
APreliminary. 02/17
B Code B and Code S combined release. 05/17
C Code A release. 09/17
D Added InSOP-24D package marking and made minor text edits. 06/18
DUpdated Full Safety and Regulatory Compliance section on page 1 and added CTI to the parameter table. 08/18
EAdded INN369x series. 04/19
F Updated page 1 Advanced Protection / Safety Features section. 06/19
G Added GaN-based INN3679C and INN3670C parts. Updated IDSS1 and IDSS2 parameters. 08/19
H Added ‘PowiGaN’ trademark name. 09/19
IPCN-19281 – Updated Figure 17. Updated parameters: VBPP(H), IUV-, IOV(H), IOV-, VV, tSS(RAMP), ISR(PU), tR, tF, RPU, VSR and IBPS(SD).10/19
JAdded INN3678C part for Code S release. 11/19
K Code A release. Added new application design example. 02/20
L Updated IDSS1 parameter to read VDS = 80% Peak Drain Voltage. 03/20
M Updated safety information on page 1 and corrected typo in Package drawing on page 33. 06/20
For the latest updates, visit our website: www.power.com
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations
does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY
HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one
or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of
Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set
forth at www.power.com/ip.htm.
Life Support Policy
POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:
1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose
failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or
death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness.
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PowiGaN, SCALE, SCALE-1, SCALE-2, SCALE-3 and SCALE-iDriver, are trademarks of Power Integrations, Inc. Other trademarks are property of
their respective companies. ©2020, Power Integrations, Inc.
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