810N252I-02 Datasheet by Renesas Electronics America Inc.
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ICS810N252I-02
DATA SHEET
ICS810N252CKI-02 REVISION A MAY 31, 2013 1 ©2013 Integrated Device Technology, Inc.
Jitter Attenuator & FemtoClock NG® Multiplier
General Description
The ICS810N252I-02 device uses IDT's fourth generation
FemtoClock® NG technology for optimal high clock frequency and
low phase noise performance, combined with a low power
consumption and high power supply noise rejection. The
ICS810N252I-02 is a PLL based synchronous multiplier that is
optimized for PDH or SONET to Ethernet clock jitter attenuation and
frequency translation.
The ICS810N252I-02 contains two internal frequency multiplication
stages that are cascaded in series. The first stage is a jitter
attenuator, capable of jitter attenuation down to 10Hz using the
external loop filter. The second stage is a FemtoClock NG®
frequency multiplier that provides the low jitter, high frequency
Ethernet output clock that easily meets Gigabit and 10 Gigabit
Ethernet jitter requirements. Pre-divider and output divider
multiplication ratios are selected using device selection control pins.
The multiplication ratios are optimized to support most common
clock rates used in PDH, SONET and Ethernet applications. The
device requires the use of an external, inexpensive fundamental
mode 27MHz crystal. The device is packaged in a space-saving
32-VFQFN package and supports industrial temperature range.
Features
•Fourth generation FemtoClock® NG technology
•Two single-ended LVCMOS/LVTTL outputs
•Each output supports independent frequency selection at 25MHz,
125MHz, 156.25MHz and 312.5MHz
•Two differential inputs support the following input types: LVPECL,
LVDS, LVHSTL, HCSL
•Accepts input frequencies from 8kHz to 155.52MHz including
8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz,
125MHz and 155.52MHz
•Crystal interface designed for a 27MHz crystal
•Attenuates the phase jitter of the input clock by using a low-cost
fundamental mode crystal
•Customized settings for jitter attenuation and reference tracking
using an external loop filter connection
•FemtoClock NG frequency multiplier provides low jitter, high
frequency output
•Absolute pull range: ±50ppm
•Power supply noise ratio (PSNR): -85dB
•FemtoClock NG VCO frequency: 625MHz
•RMS phase jitter @ 125MHz, using a 27MHz crystal
(12kHz – 20MHz): 0.67ps (typical)
•3.3V supply voltage
•-40°C to 85°C ambient operating temperature
•Available in lead-free (RoHS 6) package
9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
LF1
LF0
ISET
GND
CLK_SEL
VDD
RESERVED
GND
GND
nc
QB
VDDO
nc
QA
GND
ODASEL_0
PDSEL_2
PDSEL_1
PDSEL_0
VDD
VDDA
ODBSEL_1
ODBSEL_0
ODASEL_1
XTAL_IN
XTAL_OUT
CLK0
nCLK0
VDD
CLK1
nCLK1
VDDX
Pin Assignment
ICS810N252I-02
32 Lead VFQFN
5mm x 5mm x 0.925mm package body
3.15mm x 3.15mm ePad size
K Package
Top View
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E _ <$1=|>ICS810N252CKI-02 REVISION A MAY 31, 2013 2 ©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Block Diagram
Phase
Detector
+
Charge
Pump
A/D Control
Block
FemtoClockÒ NG
VCO
÷NA
Fractional
Feedback
Divider
PD
+
LF
÷M
Xtal
Osc.
LF0
LF1
ISET
QA
QB
0
1
÷P
÷NB
ODBSEL_[1:0]
ODASEL_[1:0]
27MHz
DIGITAL
VCXO
Pulldown
Pullup/
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown
Pulldown 2
2
Pulldown
Pullup 3
CS
RSET RS
CP
SELCLK_
nCLK0
CLK0
CLK1
nCLK1
PDSEL_[2:0]
ICS810N252CKI-02 REVISION A MAY 31, 2013 3 ©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Number Name Type Description
1, 2 LF1, LF0 Analog
Input/Output Loop filter connection node pins. LF0 is the output. LF1 is the input.
3 ISET Analog
Input/Output Charge pump current setting pin.
4, 8, 18, 24 GND Power Power supply ground.
5 CLK_SEL Input Pulldown Input clock select. When HIGH selects CLK1, nCLK1. When LOW, selects
CLK0, nCLK0. LVCMOS / LVTTL interface levels.
6, 12, 27 VDD Power Core supply pins.
7 RESERVED Reserve Reserved pin.
9,
10,
11
PDSEL_2,
PDSEL_1,
PDSEL_0
Input Pullup Pre-divider select pins. LVCMOS/LVTTL interface levels. See Table 3A.
13 VDDA Power Analog supply pin.
14,
15
ODBSEL_1,
ODBSEL_0 Input Pulldown Frequency select pins for Bank B output. See Table 3B.
LVCMOS/LVTTL interface levels.
16,
17
ODASEL_1,
ODASEL_0 Input Pulldown Frequency select pins for Bank A output. See Table 3B.
LVCMOS/LVTTL interface levels.
19 QA Output Single-ended Bank A clock output. LVCMOS/LVTTL interface levels.
20, 23 nc Unused No connect.
21 VDDO Power Output supply pin.
22 QB Output Single-ended Bank B clock output. LVCMOS/LVTTL interface levels.
25 nCLK1 Input Pullup/
Pulldown Inverting differential clock input. VDD/2 bias voltage when left floating.
26 CLK1 Input Pulldown Non-inverting differential clock input.
28 nCLK0 Input Pullup/
Pulldown Inverting differential clock input. VDD/2 bias voltage when left floating.
29 CLK0 Input Pulldown Non-inverting differential clock input.
30,
31
XTAL_OUT,
XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
32 VDDX Power Power supply pin for crystal oscillator.
ICS810N252CKI-02 REVISION A MAY 31, 2013 4 ©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Table 2. Pin Characteristics
Function Tables
Table 3A. Pre-Divider Selection Function Table
Table 3B. Output Divider Function Table
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CIN Input Capacitance 3.5 pF
CPD
Power Dissipation
Capacitance (per output) VDDO = 3.465V 8 pF
RPULLUP Input Pullup Resistor 51 k:
RPULLDOWN Input Pulldown Resistor 51 k:
ROUT Output Impedance VDDO = 3.3V 14 :
Inputs
Pre-Divider ValuePDSEL_2 PDSEL_1 PDSEL_0
000 1
0 0 1 193
0 1 0 256
0 1 1 1944
1 0 0 2500
1 0 1 7776
1 1 0 12500
1 1 1 15552 (default)
Inputs
Output Divider ValueODxSEL_1 ODxSEL_0
0 0 25 (default)
01 5
10 4
11 2
ICS810N252CKI-02 REVISION A MAY 31, 2013 5 ©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Table 3C. Frequency Function Table
Input
Frequency
(MHz)
Pre-Divider
Value
VCXO Frequency
(MHz)
FemtoClock
Feedback
Divider Value
FemtoClock VCO
Frequency (MHz)
Output Divider
Value
Output Frequency
(MHz)
0.008 1 27 25 625 25 25
0.008 1 27 25 625 5 125
0.008 1 27 25 625 4 156.25
0.008 1 27 25 625 2 312.5
1.544 193 27 25 625 25 25
1.544 193 27 25 625 5 125
1.544 193 27 25 625 4 156.25
1.544 193 27 25 625 2 312.5
2.048 256 27 25 625 25 25
2.048 256 27 25 625 5 125
2.048 256 27 25 625 4 156.25
2.048 256 27 25 625 2 312.5
19.44 1944 27 25 625 25 25
19.44 1944 27 25 625 5 125
19.44 1944 27 25 625 4 156.25
19.44 1944 27 25 625 2 312.5
25 2500 27 25 625 25 25
25 2500 27 25 625 5 125
25 2500 27 25 625 4 156.25
25 2500 27 25 625 2 312.5
77.76 7776 27 25 625 25 25
77.76 7776 27 25 625 5 125
77.76 7776 27 25 625 4 156.25
77.76 7776 27 25 625 2 312.5
125 12500 27 25 625 25 25
125 12500 27 25 625 5 125
125 12500 27 25 625 4 156.25
125 12500 27 25 625 2 312.5
155.52 15552 27 25 625 25 25
155.52 15552 27 25 625 5 125
155.52 15552 27 25 625 4 156.25
155.52 15552 27 25 625 2 312.5
ICS810N252CKI-02 REVISION A MAY 31, 2013 6 ©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 4A. LVPECL Power Supply DC Characteristics, VDD = VDDO = VDDX = 3.3V ± 5%, TA = -40°C to 85°C
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = VDDX = 3.3V ± 5%, TA = -40°C to 85°C
NOTE 1: Outputs terminated with 50: to VDDO/2. See Parameter Measurement Information section, Output Load Test Circuit diagram.
Item Rating
Supply Voltage, VDD 3.63V
Inputs, VI-0.5V to VDD+ 0.5V
Outputs, VO-0.5V to VDDO + 0.5V
Package Thermal Impedance, TJA 33.1qC/W (0 mps)
Storage Temperature, TSTG -65qC to 150qC
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Core Supply Voltage 3.135 3.3 3.465 V
VDDA Analog Supply Voltage PLL Mode VDD – 0.30 3.3 VDD V
VDDO Output Supply Voltage 3.135 3.3 3.465 V
VDDX
Crystal Oscillator Supply
Voltage 3.135 3.3 3.465 V
IDD Power Supply Current 230 mA
IDDA Analog Supply Current VDDA = HIGH 30 mA
IDDO Output Supply Current VDDA = LOW, PDSEL[2:0] = 000,
ODxSEL[1:0] = 11 15 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH Input High Voltage 2 VDD + 0.3 V
VIL Input Low Voltage -0.3 0.8 V
IIH
Input
High Current
CLK_SEL,
ODASEL_[1:0],
ODBSEL_[1:0]
VDD = VIN = 3.465V 150 μA
PDSEL_[2:0] VDD = VIN = 3.465V 5 μA
IIL
Input
Low Current
CLK_SEL,
ODASEL_[1:0],
ODBSEL_[1:0]
VDD = 3.465V, VIN = 0V -5 μA
PDSEL_[2:0] VDD = 3.465, VIN = 0V -150 μA
VOH Output High Voltage; NOTE 1 2.6 V
VOL Output Low Voltage; NOTE 1 0.5 V
ICS810N252CKI-02 REVISION A MAY 31, 2013 7 ©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Table 4C. Differential DC Characteristics, VDD = VDDO = VDDX = 3.3V ± 5%, TA = -40°C to 85°C
NOTE 1. Common mode voltage is defined at the crosspoint.
AC Electrical Characteristics
Table 5. AC Characteristics, VDD = VDDO = VDDX = 3.3V ± 5%, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Characterized with outputs at the same frequency using the loop filter components for the 44Hz loop bandwidth.
Refer to Jitter Attenuator Loop Bandwidth Selection Table.
NOTE 1: Outputs switching to same frequency. Refer to the Phase Noise Plot.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 4: Lock Time measured from power-up to stable output frequency, LOW bandwidth setting.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
IIH Input High Current CLK0, nCLK0,
CLK1, nCLK1 VDD = VIN = 3.465V 150 μA
IIL Input Low Current CLK0, CLK1 VDD = 3.465V, VIN = 0V -5 μA
nCLK0, nCLK1 VDD = 3.465V, VIN = 0V -150 μA
VPP Peak-to-Peak Input Voltage 0.15 1.3 V
VCMR Common Mode Input Voltage; NOTE 1 0.5 VDD – 0.85 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fIN Input Frequency 0.008 155.52 MHz
fOUT Output Frequency 25 312.5 MHz
tjit(Ø) RMS Phase Jitter, (Random),
NOTE 1
125MHz fOUT, 27MHz crystal,
Integration Range: 12kHz – 20MHz 0.668 0.762 ps
156.25MHz fOUT, 27MHz crystal,
Integration Range: 12kHz – 20MHz 0.684 0.797 ps
312.5MHz fOUT, 27MHz crystal,
Integration Range: 12kHz – 20MHz 0.643 0.730 ps
PSNR Power Supply Rejection Ratio VPP = 50mV Sine Wave, Integration
Range: 10kHz – 10MHz -85 dB
tsk(o) Output Skew; NOTE 2, 3 70 ps
tR / tFOutput Rise/Fall Time 20% to 80% 200 550 ps
odc Output Duty Cycle fOUT < 156.25MHz 48 52 %
fOUT = 312.5MHz 45 55 %
tLOCK
VCXO & FemtoClock PLL Lock
Time; NOTE 4
Reference Clock Input is ±50ppm from
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ICS810N252CKI-02 REVISION A MAY 31, 2013 8 ©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Typical Phase Noise at 125MHz
Noise Power dBc
Hz
Offset Frequency (Hz)
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ICS810N252CKI-02 REVISION A MAY 31, 2013 9 ©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Parameter Measurement Information
3.3V LVCMOS Output Load Test Circuit
VCXO & FemtoClock PLL Lock Time
Output Skew
Output Duty Cycle/Pulse Width/Period
Differential Input Level
RMS Phase Jitter
LVCMOS Output Rise/Fall Time
SCOPE
Qx
GND
VDD,
1.65V±5%
-1.65V±5%
1.65V±5%
VDDA
VDDX,
VDDO
tsk(o)
V
DDO
2
V
DDO
2
Qx
Qy
tPERIOD
t
PW
t
PERIOD
odc =
V
DDO
2
x 100%
t
PW
QA, QB
nCLK[0:1]
CLK[0:1]
VDD
GND
V
CMR
Cross Points
V
PP
Offset Frequency
f1f2
Phase Noise Plot
Area Under Curve Defined by the Offset Frequency Markers
RMS Phase Jitter =
Noise Power
2 * * ƒ
1*
20%
80% 80%
20%
t
R
t
F
QA, QB
VDD
1m ‘ _
Dnver ,
‘ L
RS
Ro+Rs=Zo
VDD vpp
R3
100 R1
1K
, V1
R4
100
R2
C1 1K
0 1uF
+
Receiver
4
ICS810N252CKI-02 REVISION A MAY 31, 2013 10 ©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Applications Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage V1= VDD/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as close
to the input pin as possible. The ratio of R1 and R2 might need to be
adjusted to position the V1in the center of the input voltage swing. For
example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2
value should be adjusted to set V1 at 1.25V. The values below are for
when both the single ended swing and VDD are at the same voltage.
This configuration requires that the sum of the output impedance of
the driver (Ro) and the series resistance (Rs) equals the transmission
line impedance. In addition, matched termination at the input will
attenuate the signal in half. This can be done in one of two ways.
First, R3 and R4 in parallel should equal the transmission line
impedance. For most 50: applications, R3 and R4 can be 100:. The
values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
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ICS810N252CKI-02 REVISION A MAY 31, 2013 11 ©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other
differential signals. Both differential signals must meet the VPP and
VCMR input requirements. Figures 2A to 2E show interface examples
for the input driven by the most common driver types. The input
interfaces suggested here are examples only. Please consult with the
vendor of the driver component to confirm the driver termination
requirements. For example, in Figure 2A, the input termination
applies for IDT open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
Figure 2A. CLK/nCLK Input Driven by an IDT Open
Emitter LVHSTL Driver
Figure 2C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
Figure 2B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2D. CLK/nCLK Input Driven by a
3.3V LVDS Driver
R1
50Ω
R2
50Ω
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
nCLK
3.3V
LVHSTL
IDT
LVHSTL Driver
Differential
Input
3
.
3V
C
L
K
n
C
L
K
3
.
3V
3
.
3V
LVPE
CL
Diff
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r
e
nti
a
l
In
p
u
t
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CSL
*R
3
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R4
C
L
K
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C
L
K
3
.
3V
3
.
3V
Diff
e
r
e
nti
a
l
In
p
u
t
CLK
nCLK
Differential
Input
LVPECL
3.3V
Zo = 50Ω
Zo = 50Ω
3.3V
R1
50Ω
R2
50Ω
R2
50Ω
3.3V
R1
100Ω
LVDS
CLK
nCLK
3.3V
Receiver
Zo = 50Ω
Zo = 50Ω
\//
ICS810N252CKI-02 REVISION A MAY 31, 2013 12 ©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Recommendations for Unused Input and Output Pins
Inputs:
CLK/nCLK Inputs
For applications not requiring the use of both differential inputs, it is
recommended that the CLK1 and nCLK1 inputs be used for optimal
performance. CLK0 and nCLK0 can be left floating. Though not
required, but for additional protection, a 1k: resistor can be tied from
CLK0 to ground.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k: resistor can be used.
Outputs:
LVCMOS Outputs
All unused LVCMOS outputs can be left floating. There should be no
trace attached.
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 3. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
Figure 3. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
SOLDERSOLDER PINPIN EXPOSED HEAT SLUG
PIN PAD PIN PADGROUND PLANE LAND PATTERN
(GROUND PAD)
THERMAL VIA
ICS810N252CKI-02 REVISION A MAY 31, 2013 13 ©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Jitter Attenuator EXTERNAL COMPONENTS
Choosing the correct external components and having a proper
printed circuit board (PCB) layout is a key task for quality operation of
the Jitter Attenuator. In choosing a crystal, special precaution must
be taken with load capacitance (CL), frequency accuracy and
temperature range.
The crystal’s CL characteristic determines its resonating frequency
and is closely related to the center tuning of the crystal. The total
external capacitance (CEXTERNAL) seen by the crystal when installed
on a PCB is the sum of the stray board capacitance, IC package lead
capacitance, internal device capacitance and any installed tuning
capacitors (CTUNE). The recommended CLin the Crystal Parameter
Table balances the tuning range by centering the tuning curve for a
typical PCB. If the crystal CL is greater than the total external
capacitance (CL > CEXTERNAL), the crystal will oscillate at a higher
frequency than the specification. If the crystal CL is lower than the
total external capacitance (CL < CEXTERNAL), the crystal will oscillate
at a lower frequency than the specification. Mismatches between CL
and CEXTERNAL require adjustments in CTUNE in order to center the
tuning curve. In addition, the frequency accuracy specification in the
crystal characteristics table are used to calculate the APR (Absolute
Pull Range). It is recommended that the crystal CL is not to exceed
the value stated in the Crystal Parameter Table because it can lead
to a reduced APR.
Crystal Characteristics
The VCXO-PLL Loop Bandwidth Selection Table shows RS, CS,CP
and RSET values for recommended high, mid and low loop bandwidth
configurations. The device has been characterized using these
parameters. In addition, the digital VCXO gain (KVCXO) has been
provided for additional loop filter requirements.
Jitter Attenuator Characteristics Table
Jitter Attenuator Loop Bandwidth Selection Table (2nd Order Loop Filter)
NOTE: See Application Schematic to identify loop filter components RS, CS, CP
, R3, C3 and RSET
.
LF0
LF1
ISET
XTAL_IN
XTAL_OUT
R
S
CS
CP
RSET
CTUNE
CTUNE
27MHz
Symbol Parameter Test Conditions Minimum Typical Maximum Units
Mode of Oscillation Fundamental
fNFrequency 27 MHz
fTFrequency Tolerance ±20 ppm
fSFrequency Stability ±20 ppm
Operating Temperature Range -40 +85 0C
CLLoad Capacitance 10 pF
COShunt Capacitance 4pF
ESR Equivalent Series Resistance 40 :
Drive Level 1mW
Aging @ 25 0C First Year ±3 ppm
Symbol Parameter Typical Units
kVCXO VCXO Gain 2.78 kHz/V
Bandwidth Crystal Frequency RS (k:)C
S (μF) CP (μF) R3 (k:) C3 (μF) RSET (k:)
15Hz (Low) 27MHz 215 10 0.022 0 DEPOP 2.74
30Hz (Mid) 27MHz 432 2.2 0.0047 0 DEPOP 2.74
60Hz (High) 27MHz 470 1 0.0022 0 DEPOP 1.5
ICS810N252CKI-02 REVISION A MAY 31, 2013 14 ©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
For applications in which there is substantial low frequency jitter in
the input reference and the phase detector frequency of 8kHz or
10kHz lies in or near a jitter mask, a three pole filter is recommended.
Suggested part values are in the table below. Note that the option of
a three pole filter can be left open by laying out the three pole filter
but setting R3 to 0: and not populating C3. Refer to the application
schematic for a specific example.
Jitter Attenuator Loop Bandwidth Selection Table (3rd Order Loop Filter)
NOTE: See Application Schematic to identify loop filter components RS, CS, CP
, R3, C3 and RSET
.
The crystal and external loop filter components should be kept as
close as possible to the device. Loop filter and crystal traces should
be kept short and separated from each other. Other signal traces
should be kept separate and not run underneath the device, loop filter
or crystal components.
Bandwidth Crystal Frequency RS (k:)C
S (μF) CP (μF) R3 (k:) C3 (μF) RSET (k:)
15Hz (Low) 27MHz 196 10 0.022 82.5 0.010 2.74
30Hz (Mid) 27MHz 392 2.2 0.0047 165 0.0022 2.74
60Hz (High) 27MHz 432 1 0.0022 182 0.001 1.5
ICS810N252CKI-02 REVISION A MAY 31, 2013 15 ©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Schematic Example
Figure 4 shows an example of the ICS810N252I-02 application
schematic. In this example, the device is operated at VDD= VDDA =
VDDX = VDDO = 3.3V. The inputs are driven by a 3.3V LVPECL driver
and an LVDS driver.
A three pole loop filter is used for the greater reduction of 8kHz or
10kHz phase detector spurs relative to that afforded by a two pole
loop filter. It is recommended that the loop filter components be laid
out for the 3-pole option, which will also allow a 2-pole filter to be used
The loop filter components are to be laid out on the ICS810N252I-02
side of the PCB directly adjacent to the LF0 and LF1 pins.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS810N252I-02 provides
separate VDD, VDDA, VDDX and VDDO power supplies for each jitter
attenuator to isolate any high switching noise from coupling into the
internal PLLs.
In order to achieve the best possible filtering, it is highly
recommended that the 0.1uF capacitors on the device side of the
ferrite beads be placed on the device side of the PCB as close to the
power pins as possible. This is represented by the placement of
these capacitors in the schematic. If space is limited, the ferrite
beads, 10uF and 0.1uF capacitor connected to 3.3V can be placed
on the opposite side of the PCB. If space permits, place all filter
components on the device side of the board.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added.
Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all
devices.
1|H
1H
IH
ICS810N252CKI-02 REVISION A MAY 31, 2013 16 ©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Figure 4. ICS810N252I-02 Application Schematic.
FB2
BLM1 8B B22 1S N 1
12VD D O
C2
TU N E
C1
TU N E
X1
27MHz (10pf)
C1 a nd C2 Va lues s et b y cen te r
freq uency tune p roce dur e
C12
0. 1 u F
C45
10uF
R25 10
C17
0.1uF
C30
0.1uF
C15
0.1uF
Rset
2.74K
LF 1
U1
LF 1
1
LF 0
2
IS ET
3
GND
4
CLK_SEL
5
VD D 6
nc 7
GND
8
PD SE L_ 2
9
PD SE L_ 1
10
PD SE L_ 0
11 VD D 12
VD D A 13
ODBSEL_1
14
ODBSEL_0
15
ODASEL_1
16
ODASEL_0
17
GND
18
QA 19
nc 20
VD D O 21
QB 22
nc 23
GND
24
VDDX 32
XT A L_ I N
31
XT A L_ O U T
30
CLK0
29
nC L K0
28
VD D 27
CLK1
26
nC L K1
25
ePAD
33
C47
10uF
C46
0.1uF
R26 10
RU2
Not Install
RU1
1K
RD2
1K
RD1
N o t In s t al l
VDDVD D
PD SE L_ 1
ODBSEL_1
ODBSEL_0
PD SE L_ 2
PD SE L_ 0
C14
0.1uF
To Log ic
Input
pins
Logic Control Input Examples
To Log ic
Inpu t
pins
Set Logic
Input to '1' Set Logic
Input to '0'
LF 0
R3 165k
C3
2.2nF Cs
2.2uF
Rs
392k
Cp
4.7nF
Loop filter and Rset - Mid LBW Setting
CLK_SEL
VD D O
ODASEL_0
Zo = 50
Zo = 50
R1
36
R2
36
LV C M OS R e c e iv e r
LV C M OS R e c e iv e r
LV D S Dr iv er
Zo = 50 Ohm
ODASEL_1
Zo = 50 Ohm
R33
100
Zo = 50 Ohm
R4 50
R5
50
Zo = 50 Ohm R8 50
PEC L D riv er
Place each 0.1uF bypass
cap directly adjacent
to it's corresponding
VDD, VDDA, VDDX or VDDO
pin.
VDDX
VD D
VD D A
VD D
VDD
C7
0.1uF
3. 3 V
C8
10uF
FB1
BLM1 8B B22 1S N 1
12
VD D X
VD D A
VD D
C9
0.1uF
3. 3 V
C10
10uF
ICS810N252CKI-02 REVISION A MAY 31, 2013 17 ©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS810N252I-02.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS810N252I-02 is the sum of the core power plus the power dissipation due to the load. The following is
the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
Core Output Power Dissipation
• Power (core)MAX = VDD_MAX * (IDD + IDDA) = 3.465V *(230mA + 30mA) = 900.9mW
• Power (output)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 15mA = 51.98mW
LVCMOS Output Power Dissipation
• Output Impedance ROUT Power Dissipation due to Loading 50: to VDD/2
Output Current IOUT = VDD_MAX / [2 * (50: + ROUT)] = 3.465V / [2 * (50: + 14:)] = 27.07mA
• Power Dissipation on the ROUT per LVCMOS output
Power (ROUT) = ROUT * (IOUT)2 = 14: * (27.07mA)2 = 10.26mW per output
Total Power (ROUT) = 10.26mW * 2 = 20.52mW
• Dynamic Power Dissipation at 312.5MHz
Power (312.5MHz) = CPD * Frequency * (VDDO)2 = 8pF * 312.5MHz * (3.465V)2 = 30.02mW per output
Total Power (312.5MHz) = 30.02mW * 2 = 60.04mW
Total Power
= Power (core)MAX + Power (output)MAX + Power (ROUT) + Total Power (312.5MHz)
= 900.0mW + 51.98mW + 20.52mW + 60.04mW
= 1033.4mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = TJA * Pd_total + TA
Tj = Junction Temperature
TJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance TJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 33.1°C/W per Table 76 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 1.033W * 33.1°C/W = 119.2°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance TJA for 32 Lead VFQFN, Forced Convection
TJA by Velocity
Meters per Second 013
Multi-Layer PCB, JEDEC Standard Test Boards 33.1°C/W 28.1°C/W 25.4°C/W
ICS810N252CKI-02 REVISION A MAY 31, 2013 18 ©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Reliability Information
Table 7. TJA vs. Air Flow Table for a 32 Lead VFQFN
Transistor Count
The transistor count for ICS810N252I-02 is: 44,740
TJA vs. Air Flow
Meters per Second 013
Multi-Layer PCB, JEDEC Standard Test Boards 33.1°C/W 28.1°C/W 25.4°C/W
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1* ' 9
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17* :17
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ICS810N252CKI-02 REVISION A MAY 31, 2013 19 ©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Package Outline and Package Dimensions
Package Outline - K Suffix for 32 Lead VFQFN
Table 8. Package Dimensions NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
device. The pin count and pin out are shown on the front page. The
package dimensions are in Table 8.
Reference Document: JEDEC Publication 95, MO-220
To p View
Index Area
D
Cham fer 4x
0.6 x 0.6 max
OPTIONAL
Anvil
Singula tion
A
0. 0 8 C
C
A3
A1
S eating Plan e
E2
E2
2
L
(N
-1)x e
(R ef.)
(Ref.)
N & N
Even
N
e
D2
2
D2
(Ref.)
N & N
Odd
1
2
e
2
(Ty p.)
If N & N
are Even
(N -1)x e
(Re f.)
b
Th er mal
Base
N
OR
Anvil
Singulation
N-1N
CHAMFER
1
2
N-1
1
2
N
RADIUS
4
4
Bottom View w/Type C IDBottom View w/Type A ID
There are 2 methods of indicating pin 1 corner at the back of the VFQFN package:
1. Type A: Chamfer on the paddle (near pin 1)
2. Type C: Mouse bite on the paddle (near pin 1)
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
Symbol Minimum Nominal Maximum
N32
A0.80 1.00
A1 00.05
A3 0.25 Ref.
b0.18 0.25 0.30
ND & NE8
D & E 5.00 Basic
D2 & E2 3.0 3.3
e0.50 Basic
L0.30 0.40 0.50
ICS810N252CKI-02 REVISION A MAY 31, 2013 20 ©2013 Integrated Device Technology, Inc.
ICS810N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
Ordering Information
Table 9. Ordering Information
Part/Order Number Marking Package Shipping Packaging Temperature
810N252CKI-02LF ICS252CI02L “Lead-Free” 32 Lead VFQFN Tray -40°C to 85°C
810N252CKI-02LFT ICS252CI02L “Lead-Free” 32 Lead VFQFN Tape & Reel -40°C to 85°C
0ID'IZ
www.lDT.com
ICS810N252I-02 Data Sheet JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
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