VN7004CH Datasheet by STMicroelectronics

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This is information on a product in full production.
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VN7004CH
High-side driver with CurrentSense analog feedback for
automotive applications
Datasheet - production data
Features
Max transient supply voltage
40 V
Operating voltage range
4 to 28 V
Typ. on-state resistance (per Ch)
4 mΩ
Current limitation (typ)
135 A
Stand-by current (max)
0.5 µA
AEC-Q100 qualified
General
Single channel smart high-side driver
with CurrentSense analog feedback
Very low standby current
Compatible with 3.0 V and 5 V CMOS
outputs
Diagnostic functions
Overload and short to ground (power
limitation) indication
Thermal shutdown indication
OFF-state open-load detection
Output short to VCC detection
Sense enable/ disable
Protections
Undervoltage shutdown
Overvoltage clamp
Load current limitation
Self limiting of fast thermal transients
Loss of ground and loss of VCC
Reverse battery
Electrostatic discharge protection
Applications
Specially intended for Automotive smart power
distribution, glow plugs, heating systems, DC
motors, relay replacement and high power
resistive and inductive actuators.
Description
The device is a single channel high-side driver
manufactured using ST proprietary VIPower®
technology and housed in the Octapak package.
The device is designed to drive 12 V automotive
grounded loads through a 3 V and 5 V CMOS-
compatible interface, providing protection and
diagnostics.
The device integrates advanced protective
functions such as load current limitation, overload
active management by power limitation and
overtemperature shutdown.
A sense enable pin allows OFF-state diagnosis to
be disabled during the module low-power mode
as well as external sense resistor sharing among
similar devices.
Table 1: Device summary
Package
Order codes
Tape and reel
Octapak
VN7004CHTR
Contents
VN7004CH
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Contents
1 Block diagram and pin description ................................................ 5
2 Electrical specification .................................................................... 7
2.1 Absolute maximum ratings ................................................................ 7
2.2 Thermal data ..................................................................................... 8
2.3 Electrical characteristics .................................................................... 8
2.4 Electrical characteristics curves ...................................................... 15
3 Protections..................................................................................... 19
3.1 Power limitation ............................................................................... 19
3.2 Thermal shutdown ........................................................................... 19
3.3 Current limitation ............................................................................. 19
3.4 Negative voltage clamp ................................................................... 19
4 Application information ................................................................ 20
4.1 Protection against reverse battery ................................................... 20
4.2 Immunity against transient electrical disturbances .......................... 21
4.3 MCU I/Os protection ........................................................................ 21
4.4 CS - analog current sense .............................................................. 22
4.4.1 Principle of CurrentSense signal generation .................................... 23
4.4.2 Short to VCC and OFF-state open-load detection ........................... 25
5 Package and PCB thermal data .................................................... 27
5.1 Octapak thermal data ...................................................................... 27
6 Package information ..................................................................... 30
6.1 Octapak package information.......................................................... 30
6.2 Octapak packing information ........................................................... 31
6.3 Octapak marking information .......................................................... 33
7 Revision history ............................................................................ 34
VN7004CH
List of tables
DocID027769 Rev 6
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List of tables
Table 1: Device summary ........................................................................................................................... 1
Table 2: Pin functions ................................................................................................................................. 5
Table 3: Suggested connections for unused and not connected pins ........................................................ 6
Table 4: Absolute maximum ratings ........................................................................................................... 7
Table 5: Thermal data ................................................................................................................................. 8
Table 6: Power section ............................................................................................................................... 8
Table 7: Switching ....................................................................................................................................... 9
Table 8: Logic inputs ................................................................................................................................. 10
Table 9: Protection .................................................................................................................................... 10
Table 10: CurrentSense ............................................................................................................................ 11
Table 11: Truth table ................................................................................................................................. 15
Table 12: ISO 7637-2 - electrical transient conduction along supply line ................................................. 21
Table 13: CurrentSense pin levels in off-state .......................................................................................... 25
Table 14: PCB properties ......................................................................................................................... 27
Table 15: Thermal parameters ................................................................................................................. 29
Table 16: Octapak mechanical data ......................................................................................................... 30
Table 17: Reel dimensions ....................................................................................................................... 32
Table 18: Document revision history ........................................................................................................ 34
List of figures
VN7004CH
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List of figures
Figure 1: Block diagram .............................................................................................................................. 5
Figure 2: Configuration diagram (top view)................................................................................................. 6
Figure 3: Current and voltage conventions ................................................................................................. 7
Figure 4: IOUT/ISENSE vs. IOUT ............................................................................................................. 13
Figure 5: Current sense precision vs. IOUT ............................................................................................. 13
Figure 6: Switching times and pulse skew ................................................................................................ 14
Figure 7: TDSTKON .................................................................................................................................. 14
Figure 8: OFF-state output current ........................................................................................................... 15
Figure 9: Standby current ......................................................................................................................... 15
Figure 10: IGND(ON) vs. Iout ................................................................................................................... 16
Figure 11: Logic input high level voltage .................................................................................................. 16
Figure 12: Logic input low level voltage .................................................................................................... 16
Figure 13: High level logic input current ................................................................................................... 16
Figure 14: Low level logic input current .................................................................................................... 16
Figure 15: Logic input hysteresis voltage ................................................................................................. 16
Figure 16: Undervoltage shutdown ........................................................................................................... 17
Figure 17: On-state resistance vs. Tcase ................................................................................................. 17
Figure 18: On-state resistance vs. VCC ................................................................................................... 17
Figure 19: Turn-on voltage slope .............................................................................................................. 17
Figure 20: Turn-off voltage slope .............................................................................................................. 17
Figure 21: Won vs. Tcase ......................................................................................................................... 17
Figure 22: Woff vs. Tcase ......................................................................................................................... 18
Figure 23: ILIMH vs. Tcase ....................................................................................................................... 18
Figure 24: Turn-off output voltage clamp .................................................................................................. 18
Figure 25: OFF-state open-load voltage detection threshold ................................................................... 18
Figure 26: Vs clamp vs. Tcase ................................................................................................................. 18
Figure 27: Vsenseh vs. Tcase .................................................................................................................. 18
Figure 28: Application diagram ................................................................................................................. 20
Figure 29: Simplified internal structure ..................................................................................................... 20
Figure 30: CurrentSense and diagnostic – block diagram........................................................................ 22
Figure 31: CurrentSense block diagram ................................................................................................... 23
Figure 32: Analogue HSD – open-load detection in off-state ................................................................... 24
Figure 33: Open-load / short to VCC condition ......................................................................................... 25
Figure 34: Maximum turn off current vs. inductance ................................................................................ 26
Figure 35: Octapak on two-layers PCB (2s0p to JEDEC JESD 51-5) ...................................................... 27
Figure 36: Octapak on four-layers PCB (2s2p to JEDEC JESD 51-7) ..................................................... 27
Figure 37: Rthj-amb vs PCB copper area in open box free air conditions ............................................... 28
Figure 38: Octapak thermal impedance junction ambient single pulse .................................................... 28
Figure 39: Thermal fitting model for Octapak ........................................................................................... 29
Figure 40: Octapak package dimensions ................................................................................................. 30
Figure 41: Octapack reel 13" .................................................................................................................... 31
Figure 42: Octapak carrier tape ................................................................................................................ 32
Figure 43: Octapak schematic drawing of leader and trailer tape ............................................................ 33
Figure 44: Octapak marking information................................................................................................... 33
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VN7004CH
Block diagram and pin description
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1 Block diagram and pin description
Figure 1: Block diagram
Table 2: Pin functions
Name
Function
VCC
Battery connection.
OUTPUT
Power outputs. All the pins must be connected together.
GND
Ground connection.
INPUT
Voltage controlled input pin with hysteresis. Compatible with 3 V and
5 V CMOS outputs. It controls output switch state.
CS
Analog current sense output pin delivers a current proportional to the
load current.
SEn
Active high compatible with 3 V and 5 V CMOS outputs pin; it enables
the CurrentSense diagnostic pin.
VCC
Control& Diagnostic
LOGIC
DRIVER
Current
Limitation
Power
Clamp
OFF State
Open load
Over
temperature
Undervoltage
VSENSEH
Current
Sense
OVERLOAD PROTECTION
( ACTIVE POWER LIMI TATION )
IN
CS
SEn
GND
OUT
Signal Clamp Reverse
Battery
Protection
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Block diagram and pin description
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Figure 2: Configuration diagram (top view)
Table 3: Suggested connections for unused and not connected pins
Connection / pin
CurrentSense
N.C.
Output
Input
SEn
Floating
Not allowed
X(1)
X
X
X
To ground
Through 1 kΩ
resistor
X
Not allowed
Through
15 kΩ resistor
Through
15 kΩ resistor
Notes:
(1)X: do not care.
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VN7004CH
Electrical specification
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2 Electrical specification
Figure 3: Current and voltage conventions
VF = VOUT - VCC when VOUT > VCC and INPUT = LOW
2.1 Absolute maximum ratings
Stressing the device above the rating listed in Table 4: "Absolute maximum ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to the conditions in the table below for extended
periods may affect device reliability.
Table 4: Absolute maximum ratings
Symbol
Parameter
Value
Unit
VCC
DC supply voltage
38
V
VCCPK
Maximum transient supply voltage (ISO7637-2:2004 Pulse 5b level
IV clamped to 40 V; RL = 4Ω)
40
-VCC
Reverse DC supply voltage
16
-IGND
DC reverse ground pin current
200
mA
IOUT
OUTPUT DC output current
Internally
limited
A
-IOUT
Reverse DC output current
38
IIN
INPUT DC input current
-1 to 10
mA
ISEn
SEn DC input current
ISENSE
CS pin DC output current (VGND = VCC and VSENSE < 0 V)
10
mA
CS pin DC output current in reverse (VCC < 0 V)
-20
EMAX
Maximum switching energy (single pulse)
TDEMAG = 0.13 ms; Tjstart = 150°C
105
mJ
Electrical specification
VN7004CH
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Symbol
Parameter
Value
Unit
VESD
Electrostatic discharge (JEDEC 22A-114F)
INPUT
CurrentSense
SEn
OUTPUT
VCC
4000
2000
4000
4000
4000
V
V
V
V
V
VESD
Charge device model (CDM-AEC-Q100-011)
750
V
Tj
Junction operating temperature
-40 to 150
°C
Tstg
Storage temperature
-55 to 150
2.2 Thermal data
Table 5: Thermal data
Symbol
Parameter
Typ. value
Unit
Rthj-case
Thermal resistance junction-case(1)
1.45
°C/W
Rthj-amb
Thermal resistance junction-ambient (JEDEC JESD 51-5)(2)
58.1
Rthj-amb
Thermal resistance junction-ambient (JEDEC JESD 51-7)(1)
15.6
Notes:
(1)Device mounted on four-layers 2s2p PCB
(2)Device mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace
2.3 Electrical characteristics
7 V < VCC < 28 V; -40°C < Tj < 150°C, unless otherwise specified.
All typical values refer to VCC = 13 V; Tj = 25 °C, unless otherwise specified.
Table 6: Power section
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VCC
Operating supply voltage
4
13
28
V
VUSD
Undervoltage shutdown
4
VUSDReset
Undervoltage shutdown
reset
5
VUSDhyst
Undervoltage shutdown
hysteresis
0.3
RON
On-state resistance
IOUT = 15 A; Tj = 25°C
4
mΩ
IOUT = 15 A; Tj = 150°C
8
IOUT = 15 A; VCC = 4 V;
Tj = 25°C
6
RON_Rev
RDSON in reverse battery
condition
VCC = -13 V; IOUT = -15 A;
Tj = 25°C
4
mΩ
Vclamp
Clamp voltage
IS = 20 mA; Tj = -40°C
38
V
IS = 20 mA;
25°C < Tj < 150°C
41
46
52
VN7004CH
Electrical specification
DocID027769 Rev 6
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Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
ISTBY
Supply current in standby
at VCC = 13 V(1)
VCC = 13 V;
VIN = VOUT = VSEn = 0 V;
Tj = 25°C
0.5
µA
VCC = 13 V;
VIN = VOUT = VSEn = 0 V;
Tj = 85°C(2)
1.4
µA
VCC = 13 V;
VIN = VOUT = VSEn = 0 V;
Tj = 125°C
11
µA
tD_STBY
Standby mode blanking
time
VCC = 13 V; VIN = 5 V;
VSEn = 0 V; IOUT = 0 A
60
300
550
µs
IS(ON)
Supply current
VCC = 13 V; VSEn = 0 V;
VIN = 5 V; IOUT = 0 A
4
6.5
mA
IGND(ON)
Control stage current
consumption in ON-state.
All channels active.
VCC = 13 V; VSEn = 5 V;
VIN = 5 V; IOUT = 15 A
9
mA
IL(off)
Off-state output current at
VCC = 13 V
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 25°C
0
0.01
0.5
µA
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 125°C
0
11
VF
Output - VCC diode voltage
IOUT = -15 A; Tj = 150°C
0.7
V
Notes:
(1)PowerMOS leakage included.
(2)Parameter specified by design; not subject to production test.
Table 7: Switching
VCC = 13 V; -40 ºC < Tj < 150 °C, unless otherwise specified
Symbol
Parameter
Test
conditions
Min.
Typ.
Max.
Unit
td(on)(1)
Turn-on delay time at Tj = 25 °C
RL = 0.87 Ω
10
50
120
µs
td(off)(1)
Turn-off delay time at Tj = 25 °C
10
60
100
(dVOUT/dt)on(1)
Turn-on voltage slope at Tj = 25 °C
RL = 0.87 Ω
0.075
0.28
0.7
V/µs
(dVOUT/dt)off(1)
Turn-off voltage slope at Tj = 25 °C
0.075
0.33
0.7
WON
Switching energy losses at turn-on
(twon)
RL = 0.87 Ω
—
1.8
3.6(2)
mJ
WOFF
Switching energy losses at turn-off
(twoff)
RL = 0.87 Ω
—
2
3.6(2)
mJ
tSKEW(1)
Differential Pulse skew
(tPHL - tPLH)
RL = 0.87 Ω
-50
0
50
µs
Notes:
(1)See Figure 6: "Switching times and pulse skew"
(2)Parameter guaranteed by design and characterization; not subject to production test.
Electrical specification
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Table 8: Logic inputs
7 V < VCC < 28 V; -40 °C < Tj < 150 °C
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
INPUT characteristics
VIL
Input low level voltage
0.9
V
IIL
Low level input current
VIN = 0.9 V
1
µA
VIH
Input high level voltage
2.1
V
IIH
High level input current
VIN = 2.1 V
10
µA
VI(hyst)
Input hysteresis voltage
0.2
V
VICL
Input clamp voltage
IIN = 1 mA
5.3
7.5
V
IIN = -1 mA
-0.7
SEn characteristics (7 V < VCC < 18 V)
VSEnL
Input low level voltage
0.9
V
ISEnL
Low level input current
VIN = 0.9 V
1
µA
VSEnH
Input high level voltage
2.1
V
ISEnH
High level input current
VIN = 2.1 V
10
µA
VSEn(hyst)
Input hysteresis voltage
0.2
V
VSEnCL
Input clamp voltage
IIN = 1 mA
5.3
7.5
V
IIN = -1 mA
-0.7
Table 9: Protection
7 V < VCC < 18 V; -40 °C < Tj < 150 °C
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
ILIMH(1)
DC short circuit current
VCC = 13 V
80
135
175
A
4 V < VCC < 18 V(2)
175
ILIML
Short circuit current
during thermal cycling
VCC = 13 V;
TR < Tj < TTSD
38
TTSD
Shutdown temperature
150
175
200
°C
TR
Reset temperature(2)
TRS + 1
TRS + 7
TRS
Thermal reset of fault
diagnostic indication
VSEn = 5 V
135
THYST
Thermal hysteresis
(TTSD - TR)(2)
7
ΔTJ_SD
Dynamic temperature
VCC = 13 V
60
K
VDEMAG
Turn-off output voltage
clamp
IOUT = 2 A; L = 6 mH;
Tj = -40°C
VCC -
38
V
IOUT = 2 A; L = 6 mH;
Tj = 25°C to 150°C
VCC -
41
VCC -
46
VCC -
52
V
Notes:
(1)Parameter guaranteed by an indirect test sequence.
(2)Parameter guaranteed by design and characterization; not subject to production test.
VN7004CH
Electrical specification
DocID027769 Rev 6
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Table 10: CurrentSense
7 V < VCC < 18 V; -40 °C < Tj < 150 °C
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VSENSE_CL
CurrentSense clamp
voltage
VSEn = 0 V; ISENSE = 1 mA
-17
-12
V
VSEn = 0 V; ISENSE = -1 mA
7
V
Current Sense characteristics
K1
IOUT/ISENSE
IOUT = 10 A; VSENSE = 4 V;
VSEn = 5 V
10040
16720
23400
dK1/K1(1)(2)
Current sense ratio drift
IOUT = 10 A; VSENSE = 4 V;
VSEn = 5 V
-20
20
%
K2
IOUT/ISENSE
IOUT = 15 A; VSENSE = 4 V;
VSEn = 5 V
12530
16710
20890
dK2/K2(1)(2)
Current sense ratio drift
IOUT = 15 A; VSENSE = 4 V;
VSEn = 5 V
-15
15
%
K3
IOUT/ISENSE
IOUT = 45 A; VSENSE = 4 V;
VSEn = 5 V
14450
16970
18850
dK3/K3(1)(2)
Current sense ratio drift
IOUT = 45 A; VSENSE = 4 V;
VSEn = 5 V
-10
10
%
ISENSE0
CurrentSense leakage
current
CurrentSense disabled:
VSEn = 0 V;
0
0.5
µA
CurrentSense disabled;
-1 V < VSENSE < 5 V(2)
-0.5
0.5
µA
CurrentSense enabled:
VSEn = 5 V; VIN = 5 V;
IOUT = 0 A;
0
100
µA
VOUT_CSD(2)
Output voltage for
CurrentSense
shutdown
VSEn = 5 V;
RSENSE = 2.7 kΩ; VIN = 5 V;
IOUT = 15 A
5
V
VSENSE_SAT
CurrentSense
saturation voltage
VCC = 7 V; RSENSE = 10 kΩ;
VSEn = 5 V; VIN = 5 V;
IOUT = 15 A; Tj = -40°C
5
V
ISENSE_SAT(2)
CS saturation current
VCC = 7 V; VSENSE = 4 V;
VIN = 5 V; VSEn = 5 V;
Tj = -40°C
4
mA
IOUT_SAT(2)
Output saturation
current
VCC = 7 V; VSENSE = 4 V;
VIN = 5 V; VSEn = 5 V;
Tj = -40°C
75
A
OFF-state diagnostic
VOL
OFF-state open-load
voltage detection
threshold
VIN = 0 V; VSEn = 5 V;
2
3
4
V
IL(off2)
OFF-state output sink
current
VIN = 0 V; VOUT = VOL;
Tj = -40°C to 125°C
-100
-15
µA
tDSTKON
OFF-state diagnostic
delay time from falling
edge of INPUT (see
Figure 7: "TDSTKON")
VIN = 5 V to 0 V;
VSEn = 5 V; IOUT = 0 A;
VOUT = 4 V
100
350
700
µs
Electrical specification
VN7004CH
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DocID027769 Rev 6
7 V < VCC < 18 V; -40 °C < Tj < 150 °C
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
tD_OL_V
Settling time for valid
OFF-state open load
diagnostic indication
from rising edge of SEn
VIN = 0 V; VOUT = 4 V;
VSEn = 0 V to 5 V
60
µs
tD_VOL
OFF-state diagnostic
delay time from rising
edge of VOUT
VIN = 0 V; VSEn = 5 V;
VOUT = 0 V to 4 V
5
30
µs
Fault diagnostic feedback (see Table 11: "Truth table")
VSENSEH
CurrentSense output
voltage in fault
condition
VCC = 13 V; VIN = 0 V;
VSEn = 5 V; IOUT = 0 A;
VOUT = 4 V; RSENSE = 1 kΩ
5
6.6
V
ISENSEH
CurrentSense output
current in fault
condition
VCC = 13 V; VSENSE = 5 V
7
20
30
mA
CurrentSense timings (current sense mode)(3)
tDSENSE1H
Current sense settling
time from rising edge of
SEn
VIN = 5 V; VSEn = 0 V to
5 V; RSENSE = 1 kΩ;
RL = 0.87 Ω
60
µs
tDSENSE1L
Current sense disable
delay time from falling
edge of SEn
VIN = 5 V; VSEn = 5 V to
0 V; RSENSE = 1 kΩ;
RL = 0.87 Ω
5
20
µs
tDSENSE2H
Current sense settling
time from rising edge of
INPUT
VIN = 0 V to 5 V;
VSEn = 5 V; RSENSE = 1 kΩ;
RL = 0.87 Ω
100
380
µs
ΔtDSENSE2H
Current sense settling
time from rising edge of
IOUT (dynamic response
to a step change of
IOUT)
VIN = 5 V; VSEn = 5 V;
RSENSE = 1 kΩ; ISENSE
= 90% of ISENSEMAX;
RL = 0.87 Ω
200
µs
tDSENSE2L
Current sense turn-off
delay time from falling
edge of INPUT
VIN = 5 V to 0 V; VSEn = 5
V; RSENSE = 1 kΩ;
RL = 0.87 Ω
50
250
µs
Notes:
(1)All values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.
(2)Parameter guaranteed by design and characterization; not subject to production test.
(3)Transition delay are measured up to ±10% of final conditions.
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VN7004CH
Electrical specification
DocID027769 Rev 6
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Figure 4: IOUT/ISENSE vs. IOUT
Figure 5: Current sense precision vs. IOUT
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Electrical specification
VN7004CH
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Figure 6: Switching times and pulse skew
Figure 7: TDSTKON
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VN7004CH
Electrical specification
DocID027769 Rev 6
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Table 11: Truth table
Mode
Conditions
INX
SEn
OUTX
Current Sense
Comments
Stand by
All logic inputs
low
L
L
L
Hi-Z
Low quiescent current
consumption
Normal
Nominal load
connected;
Tj < 150°C
L
H
L
0
H
L
H
Hi-Z
H
H
H
ISENSE = 1/K * IOUT
Overload
Overload or
short to GND
causing:
Tj > TTSD or
ΔTj > ΔTj_SD
H
L
H
Hi-Z
Output cycles with
temperature hysteresis
H
H
H
VSENSEH
Under-
voltage
VCC < VUSD
(falling)
X
X
L
L
Hi-Z
Hi-Z
Re-start when
VCC > VUSD + VUSDhyst
(rising)
OFF-state
diagnostics
Short to VCC
L
H
H
VSENSEH
Open-load
L
H
H
External pull-up
Negative
output
voltage
Inductive loads
turn-off
L
X
< 0 V
0
2.4 Electrical characteristics curves
Figure 8: OFF-state output current
Figure 9: Standby current
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Figure 10: IGND(ON) vs. Iout
Figure 11: Logic input high level voltage
Figure 12: Logic input low level voltage
Figure 13: High level logic input current
Figure 14: Low level logic input current
Figure 15: Logic input hysteresis voltage
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Figure 16: Undervoltage shutdown
Figure 17: On-state resistance vs. Tcase
Figure 18: On-state resistance vs. VCC
Figure 19: Turn-on voltage slope
Figure 20: Turn-off voltage slope
Figure 21: Won vs. Tcase
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Figure 22: Woff vs. Tcase
Figure 23: ILIMH vs. Tcase
Figure 24: Turn-off output voltage clamp
Figure 25: OFF-state open-load voltage
detection threshold
Figure 26: Vs clamp vs. Tcase
Figure 27: Vsenseh vs. Tcase
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3 Protections
3.1 Power limitation
The basic working principle of this protection consists of an indirect measurement of the
junction temperature swing ΔTj through the direct measurement of the spatial temperature
gradient on the device surface in order to automatically shut off the output MOSFET as
soon as ΔTj exceeds the safety level of ΔTj_SD. The protection prevents fast thermal
transient effects and, consequently, reduces thermo-mechanical fatigue.
3.2 Thermal shutdown
In case the junction temperature of the device exceeds the maximum allowed threshold
(typically 175°C), it automatically switches off and the diagnostic indication is triggered. The
device switches on again as soon as its junction temperature drops to TR.
3.3 Current limitation
The device is equipped with an output current limiter in order to protect the silicon as well
as the other components of the system (e.g. bonding wires, wiring harness, connectors,
loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or
during load power-up, the output current is clamped to a safety level, ILIMH, by operating the
output power MOSFET in the active region.
3.4 Negative voltage clamp
In case the device drives inductive load, the output voltage reaches negative value during
turn off. A negative voltage clamp structure limits the maximum negative voltage to a
certain value, VDEMAG, allowing the inductor energy to be dissipated without damaging the
device.
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4 Application information
Figure 28: Application diagram
4.1 Protection against reverse battery
Figure 29: Simplified internal structure
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The device does not need any external components to protect the internal logic in case of a
reverse battery condition. The protection is provided by internal structures.
In addition, due to the fact that the output MOSFET turns on even in reverse battery mode,
thus providing the same low ohmic path as in regular operating conditions, no additional
power dissipation has to be considered.
4.2 Immunity against transient electrical disturbances
The immunity of the device against transient electrical emissions, conducted along the
supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E)
and ISO 16750-2:2010.
The related function performance status classification is shown in Table 12: "ISO 7637-2 -
electrical transient conduction along supply line".
Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and
in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present
device only, without components and accessed through VCC and GND terminals.
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as
follows: “The function does not perform as designed during the test but returns
automatically to normal operation after the test”.
Table 12: ISO 7637-2 - electrical transient conduction along supply line
Test
Pulse
2011(E)
Test pulse severity
level with Status II
functional
performance status
Minimum
number of
pulses or test
time
Burst cycle /
pulse repetition
time
Pulse duration and
pulse generator
internal impedance
Level
US(1)
min
max
1
III
-112V
500 pulses
0,5 s
2ms, 10Ω
2a
III
+55V
500 pulses
0,2 s
5 s
50μs, 2Ω
3a
IV
-220V
1h
90 ms
100 ms
0.1μs, 50Ω
3b
IV
+150V
1h
90 ms
100 ms
0.1μs, 50Ω
4(2)
IV
-7V
1 pulse
100ms, 0.01Ω
Load dump according to ISO 16750-2:2010
Test
B(3)
40V
5 pulse
1 min
400ms, 2Ω
Notes:
(1)US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.
(2)Test pulse from ISO 7637-2:2004(E).
(3)With 40 V external suppressor referred to ground (-40°C < Tj < 150°C).
4.3 MCU I/Os protection
If a ground protection network is used and negative transients are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line both to
prevent the microcontroller I/O pins from latch-up and to protect the HSD inputs.
The value of these resistors is a compromise between the leakage current of
microcontroller and the current required by the HSD I/Os (Input levels compatibility) with
the latch-up limit of microcontroller I/Os.
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Equation
VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak = -150 V; Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
7.5 kΩ ≤ Rprot ≤ 140 kΩ.
Recommended values: Rprot = 15 kΩ
4.4 CS - analog current sense
Diagnostic information on device and load status are provided by an analog output pin (CS)
delivering the following signal:
Current monitor: current monitor of channel output current
Figure 30: CurrentSense and diagnostic – block diagram
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4.4.1 Principle of CurrentSense signal generation
Figure 31: CurrentSense block diagram
Current sense
This output is capable of providing:
Current mirror proportional to the load current in normal operation, delivering current
proportional to the load according to known ratio named K
Diagnostics flag in fault conditions delivering fixed voltage VSENSEH
The current delivered by the current sense circuit, ISENSE, can be easily converted to a
voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load
monitoring and abnormal condition detection.
Normal operation (channel ON, no fault, SEn active)
While device is operating in normal conditions (no fault intervention), VSENSE calculation can
be done using simple equations
Current provided by CurrentSense output: ISENSE = IOUT/K
Voltage on RSENSE: VSENSE = RSENSE * ISENSE = RSENSE * IOUT/K
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Where :
VSENSE is voltage measurable on RSENSE resistor
ISENSE is current provided from CS pin in current output mode
IOUT is current flowing through output
K factor represents the ratio between PowerMOS cells and SenseMOS cells; its
spread includes geometric factor spread, current sense amplifier offset and process
parameters spread of overall circuitry specifying ratio between IOUT and ISENSE.
Failure flag indication
In case of power limitation/overtemperature, the fault is indicated by the CS pin which is
switched to a “current limited” voltage source, VSENSEH .
In any case, the current sourced by the CS in this condition is limited to ISENSEH
Figure 32: Analogue HSD – open-load detection in off-state
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Figure 33: Open-load / short to VCC condition
Table 13: CurrentSense pin levels in off-state
Condition
Output
CurrentSense
SEn
Open-load
VOUT > VOL
Hi-Z
L
VSENSEH
H
VOUT < VOL
Hi-Z
L
0
H
Short to VCC
VOUT > VOL
Hi-Z
L
VSENSEH
H
Nominal
VOUT < VOL
Hi-Z
L
0
H
4.4.2 Short to VCC and OFF-state open-load detection
Short to VCC
A short circuit between VCC and output is indicated by the relevant current sense pin set to
VSENSEH during the device off-state. Small or no current is delivered by the current sense
during the on-state depending on the nature of the short circuit.
OFF-state open-load with external circuitry
Detection of an open-load in off mode requires an external pull-up resistor RPU connecting
the output to a positive supply voltage VPU.
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It is preferable VPU to be switched off during the module standby mode in order to avoid the
overall standby current consumption to increase in normal conditions, i.e. when load is
connected.
RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following
equation:
Equation
Figure 34: Maximum turn off current vs. inductance
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5 Package and PCB thermal data
5.1 Octapak thermal data
Figure 35: Octapak on two-layers PCB (2s0p to JEDEC JESD 51-5)
Figure 36: Octapak on four-layers PCB (2s2p to JEDEC JESD 51-7)
Table 14: PCB properties
Dimension
Value
Board finish thickness
1.6 mm +/- 10%
Board dimension
77 mm x 86 mm
Board material
FR4
Copper thickness (top and bottom layers)
0.070 mm
Copper thickness (inner layers)
0.035 mm
Thermal vias separation
1.2 mm
Thermal via diameter
0.3 mm +/- 0.08 mm
Copper thickness on vias
0.025 mm
Footprint dimension (top layer)
6.4 mm x 7mm
Heatsink copper area dimension (bottom layer)
Footprint, 2 cm2 or 8 cm2
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Package and PCB thermal data
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Figure 37: Rthj-amb vs PCB copper area in open box free air conditions
Figure 38: Octapak thermal impedance junction ambient single pulse
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Equation: Pulse calculation formula
ZTHδ = RTH · + ZTHtp (1 - δ)
where δ = tP/T
Figure 39: Thermal fitting model for Octapak
The fitting model is a simplified thermal tool and is valid for transient evolutions
where the embedded protections (power limitation or thermal cycling during
thermal shutdown) are not triggered.
Table 15: Thermal parameters
Area/island (cm2)
Footprint
2
8
4L
R1 (°C/W)
0.01
0.01
0.01
0.01
R2 (°C/W)
0.5
0.5
0.5
0.5
R3 (°C/W)
1.6
1.6
1.6
1.6
R4 (°C/W)
10
10
10
2.5
R5 (°C/W)
28
20
12
5
R6 (°C/W)
36
26
18
6
C1 (W.s/°C)
0.001
0.001
0.001
0.001
C2 (W.s/°C)
0.0018
0.0018
0.0018
0.0018
C3 (W.s/°C)
0.11
0.11
0.11
0.11
C4 (W.s/°C)
0.6
0.6
0.6
0.8
C5 (W.s/°C)
0.8
1.4
2.2
3
C6 (W.s/°C)
3
6
9
25
Package information
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6 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
6.1 Octapak package information
Figure 40: Octapak package dimensions
Table 16: Octapak mechanical data
Symbol
Millimeters
Min.
Typ.
Max.
A
2.20
2.30
2.40
A1
0.90
1.00
1.10
A2
0.03
0.15
b
0.38
0.45
0.52
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Symbol
Millimeters
Min.
Typ.
Max.
b1
0.70
b4
5.20
5.30
5.40
c
0.45
0.50
0.60
c2
0.75
0.80
0.90
D
6.00
6.10
6.20
D1
5.15
E
6.40
6.50
6.60
E1
5.30
e
0.85 BSC
e1
1.60
1.70
1.80
e2
3.30
3.40
3.50
e3
5.00
5.10
5.20
H
9.35
9.70
10.10
L
1.00
—
(L1)
2.80
L2
0.80
L3
0.85
R
0.40 BSC
V2
0°
8°
6.2 Octapak packing information
Figure 41: Octapack reel 13"
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Package information
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Table 17: Reel dimensions
Description
Value(1)
Base quantity
2500
Bulk quantity
2500
A (max)
330
B (min)
1.5
C (+0.5, -0.2)
13
D
20.2
N
100
W1 (+2 /-0)
16.4
W2 (max)
22.4
Notes:
(1)All dimensions are in mm.
Figure 42: Octapak carrier tape
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Figure 43: Octapak schematic drawing of leader and trailer tape
6.3 Octapak marking information
Figure 44: Octapak marking information
Parts marked as "&" are not yet qualified and therefore not approved for use in production.
ST is not responsible for any consequences resulting from such use. In no event will ST be
liable for the customer using any of these engineering samples in production. ST’s Quality
department must be contacted prior to any decision to use these engineering samples to
run a qualification activity.
Revision history
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7 Revision history
Table 18: Document revision history
Date
Revision
Changes
21-Apr-2015
1
Initial release
06-Aug-2015
2
Table 4: "Absolute maximum ratings":
VCC_LSC: removed row
EMAX: updated value
Table 6: "Power section":
ISTBY, IL(off): updated values
Updated Table 7: "Switching"
Table 9: "Protection":
ILIMH: updated values
Table 10: "CurrentSense":
Kx, dKx/Kx, ISENSE0, IOUT_SAT: updated values
12-Nov-2015
3
Updated Section "Features"
Table 6: "Power section":
ISTBY, IL(off): updated values
Table 10: "CurrentSense":
dKx/Kx: updated values
27-Apr-2016
4
Updated Figure 1: "Block diagram"
Table 10: "CurrentSense":
K3: updated values
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Date
Revision
Changes
12-Jul-2016
5
Section "Features":
Current limitation (typ): updated value
Table 4: "Absolute maximum ratings":
EMAX: updated TDEMAG parameter and value
Table 5: "Thermal data":
Updated all Typ values and Rthj-case term
Table 7: "Switching":
(dVOUT/dt)on, (dVOUT/dt)off, WON, WOFF, tSKEW: updated values
Table 9: "Protection":
ILIMH, ILIML: updated typ and max values
ΔTJ_SD: removed Tj test condition
Table 10: "CurrentSense":
VSENSE_SAT, ISENSE_SAT, IOUT_SAT: updated test conditions
tDSENSE2H: updated max value
Section 2.3: "Electrical characteristics":
Added Figure 4: "IOUT/ISENSE vs. IOUT" and Figure 5:
"Current sense precision vs. IOUT"
Added Section 2.4: "Electrical characteristics curves"
Section 4.4.2: "Short to VCC and OFF-state open-load detection":
Added Figure 34: "Maximum turn off current vs. inductance"
Section 6.1: "Octapak thermal data":
Updated Figure 35: "Octapak on two-layers PCB (2s0p to
JEDEC JESD 51-5)", Figure 36: "Octapak on four-layers PCB
(2s2p to JEDEC JESD 51-7)", Figure 37: "Rthj-amb vs PCB
copper area in open box free air conditions", Figure 38:
"Octapak thermal impedance junction ambient single pulse",
Figure 39: "Thermal fitting model for Octapak", and Table 15:
"Thermal parameters"
Minor text corrections throughout the document
09-Nov-2016
6
Updated Applications section
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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the
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