MB85RS256A Datasheet by Fujitsu Electronics America, Inc.

FuﬁTsu

FUJITSU SEMICONDUCTOR

DATA SHEET

2011.8

Memory FRAM

256 K (32 K × 8) Bit SPI

MB85RS256A

■DESCRIPTION

MB85RS256A is a FRAM (Ferroelectric Random Access Memory) chip in a configuration of 32,768

words × 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the

nonvolatile memory cells.

MB85RS256A adopts the Serial Peripheral Interface (SPI).

The MB85RS256A is able to retain data without using a back-up battery, as is needed for SRAM.

The memory cells used in the MB85RS256A can be used for 1010 read/write operations, which is a significant

improvement over the number of read and write operations supported by Flash memory and E2PROM.

MB85RS256A does not take long time to write data unlike Flash memories nor E2PROM, and MB85RS256A

takes no wait time.

■FEATURES

• Bit configuration : 32,768 words × 8 bits

• Serial Peripheral Interface : SPI (Serial Peripheral Interface)

Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1)

• Operating frequency : 25 MHz (Max)

• High endurance : 10 Billion Read/Writes

• Data retention : 10 years (+55 °C)

• Operating power supply voltage : 3.0 V to 3.6 V

• Low power operation : Operating power supply current 5 mA (Typ@25 MHz)

Standby current 9 μA (Typ)

• Operating temperature range : -40 °C to +85 °C

• Package : 8-pin plastic SOP (FPT-8P-M02)

RoHS compliant

DS501-00007-1v0-E

FUJITSU

MB85RS256A

2DS501-00007-1v0-E

■PIN ASSIGNMENT

■PIN FUNCTIONAL DESCRIPTIONS

Pin No. Pin Name Functional description

1CS

Chip Select pin

This is an input pin to make chips select. When CS is “H” level, device is in deselect

(standby) status as long as device is not write status internally, and SO becomes High-

Z. Inputs from other pins are ignored for this time. When CS is “L” level, device is in select

(active) status. CS has to be “L” level before inputting op-code.

3WP

Write Protect pin

This is a pin to control writing to a status register. When WP is “L” level, writing to a status

7HOLD

Hold pin

This pin is used to interrupt serial input/output without making chips deselect. When

HOLD is “L” level, hold operation is activated, SO becomes High-Z, SCK and SI become

do not care. While the hold operation, CS has to be retained “L” level.

6SCK

Serial Clock pin

This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising

edge, SO is output synchronously to a falling edge.

5SI

Serial Data Input pin

This is an input pin of serial data. This inputs op-code, address, and writing data.

2SO

Serial Data Output pin

This is an output pin of serial data. Reading data of FRAM memory cell array and status

8 VDD Supply Voltage pin

4 GND Ground pin

GNDSI

VDD

SCK

HOLD

(TOP VIEW)

(FPT-8P-M02)

5) FUJITSU

MB85RS256A

DS501-00007-1v0-E 3

■BLOCK DIAGRAM

SCK

SI Serial-Parallel Converter

FRAM Cell Array

32,768 ✕ 8

Column Decoder/Sense Amp/

Write Amp

FRAM

Status Register

Data Register

Parallel-Serial Converter

Control Circuit

Address Counter

Row Decoder

HOLD

& FUJITSU

MB85RS256A

4DS501-00007-1v0-E

■SPI MODE

MB85RS256A corresponds to the SPI mode 0 (CPOL = 0, CPHA = 0) , and SPI mode 3 (CPOL = 1, CPHA = 1) .

SCK

76543210

MSB LSB

SPI Mode 0

SPI Mode 3

& FUJITSU

MB85RS256A

DS501-00007-1v0-E 5

■SERIAL PERIPHERAL INTERFACE (SPI)

MB85RS256A works as a slave of SPI. More than 2 devices can be connected by using microcontroller

equipped with SPI port. By using a microcontroller not equipped with SPI port, SI and SO can be bus

connected to use.

SCK

SS1

HOLD1

MOSI

MISO

SS2

HOLD2

SCK

CS HOLD

SISO SCK

CS HOLD

SISO

MB85RS256A MB85RS256A

SCK

CS HOLD

SISO

MB85RS256A

SPI

Microcontroller

MOSI : Master Out Slave In

MISO : Master In Slave Out

SS : Slave Select

System Configuration with SPI Port

System Configuration without SPI Port

Microcontroller

5) FUJITSU

MB85RS256A

6DS501-00007-1v0-E

■STATUS REGISTER

■OP-CODE

MB85RS256A accepts 6 kinds of command specified in op-code. Op-code is a code composed of 8 bits

shown in the table below. Do not input invalid codes other than those codes. If CS is risen while inputting

op-code, the command are not performed.

Bit No. Bit Name Function

7WPEN

Status Register Write Protect

This is a bit composed of nonvolatile memories (FRAM). WPEN protects

writing to a status register (refer to “■ WRITING PROTECT”) relating with

WP input. Writing with the WRSR command and reading with the RDSR

command are possible.

6 to 4 ⎯

Not Used Bits

These are bits composed of nonvolatile memories, writing with the WRSR

command is possible, and “000” is written before shipment. These bits are

not used but they are read with the RDSR command.

3 BP1 Block Protect

This is a bit composed of nonvolatile memory. This defines block size for

writing protect with the WRITE command (refer to “■ BLOCK PRO-

TECT”). Writing with the WRSR command and reading with the RDSR

command are possible.

2 BP0

1WEL

Write Enable Latch

This indicates FRAM Array and status register are writable. The WREN

command is for setting, and the WRDI command is for resetting. With the

RDSR command, reading is possible but writing is not possible with the

WRSR command. WEL is reset after the following operations.

The time when power is up.

The time when the WRDI command is input.

The time when the WRSR command is input.

The time when the WRITE command is input.

0 0 This is a bit fixed to “0”.

Name Description Op-code

WREN Set Write Enable Latch 0000 0110B

WRDI Reset Write Enable Latch 0000 0100B

RDSR Read Status Register 0000 0101B

WRSR Write Status Register 0000 0001B

READ Read Memory Code 0000 0011B

WRITE Write Memory Code 0000 0010B

? 7 é T 5) FUJITSU

MB85RS256A

DS501-00007-1v0-E 7

■COMMAND

• WREN

The WREN command sets WEL (Write Enable Latch) . WEL has to be set with the WREN command before

writing operation (WRSR command and WRITE command) .

• WRDI

The WRDI command resets WEL (Write Enable Latch) . Writing operation (WRSR command and WRITE

command) are not performed when WEL is reset.

SCK

00000110

High-Z

76543210

InvalidInvalid

SCK

00000100

High-Z

76543210

InvalidInvalid

m m m E 5) FUJITSU

MB85RS256A

8DS501-00007-1v0-E

• RDSR

The RDSR command reads status register data. After op-code of RDSR is input to SI, 8-cycle clock is input

to SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. Continuously

reading status register is enabled by keep on sending SCK before rising CS with the RDSR command.

• WRSR

The WRSR command writes data to the nonvolatile memory bit of status register. After performing WRSR

op-code to a SI pin, 8 bits writing data is input. WEL (Write Enable Latch) is not able to be written with WRSR

command. A SI value correspondent to bit 1 is ignored. Bit 0 of the status register is fixed to “0” and cannot

be written. The SI value corresponding to bit 0 is ignored. WP signal level shall be fixed before performing

WRSR command, and do not change the WP signal level until the end of command sequence.

SCK

00000101

High-Z

76543210

Invalid

MSB

76543210

Data Out

LSB

Invalid

SCK

00000001

76543210

Data In

MSB

76543210

High-Z

LSB

76543210

Instruction

A /_ WW l—l—DKXECXE~JIIIIII(: M 5) FUJITSU

MB85RS256A

DS501-00007-1v0-E 9

• READ

The READ command reads FRAM memory cell array data. Arbitrary 16 bits address and op-code of READ

are input to SI. The most significant address bit is invalid. Then, 8-cycle clock is input to SCK. SO is output

synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen, the READ

command is completed, but keep on reading with automatic address increment is enabled by continuously

sending clock for 8 cycles each to SCK before CS is risen. When it reaches the most significant address, it

rolls over to come back to the starting address, and reading cycle keeps on infinitely.

• WRITE

The WRITE command writes data to FRAM memory cell array. WRITE op-code, arbitrary 16 bits of address

and 8 bits of writing data are input to SI. The most significant address bit is invalid. When 8 bits of writing

data is input, data is written to FRAM memory cell array. Risen CS will terminate the WRITE command, but

if you continue sending the writing data for 8 bits each before CS is risen, it is possible to continue writing

with automatic address increment. When it reaches the most significant address, it rolls over, comes back

to the starting address, and writing cycle can be continued infinitely.

SCK

00 00X11210

MSB

76543210

Data Out

MSB

High-Z LSB

4201

Invalid

13121110982524232221201918 313029282726

OP-CODE

00 1 111314 35

16-bit Address

Invalid

LSB

20136457

SCK

00 00X11210

MSB

76543210

Data In

MSB

High-Z LSB

4201

13121110982524232221201918 313029282726

OP-CODE

00 0 111314 35

16-bit Address

LSB

20136457

||7 & FUJITSU

MB85RS256A

10 DS501-00007-1v0-E

■BLOCK PROTECT

Writing protect block is configured by the WRITE command with BP1, BP0 value of the status register.

■WRITING PROTECT

Writing operation of the WRITE command and the WRSR command are protected with the value of WEL,

WPEN, WP as shown in the table.

■HOLD OPERATION

Hold status is retained without aborting a command if HOLD is “L” level while CS is “L” level. The timing for

starting and ending hold status depends on the SCK to be “H” level or “L” level when a HOLD pin input is

transited as shown in the diagram below. Arbitrary command operation is interrupted in hold status, SCK

and SI inputs become do not care. And, SO becomes High-Z while reading command (RDSR, READ) . If

CS is risen with hold status, a command is aborted and device is reset.

BP1 BP0 Protected Block

00None

0 1 6000H to 7FFFH (upper 1/4)

1 0 4000H to 7FFFH (upper 1/2)

1 1 0000H to 7FFFH (all)

WEL WPEN WP Protected Blocks Unprotected Blocks Status Register

0 X X Protected Protected Protected

1 0 X Protected Unprotected Unprotected

1 1 0 Protected Unprotected Protected

1 1 1 Protected Unprotected Unprotected

SCK

Hold Condition

HOLD

Hold Condition

5) FUJITSU

MB85RS256A

DS501-00007-1v0-E 11

■ABSOLUTE MAXIMUM RATINGS

*:These parameters are based on the condition that VSS is 0 V.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■RECOMMENDED OPERATING CONDITIONS

*:These parameters are based on the condition that VSS is 0 V.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of

the semiconductor device. All of the device's electrical characteristics are warranted when the

device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented

on the data sheet. Users considering application outside the listed conditions are advised to contact

their representatives beforehand.

Parameter Symbol Rating Unit

Min Max

Power supply voltage* VDD − 0.5 + 4.0 V

Input voltage* VIN − 0.5 VDD + 0.5 V

Output voltage* VOUT − 0.5 VDD + 0.5 V

Operating temperature TA − 40 + 85 °C

Storage temperature Tstg − 40 + 125 °C

Parameter Symbol Value Unit

Min Typ Max

Power supply voltage* VDD 3.0 3.3 3.6 V

Input high voltage* VIH VDD × 0.8 ⎯VDD + 0.5 V

Input low voltage* VIL − 0.5 ⎯ + 0.6 V

Operating temperature TA − 40 ⎯ + 85 °C

5) FUJITSU

MB85RS256A

12 DS501-00007-1v0-E

■ELECTRICAL CHARACTERISTICS

1. DC Characteristics

(within recommended operating conditions)

Parameter Symbol Condition Value Unit

Min Typ Max

Input leakage current |ILI|VIN = 0 V to VDD ⎯⎯10 μA

Output leakage current |ILO|VOUT = 0 V to VDD ⎯⎯10 μA

Operating power supply current IDD SCK = 25 MHz ⎯510mA

Standby current ISB All inputs VSS or

SCK = SI = CS = VDD ⎯950μA

Output high voltage VOH IOH = −2 mA VDD × 0.8 ⎯⎯V

Output low voltage VOL IOL = 2 mA ⎯⎯0.4 V

5) FUJITSU

MB85RS256A

DS501-00007-1v0-E 13

2. AC Characteristics

(within recommended operating conditions)

AC Test Condition

Power supply voltage : 3.0 V to 3.6 V

Operation temperature : − 40 °C to + 85 °C

Input voltage magnitude : 0.3 V to 2.7 V

Input rising time : 5 ns

Input falling time : 5 ns

Input judge level : VDD/2

Output judge level : VDD/2

Parameter Symbol Value Unit

Min Max

SCK clock frequency fCK 025MHz

Clock high time tCH 20 ⎯ns

Clock low time tCL 20 ⎯ns

Chip select set up time tCSU 10 ⎯ns

Chip select hold time tCSH 10 ⎯ns

Output disable time tOD ⎯20 ns

Output data valid time tODV ⎯18 ns

Output hold time tOH 0⎯ns

Deselect time tD60 ⎯ns

Data in rise time tR⎯50 ns

Data fall time tF⎯50 ns

Data set up time tSU 5⎯ns

Data hold time tH5⎯ns

HOLD set up time tHS 10 ⎯ns

HOLD hold time tHH 10 ⎯ns

HOLD output floating time tHZ ⎯20 ns

HOLD output active time tLZ ⎯20 ns

5) FUJITSU

MB85RS256A

14 DS501-00007-1v0-E

AC Load Equivalent Circuit

3. Pin Capacitance

Parameter Symbol Condition Value Unit

Min Max

Output capacitance COVDD = VIN = VOUT = 0 V,

f = 1 MHz, TA = +25 °C

⎯10 pF

Input capacitance CI⎯10 pF

30 pF

Output

3.3 V

1.2 k

0.95 k

w—u 1 ‘ 14—» n7 4w ‘ ‘ %W%W% w—u‘w—w‘ S W 5) FUJITSU

MB85RS256A

DS501-00007-1v0-E 15

■TIMING DIAGRAM

• Serial Data Timing

• Hold Timing

SCK

Valid in

SO High-Z

: do not care

tCSU

tCH tCL

tSU tH

tODVtOH tOD

tCSH

High-Z

SCK

tHStHS

tHHtHH tHH tHH

tHZ tLZ tHZ tLZ

tHStHS

HOLD

High-ZHigh-Z

5) FUJITSU

MB85RS256A

16 DS501-00007-1v0-E

■POWER ON/OFF SEQUENCE

■NOTES ON USE

Data written before performing IR reflow is not guaranteed after IR reflow.

Parameter Symbol Value Unit

Min Max

CS level hold time at power OFF tpd 200 ⎯ns

CS level hold time at power ON tpu 85 ⎯ns

Power supply rising time tr 0.05 200 ms

GND

CS >

DD × 0.8*

tpd tputr

VIL (Max)

1.0 V

VIH (Min)

3.0 V

VDD

CS : do not care CS >

DD × 0.8*

CS CS

GND

VIL (Max)

1.0 V

VIH (Min)

3.0 V

* : CS (Max) < VDD + 0.5 V

Note : •Because turning the power-on from an intermediate level may cause malfunctions, when the power

is turned on, VDD is required to be started from 0 V.

•If the device does not operate within the specified conditions of read cycle, write cycle, power on/

off sequence, memory data can not be guaranteed.

5) FUJITSU

MB85RS256A

DS501-00007-1v0-E 17

■ORDERING INFORMATION

Part number Package Remarks

MB85RS256APNF-G-JNE1 8-pin plastic SOP

(FPT-8P-M02)

MB85RS256APNF-G-JNERE1 8-pin plastic SOP

(FPT-8P-M02) Embossed Carrier tape

505 V199 s ﬁﬂﬂﬁ FUJITSU

MB85RS256A

18 DS501-00007-1v0-E

■PACKAGE DIMENSION

Please check the latest package dimension at the following URL.

http://edevice.fujitsu.com/package/en-search/

8-pin plastic SOP Lead pitch 1.27 mm

Package width

package length

3.9 mm × 5.05 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height 1.75 mm MAX

Weight 0.06 g

8-pin plastic SOP

(FPT-8P-M02)

2002-2010 FUJITSU SEMICONDUCTOR LIMITED F08004S-c-4-9

1.27(.050)

3.90±0.30 6.00±0.40

.199 –.008

+.010

–0.20

+0.25

5.05

0.13(.005)

(.154±.012) (.236±.016)

0.10(.004)

0.44±0.08

(.017±.003)

–0.07

+0.03

0.22

.009 +.001

–.003

45°

0.40(.016)

"A" 0~8°

0.25(.010)

(Mounting height)

Details of "A" part

1.55±0.20

(.061±.008)

0.50±0.20

(.020±.008)

0.60±0.15

(.024±.006)

0.15±0.10

(.006±.004)

(Stand off)

0.10(.004)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

Note 1) *1 : These dimensions include resin protrusion.

Note 2) *2 : These dimensions do not include resin protrusion.

Note 3) Pins width and pins thickness include plating thickness.

Note 4) Pins width do not include tie bar cutting remainder.

5) FUJITSU

MB85RS256A

DS501-00007-1v0-E 19

■MAJOR CHANGES IN THIS EDITION

A change on a page is indicated by a vertical line drawn on the left side of that page.

Page Section Change Results

1■ FEATURES

• Package

Added “RoHS compliant”.

■ COMMAND

• WRSR

Added “WP signal level shall be fixed before performing

WRSR command, and do not change the WP signal level

until the end of command sequence”.

■ ELECTRICAL CHACTERISTIC

• Pin Capacitance

Added the row of “Condition” to the table.

Condition;

VDD = VIN = VOUT = 0 V, f = 1 MHz, TA = +25 °C

■ ORDERING INFORMATION Changed the part numbers from TBD.

MB85RS256APNF-G-JNE1

MB85RS256APNF-G-JNERE1

MB85RS256A

FUJITSU SEMICONDUCTOR LIMITED

Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,

Kohoku-ku Yokohama Kanagawa 222-0033, Japan

Tel: +81-45-415-5858

http://jp.fujitsu.com/fsl/en/

For further information please contact:

North and South America

FUJITSU SEMICONDUCTOR AMERICA, INC.

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94085-5401, U.S.A.

Tel: +1-408-737-5600 Fax: +1-408-737-5999

http://us.fujitsu.com/micro/

Europe

FUJITSU SEMICONDUCTOR EUROPE GmbH

Pittlerstrasse 47, 63225 Langen, Germany

Tel: +49-6103-690-0 Fax: +49-6103-690-122

http://emea.fujitsu.com/semiconductor/

Korea

FUJITSU SEMICONDUCTOR KOREA LTD.

902 Kosmo Tower Building, 1002 Daechi-Dong,

Gangnam-Gu, Seoul 135-280, Republic of Korea

Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

http://kr.fujitsu.com/fsk/

Asia Pacific

FUJITSU SEMICONDUCTOR ASIA PTE. LTD.

151 Lorong Chuan,

#05-08 New Tech Park 556741 Singapore

Tel : +65-6281-0770 Fax : +65-6281-0220

http://sg.fujitsu.com/semiconductor/

FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.

Rm. 3102, Bund Center, No.222 Yan An Road (E),

Shanghai 200002, China

Tel : +86-21-6146-3688 Fax : +86-21-6335-1605

http://cn.fujitsu.com/fss/

FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.

10/F., World Commerce Centre, 11 Canton Road,

Tsimshatsui, Kowloon, Hong Kong

Tel : +852-2377-0226 Fax : +852-2376-3269

http://cn.fujitsu.com/fsp/

Specifications are subject to change without notice. For further information please contact each office.

The contents of this document are subject to change without notice.

Customers are advised to consult with sales representatives before ordering.

The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose

of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does

not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating

the device based on such information, you must assume any responsibility arising out of such use of the information.

FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.

Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use

or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any

third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right

by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or

other rights of third parties which would result from the use of information contained herein.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured

as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect

to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in

nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in

weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).

Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages aris-

ing in connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures

by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-

current levels and other abnormal operating conditions.

Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations

of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.

The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

Edited: Sales Promotion Department

Products related to this Datasheet

IC FRAM 256K SPI 25MHZ 8SOP

MB85RS256APNF-G-JNE1