SIC632(A) Datasheet by Vishay Siliconix

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SiC632, SiC632A
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S19-0567-Rev. D, 22-Jul-2019 1Document Number: 62992
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50 A VRPower® Integrated Power Stage
DESCRIPTION
The SiC632 and SiC632A are integrated power stage
solutions optimized for synchronous buck applications to
offer high current, high efficiency, and high power density
performance. Packaged in Vishay’s proprietary
5 mm x 5 mm
MLP package, SiC632 and SiC632A enables voltage
regulator designs to deliver up to 50 A continuous current
per phase.
The internal power MOSFETs utilizes Vishay’s
state-of-the-art Gen IV TrenchFET technology that delivers
industry benchmark performance to significantly reduce
switching and conduction losses.
The SiC632 and SiC632A incorporate an advanced
MOSFET gate driver IC that features high current driving
capability, adaptive dead-time control, an integrated
bootstrap Schottky diode, a thermal warning (THWn) that
alerts the system of excessive junction temperature, and
zero current detection to improve light load efficiency. The
drivers are also compatible with a wide range of PWM
controllers and supports tri-state PWM, 3.3 V (SiC632A) /
5 V (SiC632) PWM logic.
FEATURES
• Thermally enhanced PowerPAK® MLP55-31L
package
• Vishay’s Gen IV MOSFET technology and a low
side MOSFET with integrated Schottky diode
• Delivers up to 50 A continuous current
• High efficiency performance
• High frequency operation up to 1.5 MHz
• Power MOSFETs optimized for 19 V input stage
• 3.3 V (SiC632A) / 5 V (SiC632) PWM logic with tri-state and
hold-off
• Zero current detect control for light load efficiency
improvement
• Low PWM propagation delay (< 20 ns)
• Faster disable
• Thermal monitor flag
• Under voltage lockout for VCIN
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS
• Multi-phase VRDs for computing, graphics card and memory
• Intel IMVP-8 VRPower delivery
-V
CORE
, V
GRAPHICS
, V
SYSTEM AGENT
Skylake, Kabylake platforms
-V
CCGI
for Apollo Lake platforms
• Up to 24 V rail input DC/DC VR modules
TYPICAL APPLICATION DIAGRAM
Fig. 1 - SiC632 and SiC632A Typical Application Diagram
PWM
controller
Gate
driver
5V VIN
VOUT
VCIN
ZCD_EN#
DSBL#
PWM
THWn
VDRV
VIN
BOOT
VSWH
PGND
GL
CGND
PHASE
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SiC632, SiC632A
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S19-0567-Rev. D, 22-Jul-2019 2Document Number: 62992
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PINOUT CONFIGURATION
Fig. 2 - SiC632 and SiC632A Pin Configuration
PIN CONFIGURATION
PIN NUMBER NAME FUNCTION
1 PWM PWM input logic
2 ZCD_EN# ZCD control. Active low
3V
CIN Supply voltage for internal logic circuitry
4, 32 CGND Signal ground
5 BOOT High side driver bootstrap voltage
6 N.C. Not connected internally, can be left floating or connected to ground
7 PHASE Return path of high side gate driver
8 to 11, 34 VIN Power stage input voltage. Drain of high side MOSFET
12 to 15, 28, 35 PGND Power ground
16 to 26 VSWH Phase node of the power stage
27, 33 GL Low side MOSFET gate signal
29 VDRV Supply voltage for internal gate driver
30 THWn Thermal warning open drain output
31 DSBL# Disable pin. Active low
ORDERING INFORMATION
PART NUMBER PACKAGE MARKING CODE OPTION
SiC632CD-T1-GE3 PowerPAK MLP55-31L SiC632 5 V PWM optimized
SiC632ACD-T1-GE3 PowerPAK MLP55-31L SiC632A 3.3 V PWM optimized
SiC632DB / SiC632ADB Reference board
PGND
CGND
BOOT
PHASE
VIN
PGND
PGND
PGND
PGND
VIN
VIN
VIN
N.C.
GL
VDRV
THWn
DSBL#
PWM
ZCD_EN#
VCIN
PGND
VIN
CGND
GL
Top view Bottom view
PGND
CGND
BOOT
PHASE
VIN
PGND
PGND
PGND
PGND
VIN
VIN
VIN
N.C.
GL
VDRV
THWn
DSBL#
PWM
ZCD_EN#
VCIN
35
PGND
34
VIN
32
CGND
GL
2
1
4
3
6
5
8
7
2425262728293031
1514131211109
2
1
4
3
6
5
8
7
15 14 13 12 11 10 9
24 25 26 27 28 29 30 31
VSWH 23
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
33
GL
VSWH 22
VSWH 21
VSWH 20
VSWH 19
VSWH 18
VSWH 17
VSWH 16
23 VSWH
22 VSWH
21 VSWH
20 VSWH
19 VSWH
16 VSWH
18 VSWH
17 VSWH
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S19-0567-Rev. D, 22-Jul-2019 3Document Number: 62992
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PART MARKING INFORMATION
Notes
• Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
(1) The specification values indicated “AC” is VSWH to PGND -8 V (< 20 ns, 10 μJ), min. and 33 V (< 50 ns), max.
(2) The specification value indicates “AC voltage” is VBOOT to PGND, 40 V (< 50 ns) max.
(3) The specification value indicates “AC voltage” is VBOOT to VPHASE, 8 V (< 20 ns) max.
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL PARAMETER CONDITIONS LIMIT UNIT
Input voltage VIN -0.3 to +28
V
Control logic supply voltage VCIN -0.3 to +7
Drive supply voltage VDRV -0.3 to +7
Switch node (DC voltage) VSWH
-0.3 to +28
Switch node (AC voltage) (1) -7 to +33
BOOT voltage (DC voltage) VBOOT
35
BOOT voltage (AC voltage) (2) 40
BOOT to PHASE (DC voltage) VBOOT-PHASE
-0.3 to +7
BOOT to PHASE (AC voltage) (3) -0.3 to +8
All logic inputs and outputs
(PWM, DSBL#, and THWn) -0.3 to VCIN + 0.3
Max. operating junction temperature TJ150
°CAmbient temperature TA-40 to +125
Storage temperature Tstg -65 to +150
Electrostatic discharge protection Human body model, JESD22-A114 3000 V
Charged device model, JESD22-C101 1000
RECOMMENDED OPERATING RANGE
ELECTRICAL PARAMETER MINIMUM TYPICAL MAXIMUM UNIT
Input voltage (VIN)4.5-24
V
Drive supply voltage (VDRV) 4.555.5
Control logic supply voltage (VCIN) 4.555.5
BOOT to PHASE (VBOOT-PHASE, DC voltage) 4 4.5 5.5
Thermal resistance from junction to ambient - 10.6 - °C/W
Thermal resistance from junction to case - 1.6 -
= Pin 1 Indicator
P/N = Part Number Code
= Siliconix Logo
= ESD Symbol
F = Assembly Factory Code
Y = Year Code
WW = Week Code
LL = Lot Code
F Y W W
P/N
LL
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SiC632, SiC632A
www.vishay.com Vishay Siliconix
S19-0567-Rev. D, 22-Jul-2019 4Document Number: 62992
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ELECTRICAL SPECIFICATIONS
(DSBL# = ZCD_EN# = 5 V, VIN = 12 V, VDRV and VCIN = 5 V, TA = 25 °C)
PARAMETER SYMBOL TEST CONDITION LIMITS UNIT
MIN. TYP. MAX.
POWER SUPPLY
Control logic supply current IVCIN
VDSBL# = 0 V, no switching, VPWM = FLOAT - 10 -
μAVDSBL# = 5 V, no switching, VPWM = FLOAT - 300 -
VDSBL# = 5 V, fS = 300 kHz, D = 0.1 - 525 -
Drive supply current IVDRV
fS = 300 kHz, D = 0.1 - 10 15 mA
fS = 1 MHz, D = 0.1 - 35 -
VDSBL# = 0 V, no switching - 15 - μA
VDSBL# = 5 V, no switching - 55 -
BOOTSTRAP SUPPLY
Bootstrap diode forward voltage VFIF = 2 mA 0.4 V
PWM CONTROL INPUT (SiC632)
Rising threshold VTH_PWM_R 3.4 3.8 4.2
V
Falling threshold VTH_PWM_F 0.72 0.9 1.1
Tri-state voltage VTRI VPWM = FLOAT - 2.3 -
Tri-state rising threshold VTRI_TH_R 0.9 1.15 1.38
Tri-state falling threshold VTRI_TH_F 33.33.6
Tri-state rising threshold hysteresis VHYS_TRI_R - 225 - mV
Tri-state falling threshold hysteresis VHYS_TRI_F - 325 -
PWM input current IPWM
VPWM = 5 V - - 350 μA
VPWM = 0 V - - -350
PWM CONTROL INPUT (SiC632A)
Rising threshold VTH_PWM_R 2.3 2.45 2.7
V
Falling threshold VTH_PWM_F 0.72 0.9 1.1
Tri-state Voltage VTRI VPWM = FLOAT - 1.8 -
Tri-state rising threshold VTRI_TH_R 0.9 1.15 1.38
Tri-state falling threshold VTRI_TH_F 1.95 2.2 2.45
Tri-state rising threshold hysteresis VHYS_TRI_R - 250 - mV
Tri-state falling threshold hysteresis VHYS_TRI_F - 300 -
PWM input current IPWM
VPWM = 3.3 V - - 225 μA
VPWM = 0 V - - -225
TIMING SPECIFICATIONS
Tri-state to GH/GL rising
propagation delay tPD_TRI_R
No load, see fig. 4
-30-
ns
Tri-state hold-off time tTSHO - 130 -
GH - turn off propagation delay tPD_OFF_GH -15-
GH - turn on propagation delay
(dead time rising) tPD_ON_GH -10-
GL - turn off propagation delay tPD_OFF_GL -13-
GL - turn on propagation delay
(dead time falling) tPD_ON_GL -10-
DSBL# Lo to GH/GL falling
propagation delay tPD_DSBL#_F Fig. 5 - 15 -
PWM minimum on-time tPWM_ON_MIN 30 - -
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Notes
(1) Typical limits are established by characterization and are not production tested
(2) Guaranteed by design
DETAILED OPERATIONAL DESCRIPTION
PWM Input with Tri-state Function
The PWM input receives the PWM control signal from the VR
controller IC. The PWM input is designed to be compatible
with standard controllers using two state logic (H and L) and
advanced controllers that incorporate tri-state logic (H, L
and tri-state) on the PWM output. For two state logic, the
PWM input operates as follows. When PWM is driven above
VPWM_TH_R the low side is turned OFF and the high side is
turned ON. When PWM input is driven below VPWM_TH_F the
high side is turned OFF and the low side is turned ON. For
tri-state logic, the PWM input operates as previously stated
for driving the MOSFETs when PWM is logic high and logic
low. However, there is a third state that is entered as the
PWM output of tri-state compatible controller enters its high
impedance state during shut-down. The high impedance
state of the controller’s PWM output allows the SiC632 and
SiC632A to pull the PWM input into the tri-state region (see
definition of PWM logic and Tri-State, fig. 4). If the PWM
input stays in this region for the Tri-state Hold-Off Period,
tTSHO, both high side and low side MOSFETs are turned
OFF. The function allows the VR phase to be disabled
without negative output voltage swing caused by inductor
ringing and saves a Schottky diode clamp. The PWM and
tri-state regions are separated by hysteresis to prevent false
triggering. The SiC632A incorporates PWM voltage
thresholds that are compatible with 3.3 V logic and the
SiC632 thresholds are compatible with 5 V logic.
Disable (DSBL#)
In the low state, the DSBL# pin shuts down the driver IC and
disables both high side and low side MOSFETs. In this state,
standby current is minimized. If DSBL# is left unconnected,
an internal pull-down resistor will pull the pin to CGND and
shut down the IC.
Diode Emulation Mode (ZCD_EN#)
When ZCD_EN# pin is driven below VIL_ZCD_EN#. diode
emulation mode is enabled. If the PWM signal switches
below VTH_PWM_F then the LS MOSFET is under control of
the ZCD (zero crossing detect) comparator. If, after the
internal blanking delay, the inductor current becomes less
than or = 0 the low side is turned OFF. Light load efficiency
is improved by avoiding discharge of output capacitors. If
both high side and low side MOSFETs are required to be
turned OFF, regardless of inductor current, the PWM input
should be tri-stated.
Thermal Shutdown Warning (THWn)
The THWn pin is an open drain signal that flags the presence
of excessive junction temperature. Connect with a
maximum of 20 k, to VCIN. An internal temperature sensor
detects the junction temperature. The temperature
threshold is 160 °C. When this junction temperature is
exceeded the THWn flag is set. When the junction
temperature drops below 135 °C the device will clear the
THWn signal. The SiC632 and SiC632A do not stop
operation when the flag is set. The decision to shutdown
must be made by an external thermal control function.
Voltage Input (VIN)
This is the power input to the drain of the high side power
MOSFET. This pin is connected to the high power
intermediate BUS rail.
DSBL# ZCD_EN# INPUT
DSBL# logic input voltage VIH_DSBL# Input logic high 2 - -
V
VIL_DSBL# Input logic low - - 0.8
ZCD_EN# logic input voltage VIH_ZCD_EN# Input logic high 2 - -
VIL_ZCD_EN# Input logic low - - 0.8
PROTECTION
Under voltage lockout VUVLO
VCIN rising, on threshold - 3.7 4.1 V
VCIN falling, off threshold 2.7 3.1 -
Under voltage lockout hysteresis VUVLO_HYST - 575 - mV
THWn flag set (2) TTHWn_SET - 160 -
°CTHWn flag clear (2) TTHWn_CLEAR - 135 -
THWn flag hysteresis (2) TTHWn_HYST -25-
THWn output low VOL_THWn ITHWn = 2 mA - 0.02 - V
ELECTRICAL SPECIFICATIONS
(DSBL# = ZCD_EN# = 5 V, VIN = 12 V, VDRV and VCIN = 5 V, TA = 25 °C)
PARAMETER SYMBOL TEST CONDITION LIMITS UNIT
MIN. TYP. MAX.
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Switch Node (VSWH and PHASE)
The switch node, VSWH, is the circuit power stage output.
This is the output applied to the power inductor and output
filter to deliver the output for the buck converter. The PHASE
pin is internally connected to the switch node VSWH. This pin
is to be used exclusively as the return pin for the BOOT
capacitor. A 20 k resistor is connected between GH
(the high side gate) and PHASE to provide a discharge path
for the HS MOSFET in the event that VCIN goes to zero while
VIN is still applied.
Ground Connections (CGND and PGND)
PGND (power ground) should be externally connected
to CGND (signal ground). The layout of the printed circuit
board should be such that the inductance separating CGND
and PGND is minimized. Transient differences due to
inductance effects between these two pins should not
exceed 0.5 V
Control and Drive Supply Voltage Input (VDRV, VCIN)
VCIN is the bias supply for the gate drive control IC. VDRV is
the bias supply for the gate drivers. It is recommended to
separate these pins through a resistor. This creates a low
pass filtering effect to avoid coupling of high frequency gate
drive noise into the IC.
Bootstrap Circuit (BOOT)
The internal bootstrap diode and an external bootstrap
capacitor form a charge pump that supplies voltage to the
BOOT pin. An integrated bootstrap diode is incorporated so
that only an external capacitor is necessary to complete the
bootstrap circuit. Connect a boot strap capacitor with one
leg tied to BOOT pin and the other tied to PHASE pin.
Shoot-Through Protection and Adaptive Dead Time
The SiC632 and SiC632A have an internal adaptive logic to
avoid shoot through and optimize dead time. The shoot
through protection ensures that both high side and low side
MOSFETs are not turned ON at the same time. The adaptive
dead time control operates as follows. The high side and low
side gate voltages are monitored to prevent the MOSFET
turning ON from tuning ON until the other MOSFET's gate
voltage is sufficiently low (< 1 V). Built in delays also ensure
that one power MOSFET is completely OFF, before the other
can be turned ON. This feature helps to adjust dead time as
gate transitions change with respect to output current and
temperature.
Under Voltage Lockout (UVLO)
During the start up cycle, the UVLO disables the gate
drive holding high side and low side MOSFET gates low
until the supply voltage rail has reached a point at which
the logic circuitry can be safely activated. The SiC632,
SiC632A also incorporates logic to clamp the gate drive
signals to zero when the UVLO falling edge triggers the
shutdown of the device. As an added precaution, a 20 k
resistor is connected between GH (the high side gate) and
PHASE to provide a discharge path for the HS MOSFET.
FUNCTIONAL BLOCK DIAGRAM
Fig. 3 - SiC632 and SiC632A Functional Block Diagram
DISB#
20K
VSWH
VSWH
GL
+
-
GL
+
-
ZCD_EN#
Thermal monitor
& warning
UVLO
V
CIN
PWM logic
control &
state
machine
Anti-cross
conduction
control
logic
BOOT
THWn V
IN
PWM
C
GND
V
CIN
V
ref
= 1 V
V
ref
= 1 V
P
GND
PHASE
V
DRV
V
DRV
P
GND
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PWM TIMING DIAGRAM
Fig. 4 - Definition of PWM Logic and Tri-state
DSBL# PROPAGATION DELAY
Fig. 5 - DSBL# Falling Propagation Delay
DEVICE TRUTH TABLE
DSBL# ZCD_EN# PWM GH GL
Open X X L L
LXXLL
HLLL
H, IL > 0 A
L, IL < 0 A
HLHHL
HLTri-stateLL
HHL LH
HHHHL
HHTri-stateL L
VTH_PWM_R
VTH_PWM_F
VTH_TRI_R
VTH_TRI_F
PWM
GH
GL
tPD_OFF_GLtTSHO
tPD_ON_GHtPD_OFF_GH
tPD_ON_GL
tTSHO
tPD_TRI_R
tPD_TRI_R
PWM
DSBL#
GH
GL
DSBL#Low to GH Falling Propagation Delay
t
DSBL# Low to GL Falling Propagation Delay
PWM
DSBL#
GH
GL
t
Disable
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ELECTRICAL CHARACTERISTICS
Test condition: VIN = 13 V, DSBL# = VDRV = VCIN = 5 V, ZCD_EN# = 5 V, VOUT = 1 V, LOUT = 250 nH (DCR = 0.32 m), TA = 25 °C,
natural convection cooling (All power loss and normalized power loss curves show SiC632 and SiC632A losses only unless otherwise stated)
Fig. 6 - Efficiency vs. Output Current (VIN = 12.6 V)
Fig. 7 - Power Loss vs. Switching Frequency (VIN = 12.6 V)
Fig. 8 - Efficiency vs. Output Current (VIN = 9 V)
Fig. 9 - Safe Operating Area
Fig. 10 - Power Loss vs. Output Current (VIN = 12.6 V)
Fig. 11 - Efficiency vs. Output Current (VIN = 19 V)
62
66
70
74
78
82
86
90
94
0 5 10 15 20 25 30 35 40 45 50
Efficiency (%)
Output Current, IOUT (A)
Complete converter efficiency
PIN = [(VIN x IIN) + 5 V x (IVDRV + IVCIN)]
POUT = VOUT x IOUT, measured at output capacitor
1 MHz
750 kHz
500 kHz
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
200 300 400 500 600 700 800 900 1000 1100
Power Loss, PL(W)
Switching Frequency, fs (KHz)
IOUT = 25A
62
66
70
74
78
82
86
90
94
98
0 5 10 15 20 25 30 35 40 45 50
Efficiency (%)
Output Current, IOUT (A)
Complete converter efficiency
PIN = [(VIN x IIN) + 5 V x (IVDRV + IVCIN)]
POUT = VOUT x IOUT, measured at output capacitor
1 MHz
750 kHz
500 kHz
15
20
25
30
35
40
45
50
55
0 153045607590105120135150
Output Current, IOUT (A)
PCB Temperature, TPCB (°C)
1 MHz
500 kHz
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
0 5 10 15 20 25 30 35 40 45
Power Loss, PL(W)
Output Current, IOUT (A)
750 kHz
1 MHz
500 kHz
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ELECTRICAL CHARACTERISTICS
Test condition: VIN = 13 V, DSBL# = VDRV = VCIN = 5 V, ZCD_EN# = 5 V, VOUT = 1 V, LOUT = 250 nH (DCR = 0.32 m), TA = 25 °C,
natural convection cooling (All power loss and normalized power loss curves show SiC632 and SiC632A losses only unless otherwise stated)
Fig. 12 - UVLO Threshold vs. Temperature
Fig. 13 - PWM Threshold vs. Temperature (SiC632A)
Fig. 14 - PWM Threshold vs. Temperature (SiC632)
Fig. 15 - Boot Diode Forward Voltage vs. Temperature
Fig. 16 - PWM Threshold vs. Driver Supply Voltage (SiC632A)
Fig. 17 - PWM Threshold vs. Driver Supply Voltage (SiC632)
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
-60 -40 -20 0 20 40 60 80 100 120 140
Control Logic Supply Voltage, VCIN (V)
Temperature (°C)
VUVLO_FALLING
VUVLO_RISING
4.2
0.40
0.75
1.10
1.45
1.80
2.15
2.50
2.85
3.20
-60 -40 -20 0 20 40 60 80 100 120 140
Control Logic Supply Voltage, VPWM (V)
Temperature (°C)
VTRI_TH_R
VTRI_TH_F
VTRI
VTH_PWM_R
VTH_PWM_F
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-60 -40 -20 0 20 40 60 80 100 120 140
Control Logic Supply Voltage, VPWM (V)
Temperature (°C)
VTRI_TH_R
VTRI_TH_F
VTRI
VTH_PWM_R
VTH_PWM_F
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
-60 -40 -20 0 20 40 60 80 100 120 140
BOOT Diode Forward Voltage, VF(V)
Temperature (°C)
IF= 2 mA
0.40
0.75
1.10
1.45
1.80
2.15
2.50
2.85
3.20
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
PWM Threshold Voltage, VPWM (V)
Driver Supply Voltage, VCIN (V)
VTH_PWM_F
VTH_PWM_R
VTRI_TH_F
VTRI_TH_R
V
TRI
0
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
5.00
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
PWM Threshold Voltage, VPWM (V)
Driver Supply Voltage, VCIN (V)
VTH_PWM_F
VTH_PWM_R
VTRI_TH_F
VTRI_TH_R
VTRI
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ELECTRICAL CHARACTERISTICS
Test condition: VIN = 13 V, DSBL# = VDRV = VCIN = 5 V, ZCD_EN# = 5 V, VOUT = 1 V, LOUT = 250 nH (DCR = 0.32 m), TA = 25 °C,
natural convection cooling (All power loss and normalized power loss curves show SiC632 and SiC632A losses only unless otherwise stated)
Fig. 18 - DSBL# Threshold vs. Temperature
Fig. 19 - DSBL# vs. Driver Input Voltage
Fig. 20 - DSBL# Pull-Down Current vs. Temperature
Fig. 21 - ZCD_EN# Threshold vs. Driver Supply Voltage
Fig. 22 - Driver Shutdown Current vs. Temperature
Fig. 23 - Driver Supply Current vs. Temperature
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
-60 -40 -20 0 20 40 60 80 100 120 140
DSBL# Threshold Voltage, VDSBL# (V)
Temperature (°C)
VIL_DSBL#
VIH_DSBL#
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
DSBL# Threshold Voltage, VDSBL# (V)
Driver Supply Voltage, VCIN (V)
VIH_DSBL#
VIL_DSBL#
10.0
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
-60 -40 -20 0 20 40 60 80 100 120 140
DSBL# Pull-Down Current, IDSBL# (uA)
Temperature (°C)
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
2.20
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
ZCD_EN# Threshold Voltage, VZCD_EN# (V)
Driver Supply Voltage, VCIN (V)
VIH_ZCD_EN#_R
VIL_ZCD_EN#_F
0
10
20
30
40
50
60
70
80
-60 -40 -20 0 20 40 60 80 100 120 140
Driver Supply Current, IVDVR & IVCIN (V)
Temperature (°C)
VDSBL# = 0 V
310
320
330
340
350
360
370
380
390
-60 -40 -20 0 20 40 60 80 100 120 140
Driver Supply Current, IVDVR & IVCIN (V)
Temperature (°C)
VPWM = FLOAT
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PCB LAYOUT RECOMMENDATIONS
Step 1: VIN/GND Planes and Decoupling
1. Layout VIN and PGND planes as shown above
2. Ceramic capacitors should be placed right between VIN
and PGND, and very close to the device for best
decoupling effect
3. Difference values / packages of ceramic capacitors
should be used to cover entire decoupling spectrum e.g.
1210, 0805, 0603 and 0402
4. Smaller capacitance value, closer to device VIN pin(s)
- better high frequency noise absorbing
Step 2: VSWH Plane
1. Connect output inductor to DrMOS with large plane to
lower the resistance
2. If any snubber network is required, place the
components as shown above and the network can be
placed at bottom
Step 3: VCIN/VDRV Input Filter
1. The VCIN/VDRV input filter ceramic cap should be placed
very close to IC. It is recommended to connect two caps
separately.
2. CVCIN cap should be placed between pin 3 and pin 4
(CGND of driver IC) to achieve best noise filtering.
3. CVDRV cap should be placed between pin 28 (PGND of
driver IC) and pin 29 to provide maximum instantaneous
driver current for low side MOSFET during switching
cycle
4. For connecting CVCIN analog ground, it is recommended
to use large plane to reduce parasitic inductance.
Step 4: BOOT Resistor and Capacitor Placement
1. These components need to be placed very close to IC,
right between PHASE (pin 7) and BOOT (pin 5).
2. To reduce parasitic inductance, chip size 0402 can be
used.
VIN
VSWH
PGND
VIN plane
PGND plane
PGND Plane
VSWH
Snubber
VSWH
PGND plane
C
GND
CVCIN
CVDRV
P
G
N
D
Cboot
Rboot
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Step 5: Signal Routing
1. Route the PWM / ZCD_EN# / DSBL# / THWn signal
traces out of the top left corner next DrMOS pin 1.
2. PWM signal is very important signal, both signal and
return traces need to pay special attention of not letting
this trace cross any power nodes on any layer.
3. It is best to “shield” traces form power switching nodes,
e.g. VSWH, to improve signal integrity.
4. GL (pin 27) has been connected with GL pad internally
and does not need to connect externally.
Step 6: Adding Thermal Relief Vias
1. Thermal relief vias can be added on the VIN and PGND
pads to utilize inner layers for high current and thermal
dissipation.
2. To achieve better thermal performance, additional vias
can be put on VIN plane and PGND plane.
3. VSWH pad is a noise source and not recommended to put
vias on this plane.
4. 8 mil drill for pads and 10 mils drill for plane can be the
optional via size. Vias on pad may drain solder during
assembly and cause assembly issue. Please consult
with the assembly house for guideline.
Step 7: Ground Connection
1. It is recommended to make single connection between
CGND and PGND and this connection can be done on top
layer.
2. It is recommended to make the whole inner 1 layer (next
to top layer) ground plane and separate them into CGND
and PGND plane.
3. These ground planes provide shielding between noise
source on top layer and signal trace on bottom layer.
PGND
CGND
CGND
VIN plane
PGND
plane
VSWH
PGND
VIN
CGND
V
SWH
PGND
CGND
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Multi-Phases VRPower PCB Layout
Following is an example for 6 phase layout. As can be seen, all the VRPower stages are lined in X-direction compactly with
decoupling caps next to them. The inductors are placed as close as possible to the SiC632 and SiC632A to minimize the PCB
copper loss. Vias are applied on all PADs (VIN, PGND, CGND) of the SiC632 and SiC632A to ensure that both electrical and thermal
performance are excellent. Large copper planes are used for all the high current loops, such as VIN, VSWH, VOUT and PGND. These
copper planes are duplicated in other layers to minimize the inductance and resistance. All the control signals are routed from
the SiC632 and SiC632A to a controller placed to the north of the power stage through inner layers to avoid the overlap of high
current loops. This achieves a compact design with the output from the inductors feeding a load located to the south of the
design as shown in the figure.
Fig. 24 - Multi - Phase VRPower Layout Top View
Fig. 25 - Multi - Phase VRPower Layout Bottom View
V
OUT
PGND
V
IN
VIN
PGND
VOUT
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Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?62992.
PRODUCT SUMMARY
Part number SiC632 SiC632A
Description 50 A, 4.5 V to 24 V, 5 V PWM, VRPower with ZCD 50 A, 4.5 V to 24 V, 3.3 V PWM, VRPower with ZCD
Input voltage min. (V) 4.5 4.5
Input voltage max. (V) 24 24
Current rating (A) 50 50
Switch frequency max. (kHz) 1500 1500
Enable (yes / no) Yes Yes
Monitoring features None None
Protection LS-UVLO, THW LS-UVLO, THW
Light load mode ZCD ZCD
Peak efficiency (%) 95 95
Pulse-width modulation (V) 5 3.3
Package type PowerPAK MLP55-31L PowerPAK MLP55-31L
Package size (W, L, H) (mm) 5 x 5 x 0.7 5 x 5 x 0.7
Status code 2 2
Product type VRPower (DrMOS) VRPower (DrMOS)
Applications Computer, industrial, networking Computer, industrial, networking
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PowerPAK® MLP55-31L Case Outline
DIM.
MILLIMETERS INCHES
MIN. NOM. MAX. MIN. NOM. MAX.
A (8) 0.70 0.75 0.80 0.027 0.029 0.031
A1 0.00 - 0.05 0.000 - 0.002
A2 0.20 ref. 0.008 ref.
b (4) 0.20 0.25 0.30 0.008 0.010 0.012
D 4.90 5.00 5.10 0.193 0.196 0.200
e 0.50 BSC 0.019 BSC
E 4.90 5.00 5.10 0.193 0.196 0.200
L 0.35 0.40 0.45 0.013 0.015 0.017
N (3) 32 32
Nd (3) 88
Ne (3) 88
D2-1 0.98 1.03 1.08 0.039 0.041 0.043
D2-2 0.98 1.03 1.08 0.039 0.041 0.043
D2-3 1.87 1.92 1.97 0.074 0.076 0.078
D2-4 0.30 BSC 0.012 BSC
D2-5 1.00 1.05 1.10 0.039 0.041 0.043
E2-1 1.27 1.32 1.37 0.050 0.052 0.054
E2-2 1.93 1.98 2.03 0.076 0.078 0.080
E2-3 3.75 3.80 3.82 0.148 0.150 0.152
E2-4 0.45 BSC 0.018 BSC
F1 0.20 BSC 0.008 BSC
F2 0.20 BSC 0.008 BSC
K1 0.67 BSC 0.026 BSC
K2 0.22 BSC 0.008 BSC
K3 1.25 BSC 0.049 BSC
K4 0.05 BSC 0.002 BSC
K5 0.38 BSC 0.015 BSC
K6 0.12 BSC 0.005 BSC
by marking
E
Pin 1 dot
Top view
D
MLP55-31L
(5 mm x 5 mm)
E2- 1
(Nd-1) x e
ref.
Bottom view
Side view
e
D2- 3 D2- 2
E2- 2
A0.10 C A
2 x
0.10 C B
2 x
0.08 C
C
A
A2
A1
B
(Nd-1) xe
ref.
K7
56
D2- 1
E2- 3
4
0.10 m C A B
D2-4
E2-4
K8
b
L
K3
K10
K1
K2
K4
K5
K6
K9
D2-5
K11
K12
F1
F2
1
9
8
1
16
23
31
24
15 9
8
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Notes
1. Use millimeters as the primary measurement
2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994
3. N is the number of terminals,
Nd is the number of terminals in X-direction, and
Ne is the number of terminals in Y-direction
4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip
5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body
6. Exact shape and size of this feature is optional
7. Package warpage max. 0.08 mm
8. Applied only for terminals
K7 0.40 BSC 0.016 BSC
K8 0.40 BSC 0.016 BSC
K9 0.40 BSC 0.016 BSC
K10 0.85 BSC 0.033 BSC
K11 0.40 BSC 0.016 BSC
K12 0.40 BSC 0.016 BSC
ECN: T16-0644-Rev. E, 24-Oct-16
DWG: 6025
DIM.
MILLIMETERS INCHES
MIN. NOM. MAX. MIN. NOM. MAX.
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Recommended Land Pattern
PowerPAK® MLP55-31L for SiC620, SiC620A
Land pattern for MLP55-31L
Top side transparent view
(not bottom view)
All dimensions in millimeters
1.75
0.75
24
1
0.3
0.3
0.5
1.15
1.13
31
1.35
5
0.57
2.02
23
16
0.75
15
0.5
0.18
0.35
0.35
0.65
0.5
9
0.35
0.3
1
5
0.35
0.15
1.42
0.33
0.07
0.42.08
2.15
3.05
0.3
0.33
0.75
1.6
0.85
3.5
0.3
0.65
0.58 0.5
8
(D2-4)
3.4
(D2-1)
1.03
(D2-5)
1.05 24
31
(K2) 0.22
(K1) 0.67
(D3) 0.3
(D2-2)
1.03
(D2-3)
1.92
915
16
23
8
1
24
31
915
16
23
8
1
(L)
0.4
(L)
0.4
(E2-2)
1.32
0.5 (e)
(E2-3)
1.98
(E3)
0.45
(E2-1)
4.2
(b)
0.25
33
33
32
35 Land pattern for MLP55-31L
Component for MLP55-31L
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RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a
particular product with the properties described in the product specification is suitable for use in a particular application.
Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s
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including but not limited to the warranty expressed therein.
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